[u-boot.git] / include / configs / s32v234evb.h

/*
 * (C) Copyright 2015-2016 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 *
 * Configuration settings for the Freescale S32V234 EVB board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
#endif

#include <asm/arch/imx-regs.h>

#define CONFIG_S32V234
#define CONFIG_DM

/* Config GIC */
#define CONFIG_GICV2
#define GICD_BASE 0x7D001000
#define GICC_BASE 0x7D002000

#define CONFIG_REMAKE_ELF
#undef CONFIG_RUN_FROM_IRAM_ONLY

#define CONFIG_RUN_FROM_DDR1
#undef CONFIG_RUN_FROM_DDR0

/* Run by default from DDR1  */
#ifdef CONFIG_RUN_FROM_DDR0
#define DDR_BASE_ADDR		0x80000000
#else
#define DDR_BASE_ADDR		0xC0000000
#endif

#define CONFIG_MACH_TYPE		4146

#define CONFIG_SKIP_LOWLEVEL_INIT

/* Config CACHE */
#define CONFIG_CMD_CACHE

#define CONFIG_SYS_FULL_VA

/* Enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG

/* SMP Spin Table Definitions */
#define CPU_RELEASE_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x7fff0)

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY               (1000000000)	/* 1000MHz */
#define CONFIG_SYS_FSL_ERRATUM_A008585

/* Size of malloc() pool */
#ifdef CONFIG_RUN_FROM_IRAM_ONLY
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1 * 1024 * 1024)
#else
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#endif

#define CONFIG_DM_SERIAL
#define CONFIG_FSL_LINFLEXUART
#define LINFLEXUART_BASE		LINFLEXD0_BASE_ADDR

#define CONFIG_DEBUG_UART_LINFLEXUART
#define CONFIG_DEBUG_UART_BASE		LINFLEXUART_BASE

/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_UART_PORT		(1)
#define CONFIG_BAUDRATE				115200

#undef CONFIG_CMD_IMLS

#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM	1

#define CONFIG_CMD_MMC
/* #define CONFIG_CMD_EXT2 EXT2 Support */

#if 0

/* Ethernet config */
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE            ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE     RMII
#define CONFIG_FEC_MXC_PHYADDR  0
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#endif

#if 0				/* Disable until the I2C driver will be updated */

/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE		I2C0_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED		100000
#endif

#if 0				/* Disable until the FLASH will be implemented */
#define CONFIG_SYS_USE_NAND
#endif

#ifdef CONFIG_SYS_USE_NAND
/* Nand Flash Configs */
#define	CONFIG_CMD_NAND
#define CONFIG_JFFS2_NAND
#define MTD_NAND_FSL_NFC_SWECC 1
#define CONFIG_NAND_FSL_NFC
#define CONFIG_SYS_NAND_BASE		0x400E0000
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS			CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_SELECT_DEVICE
#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
#endif

#define CONFIG_LOADADDR			0xC307FFC0
#define CONFIG_BOOTARGS			"console=ttyLF0 root=/dev/ram rw"

#define CONFIG_CMD_ENV
#define CONFIG_EXTRA_ENV_SETTINGS \
	"boot_scripts=boot.scr.uimg boot.scr\0" \
	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
	"console=ttyLF0,115200\0" \
	"fdt_file=s32v234-evb.dtb\0" \
	"fdt_high=0xffffffff\0" \
	"initrd_high=0xffffffff\0" \
	"fdt_addr_r=0xC2000000\0" \
	"kernel_addr_r=0xC307FFC0\0" \
	"ramdisk_addr_r=0xC4000000\0" \
	"ramdisk=rootfs.uimg\0"\
	"ip_dyn=yes\0" \
	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
	"update_sd_firmware_filename=u-boot.imx\0" \
	"update_sd_firmware=" \
		"if test ${ip_dyn} = yes; then " \
			"setenv get_cmd dhcp; " \
		"else " \
			"setenv get_cmd tftp; " \
		"fi; " \
		"if mmc dev ${mmcdev}; then "	\
			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
				"setexpr fw_sz ${filesize} / 0x200; " \
				"setexpr fw_sz ${fw_sz} + 1; "	\
				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
			"fi; "	\
		"fi\0" \
	"loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \
	"jtagboot=echo Booting using jtag...; " \
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	"jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \
		"run loaduimage; run loadramdisk; run loadfdt;"\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	"boot_net_usb_start=true\0" \
	BOOTENV

#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 1) \
	func(MMC, mmc, 0) \
	func(DHCP, dhcp, na)

#define CONFIG_BOOTCOMMAND \
	"run distro_bootcmd"

#include <config_distro_bootcmd.h>

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		"=> "
#undef CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		\
			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define CONFIG_CMDLINE_EDITING

#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START	(DDR_BASE_ADDR)
#define CONFIG_SYS_MEMTEST_END		(DDR_BASE_ADDR + 0x7C00000)

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
#define CONFIG_SYS_HZ				1000

#define CONFIG_SYS_TEXT_BASE		0x3E800000	/* SDRAM */

#ifdef CONFIG_RUN_FROM_IRAM_ONLY
#define CONFIG_SYS_MALLOC_BASE		(DDR_BASE_ADDR)
#endif

/*
 * Stack sizes
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */

#if 0
/* Configure PXE */
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
#endif

/* Physical memory map */
/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			(DDR_BASE_ADDR)
#define PHYS_SDRAM_SIZE			(256 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH

#define CONFIG_ENV_SIZE			(8 * 1024)
#define CONFIG_ENV_IS_IN_MMC

#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV		0


#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

#endif
Commit	Line	Data
9702ec00 EP	1	/*
	2	* (C) Copyright 2015-2016 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*
	6	* Configuration settings for the Freescale S32V234 EVB board.
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#ifndef CONFIG_SPL_BUILD
	13	#include <config_distro_defaults.h>
	14	#endif
	15
	16	#include <asm/arch/imx-regs.h>
	17
	18	#define CONFIG_S32V234
	19	#define CONFIG_DM
	20
9702ec00 EP	21	/* Config GIC */
	22	#define CONFIG_GICV2
	23	#define GICD_BASE 0x7D001000
	24	#define GICC_BASE 0x7D002000
	25
	26	#define CONFIG_REMAKE_ELF
	27	#undef CONFIG_RUN_FROM_IRAM_ONLY
	28
	29	#define CONFIG_RUN_FROM_DDR1
	30	#undef CONFIG_RUN_FROM_DDR0
	31
	32	/* Run by default from DDR1 */
	33	#ifdef CONFIG_RUN_FROM_DDR0
	34	#define DDR_BASE_ADDR 0x80000000
	35	#else
	36	#define DDR_BASE_ADDR 0xC0000000
	37	#endif
	38
	39	#define CONFIG_MACH_TYPE 4146
	40
	41	#define CONFIG_SKIP_LOWLEVEL_INIT
	42
	43	/* Config CACHE */
	44	#define CONFIG_CMD_CACHE
	45
	46	#define CONFIG_SYS_FULL_VA
	47
	48	/* Enable passing of ATAGs */
	49	#define CONFIG_CMDLINE_TAG
	50
	51	/* SMP Spin Table Definitions */
	52	#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
	53
	54	/* Generic Timer Definitions */
	55	#define COUNTER_FREQUENCY (1000000000) /* 1000MHz */
	56	#define CONFIG_SYS_FSL_ERRATUM_A008585
	57
	58	/* Size of malloc() pool */
	59	#ifdef CONFIG_RUN_FROM_IRAM_ONLY
	60	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 * 1024 * 1024)
	61	#else
	62	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
	63	#endif
9702ec00 EP	64
	65	#define CONFIG_DM_SERIAL
	66	#define CONFIG_FSL_LINFLEXUART
	67	#define LINFLEXUART_BASE LINFLEXD0_BASE_ADDR
	68
	69	#define CONFIG_DEBUG_UART_LINFLEXUART
	70	#define CONFIG_DEBUG_UART_BASE LINFLEXUART_BASE
	71
	72	/* Allow to overwrite serial and ethaddr */
	73	#define CONFIG_ENV_OVERWRITE
	74	#define CONFIG_SYS_UART_PORT (1)
	75	#define CONFIG_BAUDRATE 115200
	76
	77	#undef CONFIG_CMD_IMLS
	78
9702ec00 EP	79	#define CONFIG_FSL_ESDHC
	80	#define CONFIG_FSL_USDHC
	81	#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR
	82	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	83
9702ec00	84	#define CONFIG_CMD_MMC
9702ec00	85	/* #define CONFIG_CMD_EXT2 EXT2 Support */
9702ec00 EP	86
	87	#if 0
	88
	89	/* Ethernet config */
	90	#define CONFIG_CMD_PING
9702ec00 EP	91	#define CONFIG_CMD_MII
	92	#define CONFIG_FEC_MXC
	93	#define CONFIG_MII
	94	#define IMX_FEC_BASE ENET_BASE_ADDR
	95	#define CONFIG_FEC_XCV_TYPE RMII
	96	#define CONFIG_FEC_MXC_PHYADDR 0
	97	#define CONFIG_PHYLIB
	98	#define CONFIG_PHY_MICREL
	99	#endif
	100
	101	#if 0 /* Disable until the I2C driver will be updated */
	102
	103	/* I2C Configs */
	104	#define CONFIG_CMD_I2C
	105	#define CONFIG_HARD_I2C
	106	#define CONFIG_I2C_MXC
	107	#define CONFIG_SYS_I2C_BASE I2C0_BASE_ADDR
	108	#define CONFIG_SYS_I2C_SPEED 100000
	109	#endif
	110
	111	#if 0 /* Disable until the FLASH will be implemented */
	112	#define CONFIG_SYS_USE_NAND
	113	#endif
	114
	115	#ifdef CONFIG_SYS_USE_NAND
	116	/* Nand Flash Configs */
	117	#define CONFIG_CMD_NAND
	118	#define CONFIG_JFFS2_NAND
	119	#define MTD_NAND_FSL_NFC_SWECC 1
	120	#define CONFIG_NAND_FSL_NFC
	121	#define CONFIG_SYS_NAND_BASE 0x400E0000
	122	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	123	#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
	124	#define CONFIG_SYS_NAND_SELECT_DEVICE
	125	#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
	126	#endif
	127
9702ec00 EP	128	#define CONFIG_LOADADDR 0xC307FFC0
	129	#define CONFIG_BOOTARGS "console=ttyLF0 root=/dev/ram rw"
	130
	131	#define CONFIG_CMD_ENV
	132	#define CONFIG_EXTRA_ENV_SETTINGS \
	133	"boot_scripts=boot.scr.uimg boot.scr\0" \
	134	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
	135	"console=ttyLF0,115200\0" \
	136	"fdt_file=s32v234-evb.dtb\0" \
	137	"fdt_high=0xffffffff\0" \
	138	"initrd_high=0xffffffff\0" \
	139	"fdt_addr_r=0xC2000000\0" \
	140	"kernel_addr_r=0xC307FFC0\0" \
	141	"ramdisk_addr_r=0xC4000000\0" \
	142	"ramdisk=rootfs.uimg\0"\
	143	"ip_dyn=yes\0" \
	144	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
	145	"update_sd_firmware_filename=u-boot.imx\0" \
	146	"update_sd_firmware=" \
	147	"if test ${ip_dyn} = yes; then " \
	148	"setenv get_cmd dhcp; " \
	149	"else " \
	150	"setenv get_cmd tftp; " \
	151	"fi; " \
	152	"if mmc dev ${mmcdev}; then " \
	153	"if ${get_cmd} ${update_sd_firmware_filename}; then " \
	154	"setexpr fw_sz ${filesize} / 0x200; " \
	155	"setexpr fw_sz ${fw_sz} + 1; " \
	156	"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
	157	"fi; " \
	158	"fi\0" \
	159	"loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \
	160	"jtagboot=echo Booting using jtag...; " \
	161	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	162	"jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \
	163	"run loaduimage; run loadramdisk; run loadfdt;"\
	164	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	165	"boot_net_usb_start=true\0" \
	166	BOOTENV
	167
	168	#define BOOT_TARGET_DEVICES(func) \
	169	func(MMC, mmc, 1) \
	170	func(MMC, mmc, 0) \
	171	func(DHCP, dhcp, na)
	172
	173	#define CONFIG_BOOTCOMMAND \
	174	"run distro_bootcmd"
	175
	176	#include <config_distro_bootcmd.h>
	177
	178	/* Miscellaneous configurable options */
	179	#define CONFIG_SYS_LONGHELP /* undef to save memory */
9702ec00 EP	180	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	181	#define CONFIG_SYS_PROMPT "=> "
	182	#undef CONFIG_AUTO_COMPLETE
	183	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	184	#define CONFIG_SYS_PBSIZE \
	185	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	186	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	187	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	188	#define CONFIG_CMDLINE_EDITING
	189
	190	#define CONFIG_CMD_MEMTEST
	191	#define CONFIG_SYS_MEMTEST_START (DDR_BASE_ADDR)
	192	#define CONFIG_SYS_MEMTEST_END (DDR_BASE_ADDR + 0x7C00000)
	193
	194	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	195	#define CONFIG_SYS_HZ 1000
	196
	197	#define CONFIG_SYS_TEXT_BASE 0x3E800000 /* SDRAM */
	198
	199	#ifdef CONFIG_RUN_FROM_IRAM_ONLY
	200	#define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR)
	201	#endif
	202
	203	/*
	204	* Stack sizes
	205	* The stack sizes are set up in start.S using the settings below
	206	*/
	207	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	208
	209	#if 0
	210	/* Configure PXE */
9702ec00 EP	211	#define CONFIG_BOOTP_PXE
	212	#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
	213	#endif
	214
	215	/* Physical memory map */
	216	/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */
	217	#define CONFIG_NR_DRAM_BANKS 1
	218	#define PHYS_SDRAM (DDR_BASE_ADDR)
	219	#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
	220
	221	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	222	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	223	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	224
	225	#define CONFIG_SYS_INIT_SP_OFFSET \
	226	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	227	#define CONFIG_SYS_INIT_SP_ADDR \
	228	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	229
	230	/* FLASH and environment organization */
	231	#define CONFIG_SYS_NO_FLASH
	232
	233	#define CONFIG_ENV_SIZE (8 * 1024)
	234	#define CONFIG_ENV_IS_IN_MMC
	235
	236	#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
	237	#define CONFIG_SYS_MMC_ENV_DEV 0
	238
	239
	240	#define CONFIG_BOOTP_BOOTFILESIZE
	241	#define CONFIG_BOOTP_BOOTPATH
	242	#define CONFIG_BOOTP_GATEWAY
	243	#define CONFIG_BOOTP_HOSTNAME
	244
	245	#endif