[u-boot.git] / include / configs / TOP860.h

/*
 * (C) Copyright 2003
 * EMK Elektronik GmbH <www.emk-elektronik.de>
 * Reinhard Meyer <[email protected]>
 *
 * Configuation settings for the TOP860 board.
 *
 * -----------------------------------------------------------------
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
/*
 * TOP860 is a simple module:
 * 16-bit wide FLASH on CS0	(2MB or more)
 * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
 * FEC with Am79C874 100-Base-T and Fiber Optic
 * Ports available, but we choose SMC1 for Console
 * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
 * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
 *
 * This config has been copied from MBX.h / MBX860T.h
 */
/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

/*-----------------------------------------------------------------------
 * CPU and BOARD type
 */
#define CONFIG_MPC860	1	/* This is a MPC860 CPU		*/
#define CONFIG_MPC860T	1	/* even better... an FEC!	*/
#define CONFIG_TOP860	1	/* ...on a TOP860 module	*/
#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#define	CONFIG_IDENT_STRING " EMK TOP860"

/*-----------------------------------------------------------------------
 * CLOCK settings
 */
#define	CONFIG_SYSCLK	49152000
#define	CFG_XTAL		32768
#define	CONFIG_EBDF		1
#define	CONFIG_COM		3
#define	CONFIG_RTC_MPC8xx

/*-----------------------------------------------------------------------
 * Physical memory map as defined by EMK
 */
#define CFG_IMMR		0xFFF00000	/* Internal Memory Mapped Register */
#define	CFG_FLASH_BASE	0x80000000	/* FLASH in final mapping */
#define	CFG_DRAM_BASE	0x00000000	/* DRAM in final mapping */
#define	CFG_FLASH_MAX	0x00400000	/* max FLASH to expect */
#define	CFG_DRAM_MAX	0x01000000	/* max DRAM to expect */

/*-----------------------------------------------------------------------
 * derived values
 */
#define	CFG_MF			(CONFIG_SYSCLK/CFG_XTAL)
#define	CFG_CPUCLOCK	CONFIG_SYSCLK
#define	CFG_BRGCLOCK	CONFIG_SYSCLK
#define	CFG_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)
#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
#define	CONFIG_8xx_GCLK_FREQ	CONFIG_SYSCLK

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CFG_FLASH_CFI

/*-----------------------------------------------------------------------
 * Command interpreter
 */
#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#define CONFIG_BAUDRATE		9600

/*
 * Allow partial commands to be matched to uniqueness.
 */
#define CFG_MATCH_PARTIAL_CMD


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_MII
#define CONFIG_CMD_BEDBUG


#define	CONFIG_AUTOSCRIPT		1
#define	CFG_LOADS_BAUD_CHANGE	1
#undef	CONFIG_LOADS_ECHO			/* NO echo on for serial download	*/


#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* Hush parse for U-Boot	*/

#ifdef	CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
 #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/*-----------------------------------------------------------------------
 * Memory Test Command
 */
#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

/*-----------------------------------------------------------------------
 * Environment handler
 * only the first 6k in EEPROM are available for user. Of that we use 256b
 */
#define	CONFIG_SOFT_I2C
#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
#define CONFIG_ENV_OFFSET		0x1000
#define CONFIG_ENV_SIZE		0x0700
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_FACT_OFFSET		0x1800
#define CFG_FACT_SIZE		0x0800
#define CFG_I2C_FACT_ADDR	0x57
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_SIZE 0x2000
#define	CFG_I2C_SPEED	100000
#define	CFG_I2C_SLAVE	0xFE
#define	CFG_EEPROM_PAGE_WRITE_DELAY_MS 12
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R

#if defined (CONFIG_SOFT_I2C)
#define	SDA	0x00010
#define	SCL	0x00020
#define __I2C_DIR	immr->im_cpm.cp_pbdir
#define __I2C_DAT	immr->im_cpm.cp_pbdat
#define __I2C_PAR	immr->im_cpm.cp_pbpar
#define	__I2C_ODR	immr->im_cpm.cp_pbodr
#define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
			  __I2C_ODR &= ~(SDA|SCL);	\
			  __I2C_DAT |= (SDA|SCL);	\
			  __I2C_DIR|=(SDA|SCL);	}
#define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
#define	I2C_SDA(x)	{ if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
#define	I2C_SCL(x)	{ if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
#define	I2C_DELAY	{ udelay(5); }
#define	I2C_ACTIVE	{ __I2C_DIR |= SDA; }
#define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }
#endif

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*-----------------------------------------------------------------------
 * defines we need to get FEC running
 */
#define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
#define CONFIG_FEC_ENET		1	/* Ethernet only via FEC	*/
#define	FEC_ENET		1	/* eth.c needs it that way... */
#define CFG_DISCOVER_PHY	1
#define CONFIG_MII		1
#define CONFIG_MII_INIT		1
#define CONFIG_PHY_ADDR		31

/*-----------------------------------------------------------------------
 * adresses
 */
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x80000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
#define CFG_INIT_VPD_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
#define CFG_INIT_SP_OFFSET	(CFG_INIT_VPD_OFFSET-8)

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/* Interrupt level assignments.
*/
#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/*-----------------------------------------------------------------------
 * Debug Enable Register
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER 0					/* used in start.S */

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
 *	12	MF		calculated	Multiplication factor
 *	4	0		0000
 *	1	SPLSS	0			System PLL lock status sticky
 *	1	TEXPS	1			Timer expired status
 *	1	0		0
 *	1	TMIST	0			Timers interrupt status
 *	1	0		0
 *	1	CSRC	0			Clock source (0=DFNH, 1=DFNL)
 *	2	LPM		00			Low-power modes
 *	1	CSR		0			Checkstop reset enable
 *	1	LOLRE	0			Loss-of-lock reset enable
 *	1	FIOPD	0			Force I/O pull down
 *	5	0		00000
 */
#define CFG_PLPRCR	(PLPRCR_TEXPS | ((CFG_MF-1)<<20))

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * set up SYPCR:
 *	16	SWTC	0xffff		Software watchdog timer count
 *	8	BMT		0xff		Bus monitor timing
 *	1	BME		1			Bus monitor enable
 *	3	0		000
 *	1	SWF		1			Software watchdog freeze
 *	1	SWE		0/1			Software watchdog enable
 *	1	SWRI	0/1			Software watchdog reset/interrupt select (1=HRESET)
 *	1	SWP		0/1			Software watchdog prescale (1=/2048)
 */
#if defined (CONFIG_WATCHDOG)
 #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
					 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
 #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * set up SIUMCR
 *	1	EARB	0			External arbitration
 *	3	EARP	000			External arbitration request priority
 *	4	0		0000
 *	1	DSHW	0			Data show cycles
 *	2	DBGC	00			Debug pin configuration
 *	2	DBPC	00			Debug port pins configuration
 *	1	0		0
 *	1	FRC		0			FRZ pin configuration
 *	1	DLK		0			Debug register lock
 *	1	OPAR	0			Odd parity
 *	1	PNCS	0			Parity enable for non memory controller regions
 *	1	DPC		0			Data parity pins configuration
 *	1	MPRE	0			Multiprocessor reservation enable
 *	2	MLRC	11			Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
 *	1	AEME	0			Async external master enable
 *	1	SEME	0			Sync external master enable
 *	1	BSC		0			Byte strobe configuration
 *	1	GB5E	0			GPL_B5 enable
 *	1	B2DD	0			Bank 2 double drive
 *	1	B3DD	0			Bank 3 double drive
 *	4	0		0000
 */
#define CFG_SIUMCR	(SIUMCR_MLRC11)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * set up SCCR (System Clock and Reset Control Register)
 *	1	0		0
 *	2	COM		11			Clock output module (00=full, 01=half, 11=off)
 *	3	0		000
 *	1	TBS		1			Timebase source (0=OSCCLK, 1=GCLK2)
 *	1	RTDIV	0			Real-time clock divide (0=/4, 1=/512)
 *	1	RTSEL	0			Real-time clock select (0=OSCM, 1=EXTCLK)
 *	1	CRQEN	0			CPM request enable
 *	1	PRQEN	0			Power management request enable
 *	2	0		00
 *	2	EBDF	xx			External bus division factor
 *	2	0		00
 *	2	DFSYNC	00			Division factor for SYNCLK
 *	2	DFBRG	00			Division factor for BRGCLK
 *	3	DFNL	000			Division factor low frequency
 *	3	DFNH	000			Division factor high frequency
 *	5	0		00000
 */
#define SCCR_MASK	0
#ifdef CONFIG_EBDF
 #define CFG_SCCR	(SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
#else
 #define CFG_SCCR	(SCCR_COM11 | SCCR_TBS)
#endif

/*-----------------------------------------------------------------------
 * Chip Select 0 - FLASH
 *-----------------------------------------------------------------------
 * Preliminary Values
 */
/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1	*/
#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
#define CFG_OR0_PRELIM	(-CFG_FLASH_MAX | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | BR_PS_16 | BR_V )

/*-----------------------------------------------------------------------
 * misc
 *-----------------------------------------------------------------------
 *
 */
/*
 * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
 */
#define CONFIG_BOOTDELAY				5

/*
 * Pass the clock frequency to the Linux kernel in units of MHz
 */
#define	CONFIG_CLOCKS_IN_MHZ

#define CONFIG_PREBOOT		\
	"echo;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND	\
	"bootp;" \
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
	"bootm"

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Set default IP stuff just to get bootstrap entries into the
 * environment so that we can autoscript the full default environment.
 */
#define CONFIG_ETHADDR					9a:52:63:15:85:25
#define CONFIG_SERVERIP					10.0.4.200
#define CONFIG_IPADDR					10.0.4.111

/*-----------------------------------------------------------------------
 * Defaults for Autoscript
 */
#define CFG_LOAD_ADDR		0x00100000	/* default load address */
#define	CFG_TFTP_LOADADDR	0x00100000

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */


#endif	/* __CONFIG_H */
Commit	Line	Data
db2f721f WD	1	/*
	2	* (C) Copyright 2003
	3	* EMK Elektronik GmbH <www.emk-elektronik.de>
	4	* Reinhard Meyer <[email protected]>
	5	*
	6	* Configuation settings for the TOP860 board.
	7	*
	8	* -----------------------------------------------------------------
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27	/*
945af8d7 WD	28	* TOP860 is a simple module:
	29	* 16-bit wide FLASH on CS0 (2MB or more)
	30	* 32-bit wide DRAM on CS2 (either 4MB or 16MB)
	31	* FEC with Am79C874 100-Base-T and Fiber Optic
	32	* Ports available, but we choose SMC1 for Console
db2f721f	33	* 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
945af8d7 WD	34	* 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
	35	*
	36	* This config has been copied from MBX.h / MBX860T.h
db2f721f WD	37	*/
	38	/*
	39	* board/config.h - configuration options, board specific
	40	*/
	41
	42	#ifndef __CONFIG_H
	43	#define __CONFIG_H
	44
	45	/*
	46	* High Level Configuration Options
	47	* (easy to change)
	48	*/
	49
	50	/*-----------------------------------------------------------------------
	51	* CPU and BOARD type
	52	*/
	53	#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
	54	#define CONFIG_MPC860T 1 /* even better... an FEC! */
	55	#define CONFIG_TOP860 1 /* ...on a TOP860 module */
	56	#undef CONFIG_WATCHDOG /* watchdog disabled */
945af8d7	57	#define CONFIG_IDENT_STRING " EMK TOP860"
db2f721f WD	58
	59	/*-----------------------------------------------------------------------
	60	* CLOCK settings
	61	*/
945af8d7 WD	62	#define CONFIG_SYSCLK 49152000
	63	#define CFG_XTAL 32768
	64	#define CONFIG_EBDF 1
	65	#define CONFIG_COM 3
	66	#define CONFIG_RTC_MPC8xx
	67
db2f721f WD	68	/*-----------------------------------------------------------------------
	69	* Physical memory map as defined by EMK
	70	*/
	71	#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register */
945af8d7 WD	72	#define CFG_FLASH_BASE 0x80000000 /* FLASH in final mapping */
	73	#define CFG_DRAM_BASE 0x00000000 /* DRAM in final mapping */
	74	#define CFG_FLASH_MAX 0x00400000 /* max FLASH to expect */
	75	#define CFG_DRAM_MAX 0x01000000 /* max DRAM to expect */
	76
db2f721f WD	77	/*-----------------------------------------------------------------------
	78	* derived values
	79	*/
945af8d7 WD	80	#define CFG_MF (CONFIG_SYSCLK/CFG_XTAL)
	81	#define CFG_CPUCLOCK CONFIG_SYSCLK
	82	#define CFG_BRGCLOCK CONFIG_SYSCLK
	83	#define CFG_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF)
db2f721f	84	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
945af8d7 WD	85	#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK
945af8d7 WD	86
db2f721f WD	87	/*-----------------------------------------------------------------------
	88	* FLASH organization
	89	*/
	90	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	91	#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
	92
	93	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	94	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
945af8d7 WD	95
945af8d7 WD	96	#define CFG_FLASH_CFI
db2f721f WD	97
	98	/*-----------------------------------------------------------------------
	99	* Command interpreter
	100	*/
	101	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	102	#undef CONFIG_8xx_CONS_SMC2
	103	#define CONFIG_BAUDRATE 9600
945af8d7	104
db2f721f WD	105	/*
	106	* Allow partial commands to be matched to uniqueness.
	107	*/
	108	#define CFG_MATCH_PARTIAL_CMD
	109
a5562901	110
db2f721f	111	/*
a5562901	112	* Command line configuration.
db2f721f	113	*/
a5562901 JL	114	#include <config_cmd_default.h>
	115
	116	#define CONFIG_CMD_ASKENV
	117	#define CONFIG_CMD_DHCP
	118	#define CONFIG_CMD_I2C
	119	#define CONFIG_CMD_EEPROM
	120	#define CONFIG_CMD_REGINFO
	121	#define CONFIG_CMD_IMMAP
	122	#define CONFIG_CMD_ELF
	123	#define CONFIG_CMD_DATE
	124	#define CONFIG_CMD_MII
	125	#define CONFIG_CMD_BEDBUG
	126
db2f721f	127
945af8d7 WD	128	#define CONFIG_AUTOSCRIPT 1
945af8d7 WD	129	#define CFG_LOADS_BAUD_CHANGE 1
db2f721f WD	130	#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
db2f721f WD	131
db2f721f WD	132
	133	#define CFG_LONGHELP /* undef to save memory */
	134	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
945af8d7	135
db2f721f	136	#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */
945af8d7	137
db2f721f WD	138	#ifdef CFG_HUSH_PARSER
	139	#define CFG_PROMPT_HUSH_PS2 "> "
	140	#endif
945af8d7	141
a5562901	142	#if defined(CONFIG_CMD_KGDB)
db2f721f WD	143	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	144	#else
	145	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	146	#endif
945af8d7	147
db2f721f WD	148	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	149	#define CFG_MAXARGS 16 /* max number of command args */
	150	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	151
	152	/*-----------------------------------------------------------------------
	153	* Memory Test Command
	154	*/
	155	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	156	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
945af8d7	157
db2f721f WD	158	/*-----------------------------------------------------------------------
	159	* Environment handler
	160	* only the first 6k in EEPROM are available for user. Of that we use 256b
	161	*/
945af8d7	162	#define CONFIG_SOFT_I2C
bb1f8b4f	163	#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
0e8d1586 JCPV	164	#define CONFIG_ENV_OFFSET 0x1000
0e8d1586 JCPV	165	#define CONFIG_ENV_SIZE 0x0700
945af8d7	166	#define CFG_I2C_EEPROM_ADDR 0x57
db2f721f	167	#define CFG_FACT_OFFSET 0x1800
945af8d7 WD	168	#define CFG_FACT_SIZE 0x0800
	169	#define CFG_I2C_FACT_ADDR 0x57
	170	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	171	#define CFG_I2C_EEPROM_ADDR_LEN 2
db2f721f WD	172	#define CFG_EEPROM_SIZE 0x2000
db2f721f WD	173	#define CFG_I2C_SPEED 100000
945af8d7 WD	174	#define CFG_I2C_SLAVE 0xFE
	175	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12
	176	#define CONFIG_ENV_OVERWRITE
	177	#define CONFIG_MISC_INIT_R
	178
	179	#if defined (CONFIG_SOFT_I2C)
	180	#define SDA 0x00010
	181	#define SCL 0x00020
f57f70aa WD	182	#define __I2C_DIR immr->im_cpm.cp_pbdir
	183	#define __I2C_DAT immr->im_cpm.cp_pbdat
	184	#define __I2C_PAR immr->im_cpm.cp_pbpar
	185	#define __I2C_ODR immr->im_cpm.cp_pbodr
	186	#define I2C_INIT { __I2C_PAR &= ~(SDA\|SCL); \
	187	__I2C_ODR &= ~(SDA\|SCL); \
	188	__I2C_DAT \|= (SDA\|SCL); \
	189	__I2C_DIR\|=(SDA\|SCL); }
	190	#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
	191	#define I2C_SDA(x) { if (x) __I2C_DAT \|= SDA; else __I2C_DAT &= ~SDA; }
	192	#define I2C_SCL(x) { if (x) __I2C_DAT \|= SCL; else __I2C_DAT &= ~SCL; }
	193	#define I2C_DELAY { udelay(5); }
	194	#define I2C_ACTIVE { __I2C_DIR \|= SDA; }
	195	#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
db2f721f WD	196	#endif
	197
	198	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	199
	200	/*-----------------------------------------------------------------------
	201	* defines we need to get FEC running
945af8d7	202	*/
db2f721f	203	#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
53677ef1 WD	204	#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
53677ef1 WD	205	#define FEC_ENET 1 /* eth.c needs it that way... */
db2f721f	206	#define CFG_DISCOVER_PHY 1
53677ef1	207	#define CONFIG_MII 1
0f3ba7e9	208	#define CONFIG_MII_INIT 1
db2f721f	209	#define CONFIG_PHY_ADDR 31
945af8d7	210
db2f721f WD	211	/*-----------------------------------------------------------------------
db2f721f WD	212	* adresses
945af8d7	213	*/
db2f721f WD	214	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	215	#define CFG_MONITOR_BASE TEXT_BASE
	216	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
945af8d7	217
db2f721f WD	218	/*-----------------------------------------------------------------------
	219	* Start addresses for the final memory configuration
	220	* (Set up by the startup code)
	221	* Please note that CFG_SDRAM_BASE _must_ start at 0
	222	*/
	223	#define CFG_SDRAM_BASE 0x00000000
	224	#define CFG_FLASH_BASE 0x80000000
945af8d7	225
db2f721f WD	226	/*-----------------------------------------------------------------------
	227	* Definitions for initial stack pointer and data area (in DPRAM)
	228	*/
	229	#define CFG_INIT_RAM_ADDR CFG_IMMR
	230	#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
	231	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	232	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	233	#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
	234	#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
	235	#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8)
	236
	237	/*-----------------------------------------------------------------------
	238	* Cache Configuration
	239	*/
	240	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
a5562901	241	#if defined(CONFIG_CMD_KGDB)
db2f721f WD	242	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	243	#endif
	244
	245	/* Interrupt level assignments.
	246	*/
	247	#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
	248
	249	/*
	250	* Internal Definitions
	251	*
	252	* Boot Flags
	253	*/
	254	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	255	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	256
	257	/*-----------------------------------------------------------------------
	258	* Debug Enable Register
	259	*-----------------------------------------------------------------------
	260	*
	261	*/
	262	#define CFG_DER 0 /* used in start.S */
	263
	264	/*-----------------------------------------------------------------------
	265	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	266	*-----------------------------------------------------------------------
945af8d7 WD	267	* set up PLPRCR (PLL, Low-Power, and Reset Control Register)
	268	* 12 MF calculated Multiplication factor
	269	* 4 0 0000
	270	* 1 SPLSS 0 System PLL lock status sticky
	271	* 1 TEXPS 1 Timer expired status
	272	* 1 0 0
	273	* 1 TMIST 0 Timers interrupt status
	274	* 1 0 0
	275	* 1 CSRC 0 Clock source (0=DFNH, 1=DFNL)
	276	* 2 LPM 00 Low-power modes
	277	* 1 CSR 0 Checkstop reset enable
	278	* 1 LOLRE 0 Loss-of-lock reset enable
	279	* 1 FIOPD 0 Force I/O pull down
42d1f039	280	* 5 0 00000
db2f721f WD	281	*/
db2f721f WD	282	#define CFG_PLPRCR (PLPRCR_TEXPS \| ((CFG_MF-1)<<20))
945af8d7	283
db2f721f WD	284	/*-----------------------------------------------------------------------
	285	* SYPCR - System Protection Control 11-9
	286	* SYPCR can only be written once after reset!
	287	*-----------------------------------------------------------------------
945af8d7 WD	288	* set up SYPCR:
945af8d7 WD	289	* 16 SWTC 0xffff Software watchdog timer count
53677ef1	290	* 8 BMT 0xff Bus monitor timing
945af8d7 WD	291	* 1 BME 1 Bus monitor enable
	292	* 3 0 000
	293	* 1 SWF 1 Software watchdog freeze
	294	* 1 SWE 0/1 Software watchdog enable
	295	* 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET)
	296	* 1 SWP 0/1 Software watchdog prescale (1=/2048)
db2f721f WD	297	*/
	298	#if defined (CONFIG_WATCHDOG)
	299	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
53677ef1	300	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
db2f721f WD	301	#else
	302	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF)
	303	#endif
	304
	305	/*-----------------------------------------------------------------------
	306	* SIUMCR - SIU Module Configuration 11-6
	307	*-----------------------------------------------------------------------
945af8d7 WD	308	* set up SIUMCR
	309	* 1 EARB 0 External arbitration
	310	* 3 EARP 000 External arbitration request priority
	311	* 4 0 0000
	312	* 1 DSHW 0 Data show cycles
	313	* 2 DBGC 00 Debug pin configuration
	314	* 2 DBPC 00 Debug port pins configuration
	315	* 1 0 0
	316	* 1 FRC 0 FRZ pin configuration
	317	* 1 DLK 0 Debug register lock
	318	* 1 OPAR 0 Odd parity
	319	* 1 PNCS 0 Parity enable for non memory controller regions
	320	* 1 DPC 0 Data parity pins configuration
	321	* 1 MPRE 0 Multiprocessor reservation enable
	322	* 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
	323	* 1 AEME 0 Async external master enable
	324	* 1 SEME 0 Sync external master enable
	325	* 1 BSC 0 Byte strobe configuration
	326	* 1 GB5E 0 GPL_B5 enable
42d1f039 WD	327	* 1 B2DD 0 Bank 2 double drive
42d1f039 WD	328	* 1 B3DD 0 Bank 3 double drive
945af8d7	329	* 4 0 0000
db2f721f WD	330	*/
db2f721f WD	331	#define CFG_SIUMCR (SIUMCR_MLRC11)
945af8d7	332
db2f721f WD	333	/*-----------------------------------------------------------------------
	334	* TBSCR - Time Base Status and Control 11-26
	335	*-----------------------------------------------------------------------
	336	* Clear Reference Interrupt Status, Timebase freezing enabled
	337	*/
	338	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	339
	340	/*-----------------------------------------------------------------------
	341	* PISCR - Periodic Interrupt Status and Control 11-31
	342	*-----------------------------------------------------------------------
	343	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	344	*/
	345	#define CFG_PISCR (PISCR_PS \| PISCR_PITF \| PISCR_PTE)
	346
	347	/*-----------------------------------------------------------------------
	348	* SCCR - System Clock and reset Control Register 15-27
	349	*-----------------------------------------------------------------------
945af8d7 WD	350	* set up SCCR (System Clock and Reset Control Register)
	351	* 1 0 0
	352	* 2 COM 11 Clock output module (00=full, 01=half, 11=off)
	353	* 3 0 000
	354	* 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2)
	355	* 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512)
	356	* 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK)
	357	* 1 CRQEN 0 CPM request enable
	358	* 1 PRQEN 0 Power management request enable
	359	* 2 0 00
	360	* 2 EBDF xx External bus division factor
	361	* 2 0 00
	362	* 2 DFSYNC 00 Division factor for SYNCLK
	363	* 2 DFBRG 00 Division factor for BRGCLK
	364	* 3 DFNL 000 Division factor low frequency
	365	* 3 DFNH 000 Division factor high frequency
	366	* 5 0 00000
db2f721f WD	367	*/
db2f721f WD	368	#define SCCR_MASK 0
42dfe7a1	369	#ifdef CONFIG_EBDF
db2f721f	370	#define CFG_SCCR (SCCR_COM11 \| SCCR_TBS \| SCCR_EBDF01)
945af8d7	371	#else
db2f721f	372	#define CFG_SCCR (SCCR_COM11 \| SCCR_TBS)
945af8d7	373	#endif
db2f721f WD	374
	375	/*-----------------------------------------------------------------------
	376	* Chip Select 0 - FLASH
	377	*-----------------------------------------------------------------------
	378	* Preliminary Values
	379	*/
	380	/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */
	381	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_4_CLK \| OR_TRLX \| OR_EHTR)
	382	#define CFG_OR0_PRELIM (-CFG_FLASH_MAX \| CFG_OR_TIMING_FLASH)
	383	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| BR_PS_16 \| BR_V )
945af8d7	384
db2f721f WD	385	/*-----------------------------------------------------------------------
	386	* misc
	387	*-----------------------------------------------------------------------
	388	*
	389	*/
	390	/*
	391	* Set the autoboot delay in seconds. A delay of -1 disables autoboot
	392	*/
	393	#define CONFIG_BOOTDELAY 5
	394
	395	/*
	396	* Pass the clock frequency to the Linux kernel in units of MHz
	397	*/
	398	#define CONFIG_CLOCKS_IN_MHZ
	399
	400	#define CONFIG_PREBOOT \
	401	"echo;echo"
	402
	403	#undef CONFIG_BOOTARGS
	404	#define CONFIG_BOOTCOMMAND \
	405	"bootp;" \
fe126d8b WD	406	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	407	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
db2f721f WD	408	"bootm"
	409
	410	/*
	411	* BOOTP options
	412	*/
37d4bb70 JL	413	#define CONFIG_BOOTP_SUBNETMASK
	414	#define CONFIG_BOOTP_GATEWAY
	415	#define CONFIG_BOOTP_HOSTNAME
	416	#define CONFIG_BOOTP_BOOTPATH
	417	#define CONFIG_BOOTP_BOOTFILESIZE
42d1f039	418
db2f721f WD	419
	420	/*
	421	* Set default IP stuff just to get bootstrap entries into the
	422	* environment so that we can autoscript the full default environment.
	423	*/
	424	#define CONFIG_ETHADDR 9a:52:63:15:85:25
	425	#define CONFIG_SERVERIP 10.0.4.200
	426	#define CONFIG_IPADDR 10.0.4.111
945af8d7	427
db2f721f WD	428	/*-----------------------------------------------------------------------
	429	* Defaults for Autoscript
	430	*/
	431	#define CFG_LOAD_ADDR 0x00100000 /* default load address */
	432	#define CFG_TFTP_LOADADDR 0x00100000
945af8d7	433
db2f721f WD	434	/*
	435	* For booting Linux, the board info and command line data
	436	* have to be in the first 8 MB of memory, since this is
	437	* the maximum mapped by the Linux kernel during initialization.
	438	*/
	439	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	440
945af8d7	441
db2f721f	442	#endif /* __CONFIG_H */