[u-boot.git] / include / configs / PCIPPC2.h

/*
 * (C) Copyright 2002-2005
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 *
 * Configuration settings for the PCIPPC-2 board.
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_PCIPPC2		1	/* this is a PCIPPC2 board	*/

#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R	1

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_PREBOOT		""
#define CONFIG_BOOTDELAY	5

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP

#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1	/* PCI plug-and-play */

#define CONFIG_NAND_LEGACY

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/

/* Print Buffer Size
 */
#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)

#define	CFG_MAXARGS	64		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE	    0x00000000
#define CFG_FLASH_BASE	    0xFFF00000
#define CFG_FLASH_MAX_SIZE  0x00100000
/* Maximum amount of RAM.
 */
#define CFG_MAX_RAM_SIZE    0x20000000  /* 512Mb			*/

#define CFG_RESET_ADDRESS   0xFFF00100

#define CFG_MONITOR_BASE    TEXT_BASE

#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/

#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
    CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#endif

#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */

/* Size in bytes reserved for initial data
 */
#define CFG_GBL_DATA_SIZE    128

#define CFG_INIT_RAM_ADDR     0x40000000
#define CFG_INIT_RAM_END      0x8000
#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET

#define CFG_INIT_RAM_LOCK

/*
 * Temporary buffer for serial data until the real serial driver
 * is initialised (memtest will destroy this buffer)
 */
#define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
#define CFG_SCONSOLE_SIZE     0x0002000

/* SDRAM 0 - 256MB
 */
#define CFG_DBAT0L	      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_DBAT0U	      (CFG_SDRAM_BASE | \
			       BATU_BL_256M | BATU_VS | BATU_VP)
/* SDRAM 1 - 256MB
 */
#define CFG_DBAT1L	      ((CFG_SDRAM_BASE + 0x10000000) | \
			       BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_DBAT1U	      ((CFG_SDRAM_BASE + 0x10000000) | \
			       BATU_BL_256M | BATU_VS | BATU_VP)

/* Init RAM in the CPU DCache (no backing memory)
 */
#define CFG_DBAT2L	      (CFG_INIT_RAM_ADDR | \
			       BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_DBAT2U	      (CFG_INIT_RAM_ADDR | \
			       BATU_BL_128K | BATU_VS | BATU_VP)

/* I/O and PCI memory at 0xf0000000
 */
#define CFG_DBAT3L	      (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_DBAT3U	      (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT0L	      CFG_DBAT0L
#define CFG_IBAT0U	      CFG_DBAT0U
#define CFG_IBAT1L	      CFG_DBAT1L
#define CFG_IBAT1U	      CFG_DBAT1U
#define CFG_IBAT2L	      CFG_DBAT2L
#define CFG_IBAT2U	      CFG_DBAT2U
#define CFG_IBAT3L	      CFG_DBAT3L
#define CFG_IBAT3U	      CFG_DBAT3U

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the PCIPPC2 user's manual.
 */
#define CFG_HZ		      1000
#define CFG_BUS_HZ            100000000 /* bus speed - 100 mhz          */
#define CFG_CPU_CLK	      300000000
#define CFG_BUS_CLK	      100000000

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	      (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
#define CFG_MAX_FLASH_SECT	16	/* Max number of sectors in one bank	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

/*
 * Note: environment is not EMBEDDED in the U-Boot code.
 * It's stored in flash separately.
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x70000)
#define CONFIG_ENV_SIZE		0x1000	/* Size of the Environment		*/
#define CONFIG_ENV_SECT_SIZE	0x10000 /* Size of the Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * L2 cache
 */
#undef CFG_L2
#define L2_INIT   (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#define L2_ENABLE (L2_INIT | L2CR_L2E)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

/*-----------------------------------------------------------------------
 * Disk-On-Chip configuration
 */

#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/

#define CFG_DOC_SUPPORT_2000
#undef CFG_DOC_SUPPORT_MILLENNIUM

/*-----------------------------------------------------------------------
  RTC m48t59
*/
#define CONFIG_RTC_MK48T59

#define CONFIG_WATCHDOG

#define CONFIG_NET_MULTI			/* Multi ethernet cards support */

#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
#define CONFIG_TULIP

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743	1	/*
414eec35	2	* (C) Copyright 2002-2005
e2211743 WD	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	*
	26	* Configuration settings for the PCIPPC-2 board.
	27	*
	28	*/
	29
	30	/* ------------------------------------------------------------------------- */
	31
	32	/*
	33	* board/config.h - configuration options, board specific
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
	44	#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
	45
c837dcb1	46	#define CONFIG_BOARD_EARLY_INIT_F 1
e2211743 WD	47	#define CONFIG_MISC_INIT_R 1
	48
	49	#define CONFIG_CONS_INDEX 1
	50	#define CONFIG_BAUDRATE 9600
	51	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	52
e2211743 WD	53	#define CONFIG_PREBOOT ""
	54	#define CONFIG_BOOTDELAY 5
	55
18225e8d JL	56	/*
	57	* BOOTP options
	58	*/
	59	#define CONFIG_BOOTP_SUBNETMASK
	60	#define CONFIG_BOOTP_GATEWAY
	61	#define CONFIG_BOOTP_HOSTNAME
	62	#define CONFIG_BOOTP_BOOTPATH
	63	#define CONFIG_BOOTP_BOOTFILESIZE
e2211743 WD	64
	65	#define CONFIG_MAC_PARTITION
	66	#define CONFIG_DOS_PARTITION
	67
acf02697 JL	68
	69	/*
	70	* Command line configuration.
	71	*/
	72	#include <config_cmd_default.h>
	73
	74	#define CONFIG_CMD_ASKENV
	75	#define CONFIG_CMD_BSP
	76	#define CONFIG_CMD_DATE
	77	#define CONFIG_CMD_DHCP
	78	#define CONFIG_CMD_DOC
	79	#define CONFIG_CMD_ELF
	80	#define CONFIG_CMD_NFS
	81	#define CONFIG_CMD_PCI
	82	#define CONFIG_CMD_SNTP
e2211743 WD	83
	84	#define CONFIG_PCI 1
	85	#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
	86
cc4a0cee	87	#define CONFIG_NAND_LEGACY
e2211743 WD	88
	89	/*
	90	* Miscellaneous configurable options
	91	*/
	92	#define CFG_LONGHELP /* undef to save memory */
	93	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	94
	95	#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
	96	#ifdef CFG_HUSH_PARSER
	97	#define CFG_PROMPT_HUSH_PS2 "> "
	98	#endif
	99	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	100
	101	/* Print Buffer Size
	102	*/
	103	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
	104
	105	#define CFG_MAXARGS 64 /* max number of command args */
	106	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	107	#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
	108
	109	/*-----------------------------------------------------------------------
	110	* Start addresses for the final memory configuration
	111	* (Set up by the startup code)
	112	* Please note that CFG_SDRAM_BASE _must_ start at 0
	113	*/
	114	#define CFG_SDRAM_BASE 0x00000000
	115	#define CFG_FLASH_BASE 0xFFF00000
	116	#define CFG_FLASH_MAX_SIZE 0x00100000
	117	/* Maximum amount of RAM.
	118	*/
	119	#define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */
	120
	121	#define CFG_RESET_ADDRESS 0xFFF00100
	122
	123	#define CFG_MONITOR_BASE TEXT_BASE
	124
	125	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	126	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	127
	128	#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
	129	CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
	130	#define CFG_RAMBOOT
	131	#else
	132	#undef CFG_RAMBOOT
	133	#endif
	134
	135	#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
	136	#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
	137
	138	/*-----------------------------------------------------------------------
	139	* Definitions for initial stack pointer and data area
	140	*/
	141
	142	/* Size in bytes reserved for initial data
	143	*/
	144	#define CFG_GBL_DATA_SIZE 128
	145
	146	#define CFG_INIT_RAM_ADDR 0x40000000
	147	#define CFG_INIT_RAM_END 0x8000
	148	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	149	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	150
	151	#define CFG_INIT_RAM_LOCK
152
153	/*
154	* Temporary buffer for serial data until the real serial driver
155	* is initialised (memtest will destroy this buffer)
156	*/
157	#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR
158	#define CFG_SCONSOLE_SIZE 0x0002000
159
160	/* SDRAM 0 - 256MB
161	*/
162	#define CFG_DBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
163	#define CFG_DBAT0U (CFG_SDRAM_BASE \| \
164	BATU_BL_256M \| BATU_VS \| BATU_VP)
165	/* SDRAM 1 - 256MB
166	*/
167	#define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) \| \
168	BATL_PP_10 \| BATL_MEMCOHERENCE)
169	#define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) \| \
170	BATU_BL_256M \| BATU_VS \| BATU_VP)
171
172	/* Init RAM in the CPU DCache (no backing memory)
173	*/
174	#define CFG_DBAT2L (CFG_INIT_RAM_ADDR \| \
175	BATL_PP_10 \| BATL_MEMCOHERENCE)
176	#define CFG_DBAT2U (CFG_INIT_RAM_ADDR \| \
177	BATU_BL_128K \| BATU_VS \| BATU_VP)
178
179	/* I/O and PCI memory at 0xf0000000
180	*/
181	#define CFG_DBAT3L (0xf0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
182	#define CFG_DBAT3U (0xf0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
183
184	#define CFG_IBAT0L CFG_DBAT0L
185	#define CFG_IBAT0U CFG_DBAT0U
186	#define CFG_IBAT1L CFG_DBAT1L
187	#define CFG_IBAT1U CFG_DBAT1U
188	#define CFG_IBAT2L CFG_DBAT2L
189	#define CFG_IBAT2U CFG_DBAT2U
190	#define CFG_IBAT3L CFG_DBAT3L
191	#define CFG_IBAT3U CFG_DBAT3U
192
193	/*
194	* Low Level Configuration Settings
195	* (address mappings, register initial values, etc.)
196	* You should know what you are doing if you make changes here.
197	* For the detail description refer to the PCIPPC2 user's manual.
198	*/
199	#define CFG_HZ 1000
200	#define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */
201	#define CFG_CPU_CLK 300000000
202	#define CFG_BUS_CLK 100000000
203
204	/*
205	* For booting Linux, the board info and command line data
206	* have to be in the first 8 MB of memory, since this is
207	* the maximum mapped by the Linux kernel during initialization.
208	*/
209	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
210
211	/*-----------------------------------------------------------------------
212	* FLASH organization
213	*/
214	#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
215	#define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
216
217	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
218	#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
219
220	/*
221	* Note: environment is not EMBEDDED in the U-Boot code.
222	* It's stored in flash separately.
223	*/
5a1aceb0	224	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	225	#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x70000)
	226	#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
	227	#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
e2211743 WD	228
	229	/*-----------------------------------------------------------------------
	230	* Cache Configuration
	231	*/
	232	#define CFG_CACHELINE_SIZE 32
acf02697	233	#if defined(CONFIG_CMD_KGDB)
e2211743 WD	234	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	235	#endif
	236
	237	/*
	238	* L2 cache
	239	*/
	240	#undef CFG_L2
	241	#define L2_INIT (L2CR_L2SIZ_2M \| L2CR_L2CLK_3 \| L2CR_L2RAM_BURST \| \
8bde7f77	242	L2CR_L2OH_5 \| L2CR_L2CTL \| L2CR_L2WT)
e2211743 WD	243	#define L2_ENABLE (L2_INIT \| L2CR_L2E)
	244
	245	/*
	246	* Internal Definitions
	247	*
	248	* Boot Flags
	249	*/
	250	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	251	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	252
	253	/*-----------------------------------------------------------------------
	254	* Disk-On-Chip configuration
	255	*/
	256
	257	#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
	258
	259	#define CFG_DOC_SUPPORT_2000
	260	#undef CFG_DOC_SUPPORT_MILLENNIUM
	261
	262	/*-----------------------------------------------------------------------
	263	RTC m48t59
	264	*/
	265	#define CONFIG_RTC_MK48T59
	266
	267	#define CONFIG_WATCHDOG
	268
	269	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
	270
	271	#define CONFIG_EEPRO100
53cf9435	272	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
e2211743 WD	273	#define CONFIG_TULIP
	274
	275	#endif /* __CONFIG_H */