[u-boot.git] / include / configs / Adder.h

/*
 * Copyright (C) 2004-2005 Arabella Software Ltd.
 * Yuli Barcohen <[email protected]>
 *
 * Support for Analogue&Micro Adder boards family.
 * Tested on AdderII and Adder87x.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
#define CONFIG_MPC875
#endif

#define CONFIG_ADDER				/* Analogue&Micro Adder board	*/

#define	CONFIG_8xx_CONS_SMC1	1		/* Console is on SMC1		*/
#define CONFIG_BAUDRATE		38400

#define CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1

#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
#define CFG_DISCOVER_PHY
#define CONFIG_MII_INIT		1
#define FEC_ENET
#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */

#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
#define CFG_8xx_CPUCLK_MIN		40000000
#ifdef CONFIG_MPC852T
#define CFG_8xx_CPUCLK_MAX		50000000
#else
#define CFG_8xx_CPUCLK_MAX		133000000
#endif /* CONFIG_MPC852T */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING


#define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds	*/
#define CONFIG_BOOTCOMMAND	"bootm fe040000"	/* Autoboot command	*/
#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"

#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
#undef	CONFIG_WATCHDOG		/* Disable platform specific watchdog		*/

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 */
#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#define CFG_LONGHELP				/* #undef to save memory	*/
#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
#define CFG_MAXARGS		16		/* Max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_LOAD_ADDR		0x400000	/* Default load address		*/

#define CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * RAM configuration (note that CFG_SDRAM_BASE must be zero)
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_SDRAM_MAX_SIZE	0x01000000	/* Up to 16 Mbyte		*/

#define CFG_MAMR		0x00002114

/*
 * 4096	Up to 4096 SDRAM rows
 * 1000	factor s -> ms
 * 32	PTP (pre-divider from MPTPR)
 * 4	Number of refresh cycles per period
 * 64	Refresh cycle in ms per number of rows
 */
#define CFG_PTA_PER_CLK		((4096 * 32 * 1000) / (4 * 64))

#define CFG_MEMTEST_START	0x00100000	/* memtest works on		*/
#define CFG_MEMTEST_END		0x00500000	/* 1 ... 5 MB in SDRAM		*/

#define CFG_RESET_ADDRESS	0x09900000

/*-----------------------------------------------------------------------
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for Monitor   */
#ifdef CONFIG_BZIP2
#define CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc() */
#else
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
#endif /* CONFIG_BZIP2 */

/*-----------------------------------------------------------------------
 * Flash organisation
 */
#define CFG_FLASH_BASE		0xFE000000
#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
#define CFG_MAX_FLASH_BANKS	1		/* Max number of flash banks	*/
#define CFG_MAX_FLASH_SECT	128		/* Max num of sects on one chip */

/* Environment is in flash */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000		/* We use one complete sector	*/
#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)

#define CONFIG_ENV_OVERWRITE

#define CFG_OR0_PRELIM		0xFF000774
#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)

#define	CFG_DIRECT_FLASH_TFTP

/*-----------------------------------------------------------------------
 * Internal Memory Map Register
 */
#define CFG_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Configuration registers
 */
#ifdef CONFIG_WATCHDOG
#define CFG_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
				 SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
				 SYPCR_SWP)
#else
#define CFG_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
				 SYPCR_SWF  | SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

#define CFG_SIUMCR		(SIUMCR_MLRC01 | SIUMCR_DBGC11)

/* TBSCR - Time Base Status and Control Register */
#define CFG_TBSCR		(TBSCR_TBF | TBSCR_TBE)

/* PISCR - Periodic Interrupt Status and Control */
#define CFG_PISCR		(PISCR_PS | PISCR_PITF)

/* PLPRCR - PLL, Low-Power, and Reset Control Register */
/* #define CFG_PLPRCR		PLPRCR_TEXPS */

/* SCCR - System Clock and reset Control Register */
#define SCCR_MASK		SCCR_EBDF11
#define CFG_SCCR		SCCR_RTSEL

#define CFG_DER			0

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx chips			*/

/*-----------------------------------------------------------------------
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from flash	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#endif /* __CONFIG_H */
Commit	Line	Data
2d24a3a7	1	/*
5797b821	2	* Copyright (C) 2004-2005 Arabella Software Ltd.
2d24a3a7 WD	3	* Yuli Barcohen <[email protected]>
	4	*
	5	* Support for Analogue&Micro Adder boards family.
	6	* Tested on AdderII and Adder87x.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
	30	#define CONFIG_MPC875
	31	#endif
	32
	33	#define CONFIG_ADDER /* Analogue&Micro Adder board */
	34
	35	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	36	#define CONFIG_BAUDRATE 38400
	37
5797b821 WD	38	#define CONFIG_ETHER_ON_FEC1
5797b821 WD	39	#define CONFIG_ETHER_ON_FEC2
a6f5f317 BD	40	#define CONFIG_HAS_ETH0
a6f5f317 BD	41	#define CONFIG_HAS_ETH1
5797b821 WD	42
5797b821 WD	43	#if defined(CONFIG_ETHER_ON_FEC1) \|\| defined(CONFIG_ETHER_ON_FEC2)
2d24a3a7	44	#define CFG_DISCOVER_PHY
0f3ba7e9	45	#define CONFIG_MII_INIT 1
2d24a3a7	46	#define FEC_ENET
5797b821	47	#endif /* CONFIG_ETHER_ON_FEC \|\| CONFIG_ETHER_ON_FEC2 */
2d24a3a7	48
66ca92a5 WD	49	#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
	50	#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
	51	#define CFG_8xx_CPUCLK_MIN 40000000
	52	#ifdef CONFIG_MPC852T
	53	#define CFG_8xx_CPUCLK_MAX 50000000
	54	#else
5797b821	55	#define CFG_8xx_CPUCLK_MAX 133000000
66ca92a5	56	#endif /* CONFIG_MPC852T */
2d24a3a7	57
2d24a3a7	58
11799434 JL	59	/*
	60	* BOOTP options
	61	*/
	62	#define CONFIG_BOOTP_BOOTFILESIZE
	63	#define CONFIG_BOOTP_BOOTPATH
	64	#define CONFIG_BOOTP_GATEWAY
	65	#define CONFIG_BOOTP_HOSTNAME
	66
	67
498ff9a2 JL	68	/*
	69	* Command line configuration.
	70	*/
	71	#include <config_cmd_default.h>
	72
5728be38 WD	73	#define CONFIG_CMD_DHCP
	74	#define CONFIG_CMD_IMMAP
	75	#define CONFIG_CMD_MII
	76	#define CONFIG_CMD_PING
498ff9a2	77
2d24a3a7 WD	78
	79	#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
	80	#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
5797b821	81	#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
2d24a3a7 WD	82
	83	#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
	84	#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
	85
	86	/*-----------------------------------------------------------------------
	87	* Miscellaneous configurable options
	88	*/
	89	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	90	#define CFG_HUSH_PARSER
	91	#define CFG_PROMPT_HUSH_PS2 "> "
	92	#define CFG_LONGHELP /* #undef to save memory */
	93	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	94	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
	95	#define CFG_MAXARGS 16 /* Max number of command args */
	96	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	97
5797b821	98	#define CFG_LOAD_ADDR 0x400000 /* Default load address */
2d24a3a7 WD	99
	100	#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
	101
	102	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	103
	104	/*-----------------------------------------------------------------------
	105	* RAM configuration (note that CFG_SDRAM_BASE must be zero)
	106	*/
	107	#define CFG_SDRAM_BASE 0x00000000
5797b821	108	#define CFG_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */
2d24a3a7	109
5797b821	110	#define CFG_MAMR 0x00002114
2d24a3a7	111
66ca92a5	112	/*
5797b821	113	* 4096 Up to 4096 SDRAM rows
66ca92a5	114	* 1000 factor s -> ms
5797b821	115	* 32 PTP (pre-divider from MPTPR)
66ca92a5 WD	116	* 4 Number of refresh cycles per period
	117	* 64 Refresh cycle in ms per number of rows
	118	*/
5797b821	119	#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
66ca92a5	120
2d24a3a7	121	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
5797b821	122	#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
2d24a3a7 WD	123
	124	#define CFG_RESET_ADDRESS 0x09900000
	125
	126	/*-----------------------------------------------------------------------
	127	* For booting Linux, the board info and command line data
	128	* have to be in the first 8 MB of memory, since this is
	129	* the maximum mapped by the Linux kernel during initialization.
	130	*/
	131	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	132
	133	#define CFG_MONITOR_BASE TEXT_BASE
4fc72a0d	134	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
2d24a3a7 WD	135	#ifdef CONFIG_BZIP2
	136	#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
	137	#else
	138	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
	139	#endif /* CONFIG_BZIP2 */
	140
	141	/*-----------------------------------------------------------------------
	142	* Flash organisation
	143	*/
	144	#define CFG_FLASH_BASE 0xFE000000
	145	#define CFG_FLASH_CFI /* The flash is CFI compatible */
00b1883a	146	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
2d24a3a7 WD	147	#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
	148	#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
	149
	150	/* Environment is in flash */
5a1aceb0	151	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	152	#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
0e8d1586 JCPV	153	#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
2d24a3a7	154
5797b821 WD	155	#define CONFIG_ENV_OVERWRITE
5797b821 WD	156
2d24a3a7 WD	157	#define CFG_OR0_PRELIM 0xFF000774
	158	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| BR_PS_16 \| BR_MS_GPCM \| BR_V)
	159
26238132 WD	160	#define CFG_DIRECT_FLASH_TFTP
26238132 WD	161
2d24a3a7 WD	162	/*-----------------------------------------------------------------------
	163	* Internal Memory Map Register
	164	*/
	165	#define CFG_IMMR 0xFF000000
	166
	167	/*-----------------------------------------------------------------------
	168	* Definitions for initial stack pointer and data area (in DPRAM)
	169	*/
	170	#define CFG_INIT_RAM_ADDR CFG_IMMR
	171	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	172	#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
	173	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	174	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	175
	176	/*-----------------------------------------------------------------------
	177	* Configuration registers
	178	*/
	179	#ifdef CONFIG_WATCHDOG
	180	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| \
	181	SYPCR_SWF \| SYPCR_SWE \| SYPCR_SWRI \| \
	182	SYPCR_SWP)
	183	#else
	184	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| \
	185	SYPCR_SWF \| SYPCR_SWP)
	186	#endif /* CONFIG_WATCHDOG */
	187
	188	#define CFG_SIUMCR (SIUMCR_MLRC01 \| SIUMCR_DBGC11)
	189
	190	/* TBSCR - Time Base Status and Control Register */
	191	#define CFG_TBSCR (TBSCR_TBF \| TBSCR_TBE)
	192
	193	/* PISCR - Periodic Interrupt Status and Control */
53677ef1	194	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
2d24a3a7 WD	195
2d24a3a7 WD	196	/* PLPRCR - PLL, Low-Power, and Reset Control Register */
53677ef1	197	/* #define CFG_PLPRCR PLPRCR_TEXPS */
2d24a3a7 WD	198
2d24a3a7 WD	199	/* SCCR - System Clock and reset Control Register */
53677ef1	200	#define SCCR_MASK SCCR_EBDF11
2d24a3a7 WD	201	#define CFG_SCCR SCCR_RTSEL
2d24a3a7 WD	202
53677ef1	203	#define CFG_DER 0
2d24a3a7 WD	204
	205	/*-----------------------------------------------------------------------
	206	* Cache Configuration
	207	*/
	208	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
	209
	210	/*-----------------------------------------------------------------------
	211	* Internal Definitions
	212	*
	213	* Boot Flags
	214	*/
	215	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
	216	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	217
a6f5f317 BD	218	/* pass open firmware flat tree */
	219	#define CONFIG_OF_LIBFDT 1
	220	#define CONFIG_OF_BOARD_SETUP 1
	221
2d24a3a7	222	#endif /* __CONFIG_H */