[u-boot.git] / board / cpc45 / flash.c

/*
 * (C) Copyright 2001-2003
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc824x.h>
#include <asm/processor.h>

#if defined(CONFIG_ENV_IS_IN_FLASH)
# ifndef  CONFIG_ENV_ADDR
#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
# endif
# ifndef  CONFIG_ENV_SIZE
#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
# endif
# ifndef  CONFIG_ENV_SECT_SIZE
#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
# endif
#endif

#define FLASH_BANK_SIZE 0x800000
#define MAIN_SECT_SIZE  0x40000
#define PARAM_SECT_SIZE 0x8000

flash_info_t flash_info[CFG_MAX_FLASH_BANKS];

static int write_data (flash_info_t * info, ulong dest, ulong * data);
static void write_via_fpu (vu_long * addr, ulong * data);
static __inline__ unsigned long get_msr (void);
static __inline__ void set_msr (unsigned long msr);

/*---------------------------------------------------------------------*/
#undef	DEBUG_FLASH

/*---------------------------------------------------------------------*/
#ifdef DEBUG_FLASH
#define DEBUGF(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGF(fmt,args...)
#endif
/*---------------------------------------------------------------------*/

/*-----------------------------------------------------------------------
 */

unsigned long flash_init (void)
{
	int i, j;
	ulong size = 0;
	uchar tempChar;
	vu_long *tmpaddr;

	/* Enable flash writes on CPC45 */

	tempChar = BOARD_CTRL;

	tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);

	tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);

	BOARD_CTRL = tempChar;

	__asm__ volatile ("sync\n eieio");

	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
		vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);

		addr[0] = 0x00900090;

		__asm__ volatile ("sync\n eieio");

		udelay (100);

		DEBUGF ("Flash bank # %d:\n"
			"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
			"\tDevice ID @ 0x%08lX: 0x%08lX\n",
			i,
			(ulong) (&addr[0]), addr[0],
			(ulong) (&addr[2]), addr[2]);


		if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
		    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {

			flash_info[i].flash_id =
				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
				(INTEL_ID_28F160F3T & FLASH_TYPEMASK);

		} else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
			 && (addr[2] == addr[3])
			 && (addr[2] == INTEL_ID_28F160C3T)) {

			flash_info[i].flash_id =
				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
				(INTEL_ID_28F160C3T & FLASH_TYPEMASK);

		} else {
			flash_info[i].flash_id = FLASH_UNKNOWN;
			addr[0] = 0xFFFFFFFF;
			goto Done;
		}

		DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);

		addr[0] = 0xFFFFFFFF;

		flash_info[i].size = FLASH_BANK_SIZE;
		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
		for (j = 0; j < flash_info[i].sector_count; j++) {
			if (j > 30) {
				flash_info[i].start[j] = CFG_FLASH_BASE +
					i * FLASH_BANK_SIZE +
					(MAIN_SECT_SIZE * 31) + (j -
								 31) *
					PARAM_SECT_SIZE;
			} else {
				flash_info[i].start[j] = CFG_FLASH_BASE +
					i * FLASH_BANK_SIZE +
					j * MAIN_SECT_SIZE;
			}
		}

		/* unlock sectors, if 160C3T */

		for (j = 0; j < flash_info[i].sector_count; j++) {
			tmpaddr = (vu_long *) flash_info[i].start[j];

			if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
			    (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
				tmpaddr[0] = 0x00600060;
				tmpaddr[0] = 0x00D000D0;
				tmpaddr[1] = 0x00600060;
				tmpaddr[1] = 0x00D000D0;
			}
		}

		size += flash_info[i].size;

		addr[0] = 0x00FF00FF;
		addr[1] = 0x00FF00FF;
	}

	/* Protect monitor and environment sectors
	 */
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
	flash_protect (FLAG_PROTECT_SET,
		       CFG_MONITOR_BASE,
		       CFG_MONITOR_BASE + monitor_flash_len - 1,
		       &flash_info[1]);
#else
	flash_protect (FLAG_PROTECT_SET,
		       CFG_MONITOR_BASE,
		       CFG_MONITOR_BASE + monitor_flash_len - 1,
		       &flash_info[0]);
#endif

#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
#if CONFIG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
	flash_protect (FLAG_PROTECT_SET,
		       CONFIG_ENV_ADDR,
		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
#else
	flash_protect (FLAG_PROTECT_SET,
		       CONFIG_ENV_ADDR,
		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
#endif
#endif

Done:
	return size;
}

/*-----------------------------------------------------------------------
 */
void flash_print_info (flash_info_t * info)
{
	int i;

	switch ((i = info->flash_id & FLASH_VENDMASK)) {
	case (FLASH_MAN_INTEL & FLASH_VENDMASK):
		printf ("Intel: ");
		break;
	default:
		printf ("Unknown Vendor 0x%04x ", i);
		break;
	}

	switch ((i = info->flash_id & FLASH_TYPEMASK)) {
	case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
		printf ("28F160F3T (16Mbit)\n");
		break;

	case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
		printf ("28F160C3T (16Mbit)\n");
		break;

	default:
		printf ("Unknown Chip Type 0x%04x\n", i);
		goto Done;
		break;
	}

	printf ("  Size: %ld MB in %d Sectors\n",
		info->size >> 20, info->sector_count);

	printf ("  Sector Start Addresses:");
	for (i = 0; i < info->sector_count; i++) {
		if ((i % 5) == 0) {
			printf ("\n   ");
		}
		printf (" %08lX%s", info->start[i],
			info->protect[i] ? " (RO)" : "     ");
	}
	printf ("\n");

Done:
	return;
}

/*-----------------------------------------------------------------------
 */

int flash_erase (flash_info_t * info, int s_first, int s_last)
{
	int flag, prot, sect;
	ulong start, now, last;

	DEBUGF ("Erase flash bank %d sect %d ... %d\n",
		info - &flash_info[0], s_first, s_last);

	if ((s_first < 0) || (s_first > s_last)) {
		if (info->flash_id == FLASH_UNKNOWN) {
			printf ("- missing\n");
		} else {
			printf ("- no sectors to erase\n");
		}
		return 1;
	}

	if ((info->flash_id & FLASH_VENDMASK) !=
	    (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
		printf ("Can erase only Intel flash types - aborted\n");
		return 1;
	}

	prot = 0;
	for (sect = s_first; sect <= s_last; ++sect) {
		if (info->protect[sect]) {
			prot++;
		}
	}

	if (prot) {
		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
	} else {
		printf ("\n");
	}

	start = get_timer (0);
	last = start;
	/* Start erase on unprotected sectors */
	for (sect = s_first; sect <= s_last; sect++) {
		if (info->protect[sect] == 0) {	/* not protected */
			vu_long *addr = (vu_long *) (info->start[sect]);

			DEBUGF ("Erase sect %d @ 0x%08lX\n",
				sect, (ulong) addr);

			/* Disable interrupts which might cause a timeout
			 * here.
			 */
			flag = disable_interrupts ();

			addr[0] = 0x00500050;	/* clear status register */
			addr[0] = 0x00200020;	/* erase setup */
			addr[0] = 0x00D000D0;	/* erase confirm */

			addr[1] = 0x00500050;	/* clear status register */
			addr[1] = 0x00200020;	/* erase setup */
			addr[1] = 0x00D000D0;	/* erase confirm */

			/* re-enable interrupts if necessary */
			if (flag)
				enable_interrupts ();

			/* wait at least 80us - let's wait 1 ms */
			udelay (1000);

			while (((addr[0] & 0x00800080) != 0x00800080) ||
			       ((addr[1] & 0x00800080) != 0x00800080)) {
				if ((now = get_timer (start)) >
				    CFG_FLASH_ERASE_TOUT) {
					printf ("Timeout\n");
					addr[0] = 0x00B000B0;	/* suspend erase */
					addr[0] = 0x00FF00FF;	/* to read mode  */
					return 1;
				}

				/* show that we're waiting */
				if ((now - last) > 1000) {	/* every second  */
					putc ('.');
					last = now;
				}
			}

			addr[0] = 0x00FF00FF;
		}
	}
	printf (" done\n");
	return 0;
}

/*-----------------------------------------------------------------------
 * Copy memory to flash, returns:
 * 0 - OK
 * 1 - write timeout
 * 2 - Flash not erased
 * 4 - Flash not identified
 */

#define	FLASH_WIDTH	8	/* flash bus width in bytes */

int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
	ulong wp, cp, msr;
	int l, rc, i;
	ulong data[2];
	ulong *datah = &data[0];
	ulong *datal = &data[1];

	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
		addr, (ulong) src, cnt);

	if (info->flash_id == FLASH_UNKNOWN) {
		return 4;
	}

	msr = get_msr ();
	set_msr (msr | MSR_FP);

	wp = (addr & ~(FLASH_WIDTH - 1));	/* get lower aligned address */

	/*
	 * handle unaligned start bytes
	 */
	if ((l = addr - wp) != 0) {
		*datah = *datal = 0;

		for (i = 0, cp = wp; i < l; i++, cp++) {
			if (i >= 4) {
				*datah = (*datah << 8) |
					((*datal & 0xFF000000) >> 24);
			}

			*datal = (*datal << 8) | (*(uchar *) cp);
		}
		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
			char tmp = *src++;

			if (i >= 4) {
				*datah = (*datah << 8) |
					((*datal & 0xFF000000) >> 24);
			}

			*datal = (*datal << 8) | tmp;
			--cnt;
			++cp;
		}

		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
			if (i >= 4) {
				*datah = (*datah << 8) |
					((*datal & 0xFF000000) >> 24);
			}

			*datal = (*datah << 8) | (*(uchar *) cp);
		}

		if ((rc = write_data (info, wp, data)) != 0) {
			set_msr (msr);
			return (rc);
		}

		wp += FLASH_WIDTH;
	}

	/*
	 * handle FLASH_WIDTH aligned part
	 */
	while (cnt >= FLASH_WIDTH) {
		*datah = *(ulong *) src;
		*datal = *(ulong *) (src + 4);
		if ((rc = write_data (info, wp, data)) != 0) {
			set_msr (msr);
			return (rc);
		}
		wp += FLASH_WIDTH;
		cnt -= FLASH_WIDTH;
		src += FLASH_WIDTH;
	}

	if (cnt == 0) {
		set_msr (msr);
		return (0);
	}

	/*
	 * handle unaligned tail bytes
	 */
	*datah = *datal = 0;
	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
		char tmp = *src++;

		if (i >= 4) {
			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
						  24);
		}

		*datal = (*datal << 8) | tmp;
		--cnt;
	}

	for (; i < FLASH_WIDTH; ++i, ++cp) {
		if (i >= 4) {
			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
						  24);
		}

		*datal = (*datal << 8) | (*(uchar *) cp);
	}

	rc = write_data (info, wp, data);
	set_msr (msr);

	return (rc);
}

/*-----------------------------------------------------------------------
 * Write a word to Flash, returns:
 * 0 - OK
 * 1 - write timeout
 * 2 - Flash not erased
 */
static int write_data (flash_info_t * info, ulong dest, ulong * data)
{
	vu_long *addr = (vu_long *) dest;
	ulong start;
	int flag;

	/* Check if Flash is (sufficiently) erased */
	if (((addr[0] & data[0]) != data[0]) ||
	    ((addr[1] & data[1]) != data[1])) {
		return (2);
	}
	/* Disable interrupts which might cause a timeout here */
	flag = disable_interrupts ();

	addr[0] = 0x00400040;	/* write setup */
	write_via_fpu (addr, data);

	/* re-enable interrupts if necessary */
	if (flag)
		enable_interrupts ();

	start = get_timer (0);

	while (((addr[0] & 0x00800080) != 0x00800080) ||
	       ((addr[1] & 0x00800080) != 0x00800080)) {
		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
			addr[0] = 0x00FF00FF;	/* restore read mode */
			return (1);
		}
	}

	addr[0] = 0x00FF00FF;	/* restore read mode */

	return (0);
}

/*-----------------------------------------------------------------------
 */
static void write_via_fpu (vu_long * addr, ulong * data)
{
	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
}

/*-----------------------------------------------------------------------
 */
static __inline__ unsigned long get_msr (void)
{
	unsigned long msr;

	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);

	return msr;
}

static __inline__ void set_msr (unsigned long msr)
{
	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
}
Commit	Line	Data
3bac3513 WD	1	/*
	2	* (C) Copyright 2001-2003
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc824x.h>
	26	#include <asm/processor.h>
	27
5a1aceb0	28	#if defined(CONFIG_ENV_IS_IN_FLASH)
0e8d1586 JCPV	29	# ifndef CONFIG_ENV_ADDR
0e8d1586 JCPV	30	# define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
3bac3513	31	# endif
0e8d1586 JCPV	32	# ifndef CONFIG_ENV_SIZE
0e8d1586 JCPV	33	# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
3bac3513	34	# endif
0e8d1586 JCPV	35	# ifndef CONFIG_ENV_SECT_SIZE
0e8d1586 JCPV	36	# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
3bac3513 WD	37	# endif
	38	#endif
	39
	40	#define FLASH_BANK_SIZE 0x800000
	41	#define MAIN_SECT_SIZE 0x40000
	42	#define PARAM_SECT_SIZE 0x8000
	43
49822e23	44	flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
3bac3513	45
49822e23 WD	46	static int write_data (flash_info_t * info, ulong dest, ulong * data);
	47	static void write_via_fpu (vu_long * addr, ulong * data);
	48	static __inline__ unsigned long get_msr (void);
	49	static __inline__ void set_msr (unsigned long msr);
3bac3513 WD	50
	51	/---------------------------------------------------------------------/
	52	#undef DEBUG_FLASH
	53
	54	/---------------------------------------------------------------------/
	55	#ifdef DEBUG_FLASH
	56	#define DEBUGF(fmt,args...) printf(fmt ,##args)
	57	#else
	58	#define DEBUGF(fmt,args...)
	59	#endif
	60	/---------------------------------------------------------------------/
	61
	62	/*-----------------------------------------------------------------------
	63	*/
	64
49822e23	65	unsigned long flash_init (void)
3bac3513	66	{
49822e23 WD	67	int i, j;
	68	ulong size = 0;
	69	uchar tempChar;
	70	vu_long *tmpaddr;
3bac3513	71
49822e23	72	/* Enable flash writes on CPC45 */
3bac3513	73
49822e23	74	tempChar = BOARD_CTRL;
3bac3513	75
49822e23	76	tempChar \|= (B_CTRL_FWPT_1 \| B_CTRL_FWRE_1);
3bac3513	77
49822e23	78	tempChar &= ~(B_CTRL_FWPT_0 \| B_CTRL_FWRE_0);
3bac3513	79
49822e23	80	BOARD_CTRL = tempChar;
3bac3513	81
49822e23	82	__asm__ volatile ("sync\n eieio");
3bac3513	83
49822e23 WD	84	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
49822e23 WD	85	vu_long addr = (vu_long ) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
3bac3513	86
49822e23	87	addr[0] = 0x00900090;
3bac3513	88
49822e23	89	__asm__ volatile ("sync\n eieio");
3bac3513	90
49822e23	91	udelay (100);
3bac3513	92
49822e23 WD	93	DEBUGF ("Flash bank # %d:\n"
	94	"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
	95	"\tDevice ID @ 0x%08lX: 0x%08lX\n",
	96	i,
	97	(ulong) (&addr[0]), addr[0],
	98	(ulong) (&addr[2]), addr[2]);
3bac3513	99
3bac3513	100
49822e23 WD	101	if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
49822e23 WD	102	(addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {
3bac3513	103
49822e23 WD	104	flash_info[i].flash_id =
	105	(FLASH_MAN_INTEL & FLASH_VENDMASK) \|
	106	(INTEL_ID_28F160F3T & FLASH_TYPEMASK);
3bac3513	107
49822e23 WD	108	} else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
	109	&& (addr[2] == addr[3])
	110	&& (addr[2] == INTEL_ID_28F160C3T)) {
	111
	112	flash_info[i].flash_id =
	113	(FLASH_MAN_INTEL & FLASH_VENDMASK) \|
	114	(INTEL_ID_28F160C3T & FLASH_TYPEMASK);
3bac3513	115
3bac3513	116	} else {
49822e23 WD	117	flash_info[i].flash_id = FLASH_UNKNOWN;
	118	addr[0] = 0xFFFFFFFF;
	119	goto Done;
	120	}
	121
	122	DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
	123
	124	addr[0] = 0xFFFFFFFF;
	125
	126	flash_info[i].size = FLASH_BANK_SIZE;
	127	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
	128	memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
	129	for (j = 0; j < flash_info[i].sector_count; j++) {
	130	if (j > 30) {
	131	flash_info[i].start[j] = CFG_FLASH_BASE +
	132	i * FLASH_BANK_SIZE +
	133	(MAIN_SECT_SIZE * 31) + (j -
	134	31) *
	135	PARAM_SECT_SIZE;
	136	} else {
	137	flash_info[i].start[j] = CFG_FLASH_BASE +
	138	i * FLASH_BANK_SIZE +
	139	j * MAIN_SECT_SIZE;
	140	}
	141	}
	142
	143	/* unlock sectors, if 160C3T */
	144
	145	for (j = 0; j < flash_info[i].sector_count; j++) {
	146	tmpaddr = (vu_long *) flash_info[i].start[j];
	147
	148	if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
	149	(INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
	150	tmpaddr[0] = 0x00600060;
	151	tmpaddr[0] = 0x00D000D0;
	152	tmpaddr[1] = 0x00600060;
	153	tmpaddr[1] = 0x00D000D0;
	154	}
3bac3513	155	}
49822e23 WD	156
	157	size += flash_info[i].size;
	158
	159	addr[0] = 0x00FF00FF;
	160	addr[1] = 0x00FF00FF;
3bac3513	161	}
3bac3513	162
49822e23 WD	163	/* Protect monitor and environment sectors
49822e23 WD	164	*/
3bac3513	165	#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
49822e23 WD	166	flash_protect (FLAG_PROTECT_SET,
	167	CFG_MONITOR_BASE,
	168	CFG_MONITOR_BASE + monitor_flash_len - 1,
	169	&flash_info[1]);
3bac3513	170	#else
49822e23 WD	171	flash_protect (FLAG_PROTECT_SET,
	172	CFG_MONITOR_BASE,
	173	CFG_MONITOR_BASE + monitor_flash_len - 1,
	174	&flash_info[0]);
3bac3513 WD	175	#endif
3bac3513 WD	176
0e8d1586 JCPV	177	#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
0e8d1586 JCPV	178	#if CONFIG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
49822e23	179	flash_protect (FLAG_PROTECT_SET,
0e8d1586 JCPV	180	CONFIG_ENV_ADDR,
0e8d1586 JCPV	181	CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
3bac3513	182	#else
49822e23	183	flash_protect (FLAG_PROTECT_SET,
0e8d1586 JCPV	184	CONFIG_ENV_ADDR,
0e8d1586 JCPV	185	CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
3bac3513 WD	186	#endif
	187	#endif
	188
	189	Done:
49822e23	190	return size;
3bac3513 WD	191	}
	192
	193	/*-----------------------------------------------------------------------
	194	*/
	195	void flash_print_info (flash_info_t * info)
	196	{
	197	int i;
	198
	199	switch ((i = info->flash_id & FLASH_VENDMASK)) {
	200	case (FLASH_MAN_INTEL & FLASH_VENDMASK):
	201	printf ("Intel: ");
	202	break;
	203	default:
	204	printf ("Unknown Vendor 0x%04x ", i);
	205	break;
	206	}
	207
	208	switch ((i = info->flash_id & FLASH_TYPEMASK)) {
	209	case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
	210	printf ("28F160F3T (16Mbit)\n");
	211	break;
49822e23 WD	212
	213	case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
	214	printf ("28F160C3T (16Mbit)\n");
	215	break;
	216
3bac3513 WD	217	default:
	218	printf ("Unknown Chip Type 0x%04x\n", i);
	219	goto Done;
	220	break;
	221	}
	222
	223	printf (" Size: %ld MB in %d Sectors\n",
49822e23	224	info->size >> 20, info->sector_count);
3bac3513 WD	225
	226	printf (" Sector Start Addresses:");
	227	for (i = 0; i < info->sector_count; i++) {
	228	if ((i % 5) == 0) {
	229	printf ("\n ");
	230	}
	231	printf (" %08lX%s", info->start[i],
49822e23	232	info->protect[i] ? " (RO)" : " ");
3bac3513 WD	233	}
	234	printf ("\n");
	235
	236	Done:
	237	return;
	238	}
	239
	240	/*-----------------------------------------------------------------------
	241	*/
	242
49822e23	243	int flash_erase (flash_info_t * info, int s_first, int s_last)
3bac3513 WD	244	{
	245	int flag, prot, sect;
	246	ulong start, now, last;
	247
	248	DEBUGF ("Erase flash bank %d sect %d ... %d\n",
	249	info - &flash_info[0], s_first, s_last);
	250
	251	if ((s_first < 0) \|\| (s_first > s_last)) {
	252	if (info->flash_id == FLASH_UNKNOWN) {
	253	printf ("- missing\n");
	254	} else {
	255	printf ("- no sectors to erase\n");
	256	}
	257	return 1;
	258	}
	259
	260	if ((info->flash_id & FLASH_VENDMASK) !=
	261	(FLASH_MAN_INTEL & FLASH_VENDMASK)) {
	262	printf ("Can erase only Intel flash types - aborted\n");
	263	return 1;
	264	}
	265
	266	prot = 0;
49822e23	267	for (sect = s_first; sect <= s_last; ++sect) {
3bac3513 WD	268	if (info->protect[sect]) {
	269	prot++;
	270	}
	271	}
	272
	273	if (prot) {
49822e23	274	printf ("- Warning: %d protected sectors will not be erased!\n", prot);
3bac3513 WD	275	} else {
	276	printf ("\n");
	277	}
	278
	279	start = get_timer (0);
49822e23	280	last = start;
3bac3513	281	/* Start erase on unprotected sectors */
49822e23	282	for (sect = s_first; sect <= s_last; sect++) {
3bac3513	283	if (info->protect[sect] == 0) { /* not protected */
49822e23	284	vu_long addr = (vu_long ) (info->start[sect]);
3bac3513 WD	285
3bac3513 WD	286	DEBUGF ("Erase sect %d @ 0x%08lX\n",
49822e23	287	sect, (ulong) addr);
3bac3513 WD	288
	289	/* Disable interrupts which might cause a timeout
	290	* here.
	291	*/
49822e23	292	flag = disable_interrupts ();
3bac3513 WD	293
	294	addr[0] = 0x00500050; /* clear status register */
	295	addr[0] = 0x00200020; /* erase setup */
	296	addr[0] = 0x00D000D0; /* erase confirm */
	297
	298	addr[1] = 0x00500050; /* clear status register */
	299	addr[1] = 0x00200020; /* erase setup */
	300	addr[1] = 0x00D000D0; /* erase confirm */
	301
	302	/* re-enable interrupts if necessary */
	303	if (flag)
49822e23	304	enable_interrupts ();
3bac3513 WD	305
	306	/* wait at least 80us - let's wait 1 ms */
	307	udelay (1000);
	308
	309	while (((addr[0] & 0x00800080) != 0x00800080) \|\|
49822e23 WD	310	((addr[1] & 0x00800080) != 0x00800080)) {
	311	if ((now = get_timer (start)) >
	312	CFG_FLASH_ERASE_TOUT) {
3bac3513	313	printf ("Timeout\n");
49822e23 WD	314	addr[0] = 0x00B000B0; /* suspend erase */
49822e23 WD	315	addr[0] = 0x00FF00FF; /* to read mode */
3bac3513 WD	316	return 1;
	317	}
	318
	319	/* show that we're waiting */
49822e23	320	if ((now - last) > 1000) { /* every second */
3bac3513 WD	321	putc ('.');
	322	last = now;
	323	}
	324	}
	325
	326	addr[0] = 0x00FF00FF;
	327	}
	328	}
	329	printf (" done\n");
	330	return 0;
	331	}
	332
	333	/*-----------------------------------------------------------------------
	334	* Copy memory to flash, returns:
	335	* 0 - OK
	336	* 1 - write timeout
	337	* 2 - Flash not erased
	338	* 4 - Flash not identified
	339	*/
	340
	341	#define FLASH_WIDTH 8 /* flash bus width in bytes */
	342
49822e23	343	int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
3bac3513 WD	344	{
	345	ulong wp, cp, msr;
	346	int l, rc, i;
	347	ulong data[2];
	348	ulong *datah = &data[0];
	349	ulong *datal = &data[1];
	350
	351	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
49822e23	352	addr, (ulong) src, cnt);
3bac3513 WD	353
	354	if (info->flash_id == FLASH_UNKNOWN) {
	355	return 4;
	356	}
	357
49822e23 WD	358	msr = get_msr ();
49822e23 WD	359	set_msr (msr \| MSR_FP);
3bac3513	360
49822e23	361	wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */
3bac3513 WD	362
	363	/*
	364	* handle unaligned start bytes
	365	*/
	366	if ((l = addr - wp) != 0) {
	367	datah = datal = 0;
	368
	369	for (i = 0, cp = wp; i < l; i++, cp++) {
	370	if (i >= 4) {
	371	datah = (datah << 8) \|
49822e23	372	((*datal & 0xFF000000) >> 24);
3bac3513 WD	373	}
3bac3513 WD	374
49822e23	375	datal = (datal << 8) \| ((uchar ) cp);
3bac3513 WD	376	}
3bac3513 WD	377	for (; i < FLASH_WIDTH && cnt > 0; ++i) {
49822e23	378	char tmp = *src++;
3bac3513 WD	379
	380	if (i >= 4) {
	381	datah = (datah << 8) \|
49822e23	382	((*datal & 0xFF000000) >> 24);
3bac3513 WD	383	}
	384
	385	datal = (datal << 8) \| tmp;
49822e23 WD	386	--cnt;
49822e23 WD	387	++cp;
3bac3513 WD	388	}
	389
	390	for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
	391	if (i >= 4) {
	392	datah = (datah << 8) \|
49822e23	393	((*datal & 0xFF000000) >> 24);
3bac3513 WD	394	}
3bac3513 WD	395
49822e23	396	datal = (datah << 8) \| ((uchar ) cp);
3bac3513 WD	397	}
3bac3513 WD	398
49822e23 WD	399	if ((rc = write_data (info, wp, data)) != 0) {
49822e23 WD	400	set_msr (msr);
3bac3513 WD	401	return (rc);
	402	}
	403
	404	wp += FLASH_WIDTH;
	405	}
	406
	407	/*
	408	* handle FLASH_WIDTH aligned part
	409	*/
	410	while (cnt >= FLASH_WIDTH) {
49822e23 WD	411	datah = (ulong *) src;
	412	datal = (ulong *) (src + 4);
	413	if ((rc = write_data (info, wp, data)) != 0) {
	414	set_msr (msr);
3bac3513 WD	415	return (rc);
3bac3513 WD	416	}
49822e23	417	wp += FLASH_WIDTH;
3bac3513 WD	418	cnt -= FLASH_WIDTH;
	419	src += FLASH_WIDTH;
	420	}
	421
	422	if (cnt == 0) {
49822e23	423	set_msr (msr);
3bac3513 WD	424	return (0);
	425	}
	426
	427	/*
	428	* handle unaligned tail bytes
	429	*/
	430	datah = datal = 0;
	431	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
49822e23	432	char tmp = *src++;
3bac3513 WD	433
3bac3513 WD	434	if (i >= 4) {
49822e23 WD	435	datah = (datah << 8) \| ((*datal & 0xFF000000) >>
49822e23 WD	436	24);
3bac3513 WD	437	}
	438
	439	datal = (datal << 8) \| tmp;
3bac3513 WD	440	--cnt;
	441	}
	442
	443	for (; i < FLASH_WIDTH; ++i, ++cp) {
	444	if (i >= 4) {
49822e23 WD	445	datah = (datah << 8) \| ((*datal & 0xFF000000) >>
49822e23 WD	446	24);
3bac3513 WD	447	}
3bac3513 WD	448
49822e23	449	datal = (datal << 8) \| ((uchar ) cp);
3bac3513 WD	450	}
3bac3513 WD	451
49822e23 WD	452	rc = write_data (info, wp, data);
49822e23 WD	453	set_msr (msr);
3bac3513 WD	454
	455	return (rc);
	456	}
	457
	458	/*-----------------------------------------------------------------------
	459	* Write a word to Flash, returns:
	460	* 0 - OK
	461	* 1 - write timeout
	462	* 2 - Flash not erased
	463	*/
49822e23	464	static int write_data (flash_info_t * info, ulong dest, ulong * data)
3bac3513	465	{
49822e23	466	vu_long addr = (vu_long ) dest;
3bac3513 WD	467	ulong start;
	468	int flag;
	469
	470	/* Check if Flash is (sufficiently) erased */
	471	if (((addr[0] & data[0]) != data[0]) \|\|
49822e23	472	((addr[1] & data[1]) != data[1])) {
3bac3513 WD	473	return (2);
	474	}
	475	/* Disable interrupts which might cause a timeout here */
49822e23	476	flag = disable_interrupts ();
3bac3513	477
49822e23 WD	478	addr[0] = 0x00400040; /* write setup */
49822e23 WD	479	write_via_fpu (addr, data);
3bac3513 WD	480
	481	/* re-enable interrupts if necessary */
	482	if (flag)
49822e23	483	enable_interrupts ();
3bac3513 WD	484
	485	start = get_timer (0);
	486
	487	while (((addr[0] & 0x00800080) != 0x00800080) \|\|
49822e23 WD	488	((addr[1] & 0x00800080) != 0x00800080)) {
49822e23 WD	489	if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
3bac3513 WD	490	addr[0] = 0x00FF00FF; /* restore read mode */
	491	return (1);
	492	}
	493	}
	494
	495	addr[0] = 0x00FF00FF; /* restore read mode */
	496
	497	return (0);
	498	}
	499
	500	/*-----------------------------------------------------------------------
	501	*/
49822e23	502	static void write_via_fpu (vu_long * addr, ulong * data)
3bac3513	503	{
49822e23 WD	504	__asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
49822e23 WD	505	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
3bac3513	506	}
49822e23	507
3bac3513 WD	508	/*-----------------------------------------------------------------------
3bac3513 WD	509	*/
49822e23	510	static __inline__ unsigned long get_msr (void)
3bac3513	511	{
49822e23 WD	512	unsigned long msr;
	513
	514	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
3bac3513	515
49822e23	516	return msr;
3bac3513 WD	517	}
3bac3513 WD	518
49822e23	519	static __inline__ void set_msr (unsigned long msr)
3bac3513	520	{
49822e23	521	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
3bac3513	522	}