[u-boot.git] / drivers / ata / sata_ceva.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2015 - 2016 Xilinx, Inc.
 * Michal Simek <[email protected]>
 */
#include <common.h>
#include <dm.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/hardware.h>

#include <asm/io.h>

/* Vendor Specific Register Offsets */
#define AHCI_VEND_PCFG  0xA4
#define AHCI_VEND_PPCFG 0xA8
#define AHCI_VEND_PP2C  0xAC
#define AHCI_VEND_PP3C  0xB0
#define AHCI_VEND_PP4C  0xB4
#define AHCI_VEND_PP5C  0xB8
#define AHCI_VEND_PAXIC 0xC0
#define AHCI_VEND_PTC   0xC8

/* Vendor Specific Register bit definitions */
#define PAXIC_ADBW_BW64 0x1
#define PAXIC_MAWIDD	(1 << 8)
#define PAXIC_MARIDD	(1 << 16)
#define PAXIC_OTL	(0x4 << 20)

#define PCFG_TPSS_VAL	(0x32 << 16)
#define PCFG_TPRS_VAL	(0x2 << 12)
#define PCFG_PAD_VAL	0x2

#define PPCFG_TTA	0x1FFFE
#define PPCFG_PSSO_EN	(1 << 28)
#define PPCFG_PSS_EN	(1 << 29)
#define PPCFG_ESDF_EN	(1 << 31)

#define PP2C_CIBGMN	0x0F
#define PP2C_CIBGMX	(0x25 << 8)
#define PP2C_CIBGN	(0x18 << 16)
#define PP2C_CINMP	(0x29 << 24)

#define PP3C_CWBGMN	0x04
#define PP3C_CWBGMX	(0x0B << 8)
#define PP3C_CWBGN	(0x08 << 16)
#define PP3C_CWNMP	(0x0F << 24)

#define PP4C_BMX	0x0a
#define PP4C_BNM	(0x08 << 8)
#define PP4C_SFD	(0x4a << 16)
#define PP4C_PTST	(0x06 << 24)

#define PP5C_RIT	0x60216
#define PP5C_RCT	(0x7f0 << 20)

#define PTC_RX_WM_VAL	0x40
#define PTC_RSVD	(1 << 27)

#define PORT0_BASE	0x100
#define PORT1_BASE	0x180

/* Port Control Register Bit Definitions */
#define PORT_SCTL_SPD_GEN3	(0x3 << 4)
#define PORT_SCTL_SPD_GEN2	(0x2 << 4)
#define PORT_SCTL_SPD_GEN1	(0x1 << 4)
#define PORT_SCTL_IPM		(0x3 << 8)

#define PORT_BASE	0x100
#define PORT_OFFSET	0x80
#define NR_PORTS	2
#define DRV_NAME	"ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2	1

static int ceva_init_sata(ulong mmio)
{
	ulong tmp;
	int i;

	/*
	 * AXI Data bus width to 64
	 * Set Mem Addr Read, Write ID for data transfers
	 * Transfer limit to 72 DWord
	 */
	tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
	writel(tmp, mmio + AHCI_VEND_PAXIC);

	/* Set AHCI Enable */
	tmp = readl(mmio + HOST_CTL);
	tmp |= HOST_AHCI_EN;
	writel(tmp, mmio + HOST_CTL);

	for (i = 0; i < NR_PORTS; i++) {
		/* TPSS TPRS scalars, CISE and Port Addr */
		tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
		writel(tmp, mmio + AHCI_VEND_PCFG);

		/* Port Phy Cfg register enables */
		tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
		writel(tmp, mmio + AHCI_VEND_PPCFG);

		/* Rx Watermark setting  */
		tmp = PTC_RX_WM_VAL | PTC_RSVD;
		writel(tmp, mmio + AHCI_VEND_PTC);

		/* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
		tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
		writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
	}
	return 0;
}

static int sata_ceva_probe(struct udevice *dev)
{
	int ret;
	struct scsi_platdata *plat = dev_get_uclass_platdata(dev);

	ceva_init_sata(plat->base);

	ret = ahci_init_one_dm(dev);
	if (ret)
		return ret;

	return ahci_start_ports_dm(dev);
}

static const struct udevice_id sata_ceva_ids[] = {
	{ .compatible = "ceva,ahci-1v84" },
	{ }
};

static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
{
	struct scsi_platdata *plat = dev_get_uclass_platdata(dev);

	plat->base = devfdt_get_addr(dev);
	if (plat->base == FDT_ADDR_T_NONE)
		return -EINVAL;

	/* Hardcode number for ceva sata controller */
	plat->max_lun = 1; /* Actually two but untested */
	plat->max_id = 2;

	return 0;
}

U_BOOT_DRIVER(ceva_host_blk) = {
	.name = "ceva_sata",
	.id = UCLASS_SCSI,
	.of_match = sata_ceva_ids,
	.ops = &scsi_ops,
	.probe = sata_ceva_probe,
	.ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
679b994a MS	2	/*
	3	* (C) Copyright 2015 - 2016 Xilinx, Inc.
	4	* Michal Simek <[email protected]>
679b994a MS	5	*/
679b994a MS	6	#include <common.h>
49c4c78e	7	#include <dm.h>
679b994a MS	8	#include <ahci.h>
	9	#include <scsi.h>
	10	#include <asm/arch/hardware.h>
	11
	12	#include <asm/io.h>
	13
	14	/* Vendor Specific Register Offsets */
	15	#define AHCI_VEND_PCFG 0xA4
	16	#define AHCI_VEND_PPCFG 0xA8
	17	#define AHCI_VEND_PP2C 0xAC
	18	#define AHCI_VEND_PP3C 0xB0
	19	#define AHCI_VEND_PP4C 0xB4
	20	#define AHCI_VEND_PP5C 0xB8
	21	#define AHCI_VEND_PAXIC 0xC0
	22	#define AHCI_VEND_PTC 0xC8
	23
	24	/* Vendor Specific Register bit definitions */
	25	#define PAXIC_ADBW_BW64 0x1
	26	#define PAXIC_MAWIDD (1 << 8)
	27	#define PAXIC_MARIDD (1 << 16)
	28	#define PAXIC_OTL (0x4 << 20)
	29
	30	#define PCFG_TPSS_VAL (0x32 << 16)
	31	#define PCFG_TPRS_VAL (0x2 << 12)
	32	#define PCFG_PAD_VAL 0x2
	33
	34	#define PPCFG_TTA 0x1FFFE
	35	#define PPCFG_PSSO_EN (1 << 28)
	36	#define PPCFG_PSS_EN (1 << 29)
	37	#define PPCFG_ESDF_EN (1 << 31)
	38
	39	#define PP2C_CIBGMN 0x0F
	40	#define PP2C_CIBGMX (0x25 << 8)
	41	#define PP2C_CIBGN (0x18 << 16)
	42	#define PP2C_CINMP (0x29 << 24)
	43
	44	#define PP3C_CWBGMN 0x04
	45	#define PP3C_CWBGMX (0x0B << 8)
	46	#define PP3C_CWBGN (0x08 << 16)
	47	#define PP3C_CWNMP (0x0F << 24)
	48
	49	#define PP4C_BMX 0x0a
	50	#define PP4C_BNM (0x08 << 8)
	51	#define PP4C_SFD (0x4a << 16)
	52	#define PP4C_PTST (0x06 << 24)
	53
	54	#define PP5C_RIT 0x60216
	55	#define PP5C_RCT (0x7f0 << 20)
	56
	57	#define PTC_RX_WM_VAL 0x40
	58	#define PTC_RSVD (1 << 27)
	59
	60	#define PORT0_BASE 0x100
	61	#define PORT1_BASE 0x180
	62
	63	/* Port Control Register Bit Definitions */
	64	#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
	65	#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
	66	#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
	67	#define PORT_SCTL_IPM (0x3 << 8)
	68
	69	#define PORT_BASE 0x100
	70	#define PORT_OFFSET 0x80
	71	#define NR_PORTS 2
72	#define DRV_NAME "ahci-ceva"
73	#define CEVA_FLAG_BROKEN_GEN2 1
74
49c4c78e	75	static int ceva_init_sata(ulong mmio)
679b994a MS	76	{
679b994a MS	77	ulong tmp;
679b994a MS	78	int i;
	79
	80	/*
	81	* AXI Data bus width to 64
	82	* Set Mem Addr Read, Write ID for data transfers
	83	* Transfer limit to 72 DWord
	84	*/
	85	tmp = PAXIC_ADBW_BW64 \| PAXIC_MAWIDD \| PAXIC_MARIDD \| PAXIC_OTL;
	86	writel(tmp, mmio + AHCI_VEND_PAXIC);
	87
	88	/* Set AHCI Enable */
	89	tmp = readl(mmio + HOST_CTL);
	90	tmp \|= HOST_AHCI_EN;
	91	writel(tmp, mmio + HOST_CTL);
	92
	93	for (i = 0; i < NR_PORTS; i++) {
	94	/* TPSS TPRS scalars, CISE and Port Addr */
	95	tmp = PCFG_TPSS_VAL \| PCFG_TPRS_VAL \| (PCFG_PAD_VAL + i);
	96	writel(tmp, mmio + AHCI_VEND_PCFG);
	97
	98	/* Port Phy Cfg register enables */
	99	tmp = PPCFG_TTA \| PPCFG_PSS_EN \| PPCFG_ESDF_EN;
	100	writel(tmp, mmio + AHCI_VEND_PPCFG);
	101
	102	/* Rx Watermark setting */
	103	tmp = PTC_RX_WM_VAL \| PTC_RSVD;
	104	writel(tmp, mmio + AHCI_VEND_PTC);
	105
	106	/* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
	107	tmp = PORT_SCTL_SPD_GEN3 \| PORT_SCTL_IPM;
	108	writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
	109	}
	110	return 0;
	111	}
49c4c78e MS	112
	113	static int sata_ceva_probe(struct udevice *dev)
	114	{
cba64a2a	115	int ret;
1dc64f6c	116	struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
49c4c78e MS	117
49c4c78e MS	118	ceva_init_sata(plat->base);
7cf1afce	119
e81589ea	120	ret = ahci_init_one_dm(dev);
cba64a2a MS	121	if (ret)
	122	return ret;
	123
e81589ea	124	return ahci_start_ports_dm(dev);
49c4c78e MS	125	}
	126
	127	static const struct udevice_id sata_ceva_ids[] = {
	128	{ .compatible = "ceva,ahci-1v84" },
	129	{ }
	130	};
	131
	132	static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
	133	{
1dc64f6c	134	struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
49c4c78e	135
a821c4af	136	plat->base = devfdt_get_addr(dev);
49c4c78e MS	137	if (plat->base == FDT_ADDR_T_NONE)
	138	return -EINVAL;
	139
	140	/* Hardcode number for ceva sata controller */
	141	plat->max_lun = 1; /* Actually two but untested */
	142	plat->max_id = 2;
	143
	144	return 0;
	145	}
	146
	147	U_BOOT_DRIVER(ceva_host_blk) = {
	148	.name = "ceva_sata",
	149	.id = UCLASS_SCSI,
	150	.of_match = sata_ceva_ids,
f6ab5a92	151	.ops = &scsi_ops,
49c4c78e MS	152	.probe = sata_ceva_probe,
49c4c78e MS	153	.ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
49c4c78e	154	};