projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 7ca6f363 BS |
2 | /* |
| 3 | * Configuration settings for the SAMA5D3 Xplained board. | |
| 4 | * | |
| 5 | * Copyright (C) 2014 Atmel Corporation | |
| 6 | * Bo Shen <[email protected]> | |
| 7ca6f363 BS |
7 | */ |
| 8 | ||
| 9 | #ifndef __CONFIG_H | |
| 10 | #define __CONFIG_H | |
| 11 | ||
| df1cf775 | 12 | #include <linux/sizes.h> |
| b2d387bc | 13 | #include "at91-sama5_common.h" |
| 7ca6f363 | 14 | |
| 7ca6f363 BS |
15 | /* |
| 16 | * This needs to be defined for the OHCI code to work but it is defined as | |
| 17 | * ATMEL_ID_UHPHS in the CPU specific header files. | |
| 18 | */ | |
| e61ed48f | 19 | #define ATMEL_ID_UHP 32 |
| 7ca6f363 BS |
20 | |
| 21 | /* | |
| 22 | * Specify the clock enable bit in the PMC_SCER register. | |
| 23 | */ | |
| e61ed48f | 24 | #define ATMEL_PMC_UHP (1 << 6) |
| 7ca6f363 | 25 | |
| 7ca6f363 | 26 | /* SDRAM */ |
| e61ed48f | 27 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 7ca6f363 BS |
28 | #define CONFIG_SYS_SDRAM_SIZE 0x10000000 |
| 29 | ||
| 7ca6f363 | 30 | /* NAND flash */ |
| 7ca6f363 | 31 | #ifdef CONFIG_CMD_NAND |
| e61ed48f | 32 | #define CONFIG_SYS_NAND_BASE 0x60000000 |
| 7ca6f363 BS |
33 | /* our ALE is AD21 */ |
| 34 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
| 35 | /* our CLE is AD22 */ | |
| 36 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
| 8f1a80e9 | 37 | #endif |
| 7ca6f363 | 38 | |
| cd23aac4 | 39 | /* SPL */ |
| cd23aac4 | 40 | |
| df1cf775 | 41 | /* size of u-boot.bin to load */ |
| cd23aac4 | 42 | |
| ea83ea5a | 43 | /* Falcon boot support on raw MMC */ |
| ea83ea5a | 44 | /* U-Boot proper stored by default at 0x200 (256 KiB) */ |
| ea83ea5a | 45 | |
| cd23aac4 | 46 | #endif |