[u-boot.git] / include / configs / ls1021atsn.h

/* SPDX-License-Identifier: GPL-2.0
 * Copyright 2016-2019 NXP
 * Copyright 2019 Vladimir Oltean <[email protected]>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

/* XHCI Support - enabled by default */

#define DDR_SDRAM_CFG			0x470c0008
#define DDR_CS0_BNDS			0x008000bf
#define DDR_CS0_CONFIG			0x80014302
#define DDR_TIMING_CFG_0		0x50550004
#define DDR_TIMING_CFG_1		0xbcb38c56
#define DDR_TIMING_CFG_2		0x0040d120
#define DDR_TIMING_CFG_3		0x010e1000
#define DDR_TIMING_CFG_4		0x00000001
#define DDR_TIMING_CFG_5		0x03401400
#define DDR_SDRAM_CFG_2			0x00401010
#define DDR_SDRAM_MODE			0x00061c60
#define DDR_SDRAM_MODE_2		0x00180000
#define DDR_SDRAM_INTERVAL		0x18600618
#define DDR_DDR_WRLVL_CNTL		0x8655f605
#define DDR_DDR_WRLVL_CNTL_2		0x05060607
#define DDR_DDR_WRLVL_CNTL_3		0x05050505
#define DDR_DDR_CDR1			0x80040000
#define DDR_DDR_CDR2			0x00000001
#define DDR_SDRAM_CLK_CNTL		0x02000000
#define DDR_DDR_ZQ_CNTL			0x89080600
#define DDR_CS0_CONFIG_2		0
#define DDR_SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG2_D_INIT		0x00000010
#define DDR_CDR2_VREF_TRAIN_EN		0x00000080
#define SDRAM_CFG2_FRC_SR		0x80000000
#define SDRAM_CFG_BI			0x00000001

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
#endif /* ifdef CONFIG_NXP_ESBC */

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw U-Boot image instead of FIT image.
 */
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif

#define PHYS_SDRAM			0x80000000
#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

/* I2C */

/* PCIe */
#define FSL_PCIE_COMPAT			"fsl,ls1021a-pcie"

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE

#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0"		\
	"initrd_high=0xffffffff\0"					\
	"kernel_addr=0x61000000\0"					\
	"kernelheader_addr=0x60800000\0"				\
	"scriptaddr=0x80000000\0"					\
	"scripthdraddr=0x80080000\0"					\
	"fdtheader_addr_r=0x80100000\0"					\
	"kernelheader_addr_r=0x80200000\0"				\
	"kernel_addr_r=0x80008000\0"					\
	"kernelheader_size=0x40000\0"					\
	"fdt_addr_r=0x8f000000\0"					\
	"ramdisk_addr_r=0xa0000000\0"					\
	"load_addr=0x80008000\0"					\
	"kernel_size=0x2800000\0"					\
	"kernel_addr_sd=0x8000\0"					\
	"kernel_size_sd=0x14000\0"					\
	"kernelhdr_addr_sd=0x4000\0"					\
	"kernelhdr_size_sd=0x10\0"					\
	BOOTENV								\
	"boot_scripts=ls1021atsn_boot.scr\0"				\
	"boot_script_hdr=hdr_ls1021atsn_bs.out\0"			\
		"scan_dev_for_boot_part="				\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "						\
		"done\0"						\
	"scan_dev_for_boot="						\
		"echo Scanning ${devtype} "				\
				"${devnum}:${distro_bootpart}...; "	\
		"for prefix in ${boot_prefixes}; do "			\
			"run scan_dev_for_scripts; "			\
			"run scan_dev_for_extlinux; "			\
		"done;"							\
		"\0"							\
	"boot_a_script="						\
		"load ${devtype} ${devnum}:${distro_bootpart} "		\
			"${scriptaddr} ${prefix}${script}; "		\
		"env exists secureboot && load ${devtype} "		\
			"${devnum}:${distro_bootpart} "			\
			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
			"&& esbc_validate ${scripthdraddr};"		\
		"source ${scriptaddr}\0"				\
	"qspi_bootcmd=echo Trying load from qspi..;"			\
		"sf probe && sf read $load_addr "			\
		"$kernel_addr $kernel_size; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"				\
	"sd_bootcmd=echo Trying load from SD ..;"			\
		"mmcinfo && mmc read $load_addr "			\
		"$kernel_addr_sd $kernel_size_sd && "			\
		"env exists secureboot && mmc read $kernelheader_addr_r " \
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"		\
		"bootm $load_addr#$board\0"

/* Miscellaneous configurable options */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)

#define CONFIG_LS102XA_STREAM_ID

/* Environment */

#endif
Commit	Line	Data
87821220	1	/* SPDX-License-Identifier: GPL-2.0
66fd01fe	2	* Copyright 2016-2019 NXP
87821220 JW	3	* Copyright 2019 Vladimir Oltean <[email protected]>
	4	*/
	5
	6	#ifndef __CONFIG_H
	7	#define __CONFIG_H
	8
87821220 JW	9	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	10	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	11
	12	/* XHCI Support - enabled by default */
87821220	13
87821220 JW	14	#define DDR_SDRAM_CFG 0x470c0008
	15	#define DDR_CS0_BNDS 0x008000bf
	16	#define DDR_CS0_CONFIG 0x80014302
	17	#define DDR_TIMING_CFG_0 0x50550004
	18	#define DDR_TIMING_CFG_1 0xbcb38c56
	19	#define DDR_TIMING_CFG_2 0x0040d120
	20	#define DDR_TIMING_CFG_3 0x010e1000
	21	#define DDR_TIMING_CFG_4 0x00000001
	22	#define DDR_TIMING_CFG_5 0x03401400
	23	#define DDR_SDRAM_CFG_2 0x00401010
	24	#define DDR_SDRAM_MODE 0x00061c60
	25	#define DDR_SDRAM_MODE_2 0x00180000
	26	#define DDR_SDRAM_INTERVAL 0x18600618
	27	#define DDR_DDR_WRLVL_CNTL 0x8655f605
	28	#define DDR_DDR_WRLVL_CNTL_2 0x05060607
	29	#define DDR_DDR_WRLVL_CNTL_3 0x05050505
	30	#define DDR_DDR_CDR1 0x80040000
	31	#define DDR_DDR_CDR2 0x00000001
	32	#define DDR_SDRAM_CLK_CNTL 0x02000000
	33	#define DDR_DDR_ZQ_CNTL 0x89080600
	34	#define DDR_CS0_CONFIG_2 0
	35	#define DDR_SDRAM_CFG_MEM_EN 0x80000000
	36	#define SDRAM_CFG2_D_INIT 0x00000010
	37	#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
	38	#define SDRAM_CFG2_FRC_SR 0x80000000
	39	#define SDRAM_CFG_BI 0x00000001
	40
87821220	41	#ifdef CONFIG_SD_BOOT
bba4c7f9	42	#ifdef CONFIG_NXP_ESBC
87821220	43	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
bba4c7f9	44	#endif /* ifdef CONFIG_NXP_ESBC */
87821220	45
87821220 JW	46	#ifdef CONFIG_U_BOOT_HDR_SIZE
	47	/*
	48	* HDR would be appended at end of image and copied to DDR along
	49	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	50	* size increases then increase this size in case of secure boot as
	51	* it uses raw U-Boot image instead of FIT image.
	52	*/
87821220 JW	53	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
	54	#endif
	55
87821220 JW	56	#define PHYS_SDRAM 0x80000000
	57	#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	58
	59	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	60	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	61
87821220	62	/* Serial Port */
87821220 JW	63	#define CONFIG_SYS_NS16550_SERIAL
	64	#ifndef CONFIG_DM_SERIAL
	65	#define CONFIG_SYS_NS16550_REG_SIZE 1
	66	#endif
	67	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	68
87821220	69	/* I2C */
87821220	70
87821220	71	/* PCIe */
87821220	72	#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
87821220	73
87821220 JW	74	#define CONFIG_HWCONFIG
	75	#define HWCONFIG_BUFFER_SIZE 256
	76
	77	#define CONFIG_FSL_DEVICE_DISABLE
	78
	79	#define BOOT_TARGET_DEVICES(func) \
	80	func(MMC, mmc, 0) \
	81	func(USB, usb, 0) \
	82	func(DHCP, dhcp, na)
	83	#include <config_distro_bootcmd.h>
	84
	85	#define CONFIG_EXTRA_ENV_SETTINGS \
	86	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	87	"initrd_high=0xffffffff\0" \
87821220 JW	88	"kernel_addr=0x61000000\0" \
	89	"kernelheader_addr=0x60800000\0" \
	90	"scriptaddr=0x80000000\0" \
	91	"scripthdraddr=0x80080000\0" \
	92	"fdtheader_addr_r=0x80100000\0" \
	93	"kernelheader_addr_r=0x80200000\0" \
	94	"kernel_addr_r=0x80008000\0" \
	95	"kernelheader_size=0x40000\0" \
	96	"fdt_addr_r=0x8f000000\0" \
	97	"ramdisk_addr_r=0xa0000000\0" \
	98	"load_addr=0x80008000\0" \
	99	"kernel_size=0x2800000\0" \
	100	"kernel_addr_sd=0x8000\0" \
	101	"kernel_size_sd=0x14000\0" \
	102	"kernelhdr_addr_sd=0x4000\0" \
	103	"kernelhdr_size_sd=0x10\0" \
	104	BOOTENV \
	105	"boot_scripts=ls1021atsn_boot.scr\0" \
	106	"boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
	107	"scan_dev_for_boot_part=" \
	108	"part list ${devtype} ${devnum} devplist; " \
	109	"env exists devplist \|\| setenv devplist 1; " \
	110	"for distro_bootpart in ${devplist}; do " \
	111	"if fstype ${devtype} " \
	112	"${devnum}:${distro_bootpart} " \
	113	"bootfstype; then " \
	114	"run scan_dev_for_boot; " \
	115	"fi; " \
	116	"done\0" \
	117	"scan_dev_for_boot=" \
	118	"echo Scanning ${devtype} " \
	119	"${devnum}:${distro_bootpart}...; " \
	120	"for prefix in ${boot_prefixes}; do " \
	121	"run scan_dev_for_scripts; " \
	122	"run scan_dev_for_extlinux; " \
	123	"done;" \
	124	"\0" \
	125	"boot_a_script=" \
	126	"load ${devtype} ${devnum}:${distro_bootpart} " \
	127	"${scriptaddr} ${prefix}${script}; " \
	128	"env exists secureboot && load ${devtype} " \
	129	"${devnum}:${distro_bootpart} " \
	130	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	131	"&& esbc_validate ${scripthdraddr};" \
	132	"source ${scriptaddr}\0" \
	133	"qspi_bootcmd=echo Trying load from qspi..;" \
	134	"sf probe && sf read $load_addr " \
	135	"$kernel_addr $kernel_size; env exists secureboot " \
	136	"&& sf read $kernelheader_addr_r $kernelheader_addr " \
	137	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	138	"bootm $load_addr#$board\0" \
	139	"sd_bootcmd=echo Trying load from SD ..;" \
	140	"mmcinfo && mmc read $load_addr " \
	141	"$kernel_addr_sd $kernel_size_sd && " \
	142	"env exists secureboot && mmc read $kernelheader_addr_r " \
	143	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	144	" && esbc_validate ${kernelheader_addr_r};" \
	145	"bootm $load_addr#$board\0"
	146
	147	/* Miscellaneous configurable options */
c463eeb4 AW	148	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
c463eeb4 AW	149
87821220 JW	150	#define CONFIG_LS102XA_STREAM_ID
87821220 JW	151
87821220	152	/* Environment */
87821220	153
87821220	154	#endif