projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 864ac2cf MS |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* | |
| 3 | * Copyright (c) 2020 Engicam srl | |
| 4 | * Copyright (c) 2022 Amarula Solutions(India) | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __IMX8MP_ICORE_MX8MP_H | |
| 8 | #define __IMX8MP_ICORE_MX8MP_H | |
| 9 | ||
| 10 | #include <linux/sizes.h> | |
| 11 | #include <linux/stringify.h> | |
| 12 | #include <asm/arch/imx-regs.h> | |
| 13 | ||
| 864ac2cf MS |
14 | #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) |
| 15 | ||
| 16 | #ifdef CONFIG_SPL_BUILD | |
| 17 | /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ | |
| 18 | ||
| 19 | #define CONFIG_POWER_PCA9450 | |
| 20 | ||
| 21 | #endif | |
| 22 | ||
| 23 | #if defined(CONFIG_CMD_NET) | |
| 24 | #define CONFIG_FEC_MXC_PHYADDR 1 | |
| 25 | ||
| 26 | #define DWC_NET_PHYADDR 1 | |
| 27 | ||
| 28 | #define PHY_ANEG_TIMEOUT 20000 | |
| 29 | ||
| 30 | #endif | |
| 31 | ||
| 32 | #define BOOT_TARGET_DEVICES(func) \ | |
| 33 | func(MMC, mmc, 1) \ | |
| 34 | func(MMC, mmc, 2) | |
| 35 | ||
| 36 | #include <config_distro_bootcmd.h> | |
| 37 | ||
| 38 | /* Initial environment variables */ | |
| 39 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 40 | BOOTENV \ | |
| 41 | "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | |
| 42 | "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | |
| 43 | "image=Image\0" \ | |
| 44 | "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ | |
| 45 | "fdt_addr_r=0x43000000\0" \ | |
| 46 | "boot_fdt=try\0" \ | |
| 47 | "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ | |
| 48 | "initrd_addr=0x43800000\0" \ | |
| 49 | "bootm_size=0x10000000\0" \ | |
| 50 | "mmcpart=1\0" \ | |
| 51 | "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ | |
| 52 | ||
| 53 | /* Link Definitions */ | |
| 54 | ||
| 55 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 | |
| 56 | #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 | |
| 57 | ||
| 58 | /* Totally 2GB DDR */ | |
| 59 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
| 60 | #define PHYS_SDRAM 0x40000000 | |
| 61 | #define PHYS_SDRAM_SIZE 0x80000000 | |
| 62 | ||
| 63 | #endif /* __IMX8MP_ICORE_MX8MP_H */ |