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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c8a7ba9e TC |
2 | /* |
3 | * Copyright (C) 2015 Thomas Chou <[email protected]> | |
c8a7ba9e TC |
4 | */ |
5 | ||
b953ec2b PD |
6 | #define LOG_CATEGORY UCLASS_TIMER |
7 | ||
a5d4f861 | 8 | #include <clk.h> |
35761216 | 9 | #include <cpu.h> |
c8a7ba9e | 10 | #include <dm.h> |
401d1c4f | 11 | #include <asm/global_data.h> |
c8336975 | 12 | #include <dm/lists.h> |
a5d4f861 | 13 | #include <dm/device_compat.h> |
c8336975 | 14 | #include <dm/device-internal.h> |
b61e8b0c | 15 | #include <dm/root.h> |
c8a7ba9e | 16 | #include <errno.h> |
a5d4f861 | 17 | #include <init.h> |
c8a7ba9e | 18 | #include <timer.h> |
61b29b82 | 19 | #include <linux/err.h> |
8272d4cb | 20 | #include <relocate.h> |
c8a7ba9e | 21 | |
579eb5a0 BM |
22 | DECLARE_GLOBAL_DATA_PTR; |
23 | ||
c8a7ba9e | 24 | /* |
435ae76e | 25 | * Implement a timer uclass to work with lib/time.c. The timer is usually |
9ca07ebb | 26 | * a 32/64 bits free-running up counter. The get_rate() method is used to get |
c8a7ba9e | 27 | * the input clock frequency of the timer. The get_count() method is used |
9ca07ebb | 28 | * to get the current 64 bits count value. If the hardware is counting down, |
c8a7ba9e TC |
29 | * the value should be inversed inside the method. There may be no real |
30 | * tick, and no timer interrupt. | |
31 | */ | |
32 | ||
4f051824 | 33 | int notrace timer_get_count(struct udevice *dev, u64 *count) |
c8a7ba9e | 34 | { |
1e766a04 | 35 | struct timer_ops *ops = timer_get_ops(dev); |
c8a7ba9e TC |
36 | |
37 | if (!ops->get_count) | |
38 | return -ENOSYS; | |
39 | ||
8af7bb91 SA |
40 | *count = ops->get_count(dev); |
41 | return 0; | |
c8a7ba9e TC |
42 | } |
43 | ||
4f051824 | 44 | unsigned long notrace timer_get_rate(struct udevice *dev) |
c8a7ba9e | 45 | { |
0fd3d911 | 46 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
c8a7ba9e TC |
47 | |
48 | return uc_priv->clock_rate; | |
49 | } | |
50 | ||
579eb5a0 BM |
51 | static int timer_pre_probe(struct udevice *dev) |
52 | { | |
dcfc42b1 SG |
53 | if (CONFIG_IS_ENABLED(OF_REAL)) { |
54 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); | |
55 | struct clk timer_clk; | |
56 | int err; | |
57 | ulong ret; | |
579eb5a0 | 58 | |
dcfc42b1 SG |
59 | /* |
60 | * It is possible that a timer device has a null ofnode | |
61 | */ | |
62 | if (!dev_has_ofnode(dev)) | |
63 | return 0; | |
7efb4a6e | 64 | |
dcfc42b1 SG |
65 | err = clk_get_by_index(dev, 0, &timer_clk); |
66 | if (!err) { | |
67 | ret = clk_get_rate(&timer_clk); | |
d6d8078c AB |
68 | if (!IS_ERR_VALUE(ret)) { |
69 | uc_priv->clock_rate = ret; | |
70 | return 0; | |
71 | } | |
dcfc42b1 | 72 | } |
d6d8078c AB |
73 | |
74 | uc_priv->clock_rate = dev_read_u32_default(dev, "clock-frequency", 0); | |
b61e8b0c | 75 | } |
579eb5a0 BM |
76 | |
77 | return 0; | |
78 | } | |
79 | ||
0a7edce0 SW |
80 | static int timer_post_probe(struct udevice *dev) |
81 | { | |
82 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); | |
83 | ||
84 | if (!uc_priv->clock_rate) | |
85 | return -EINVAL; | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
529d5f96 | 90 | #if CONFIG_IS_ENABLED(CPU) |
35761216 SA |
91 | int timer_timebase_fallback(struct udevice *dev) |
92 | { | |
93 | struct udevice *cpu; | |
8a8d24bd | 94 | struct cpu_plat *cpu_plat; |
35761216 SA |
95 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
96 | ||
97 | /* Did we get our clock rate from the device tree? */ | |
98 | if (uc_priv->clock_rate) | |
99 | return 0; | |
100 | ||
101 | /* Fall back to timebase-frequency */ | |
102 | dev_dbg(dev, "missing clocks or clock-frequency property; falling back on timebase-frequency\n"); | |
103 | cpu = cpu_get_current_dev(); | |
104 | if (!cpu) | |
105 | return -ENODEV; | |
106 | ||
caa4daa2 | 107 | cpu_plat = dev_get_parent_plat(cpu); |
35761216 SA |
108 | if (!cpu_plat) |
109 | return -ENODEV; | |
110 | ||
111 | uc_priv->clock_rate = cpu_plat->timebase_freq; | |
112 | return 0; | |
113 | } | |
114 | #endif | |
115 | ||
9ca07ebb BM |
116 | u64 timer_conv_64(u32 count) |
117 | { | |
118 | /* increment tbh if tbl has rolled over */ | |
119 | if (count < gd->timebase_l) | |
120 | gd->timebase_h++; | |
121 | gd->timebase_l = count; | |
122 | return ((u64)gd->timebase_h << 32) | gd->timebase_l; | |
123 | } | |
124 | ||
4aa5053d | 125 | int dm_timer_init(void) |
c8336975 | 126 | { |
c8336975 | 127 | struct udevice *dev = NULL; |
b61e8b0c | 128 | __maybe_unused ofnode node; |
c8336975 M |
129 | int ret; |
130 | ||
131 | if (gd->timer) | |
132 | return 0; | |
133 | ||
af823151 PT |
134 | /* |
135 | * Directly access gd->dm_root to suppress error messages, if the | |
136 | * virtual root driver does not yet exist. | |
137 | */ | |
138 | if (gd->dm_root == NULL) | |
139 | return -EAGAIN; | |
140 | ||
dcfc42b1 SG |
141 | if (CONFIG_IS_ENABLED(OF_REAL)) { |
142 | /* Check for a chosen timer to be used for tick */ | |
143 | node = ofnode_get_chosen_node("tick-timer"); | |
144 | ||
145 | if (ofnode_valid(node) && | |
146 | uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) { | |
147 | /* | |
148 | * If the timer is not marked to be bound before | |
149 | * relocation, bind it anyway. | |
150 | */ | |
776bf6a5 | 151 | if (!lists_bind_fdt(dm_root(), node, &dev, NULL, false)) { |
dcfc42b1 SG |
152 | ret = device_probe(dev); |
153 | if (ret) | |
154 | return ret; | |
155 | } | |
b61e8b0c PT |
156 | } |
157 | } | |
b61e8b0c PT |
158 | |
159 | if (!dev) { | |
160 | /* Fall back to the first available timer */ | |
3f603cbb | 161 | ret = uclass_first_device_err(UCLASS_TIMER, &dev); |
c8336975 M |
162 | if (ret) |
163 | return ret; | |
c8336975 M |
164 | } |
165 | ||
166 | if (dev) { | |
167 | gd->timer = dev; | |
168 | return 0; | |
169 | } | |
170 | ||
171 | return -ENODEV; | |
172 | } | |
173 | ||
c8a7ba9e TC |
174 | UCLASS_DRIVER(timer) = { |
175 | .id = UCLASS_TIMER, | |
176 | .name = "timer", | |
579eb5a0 | 177 | .pre_probe = timer_pre_probe, |
a5d80113 | 178 | .flags = DM_UC_FLAG_SEQ_ALIAS, |
0a7edce0 | 179 | .post_probe = timer_post_probe, |
41575d8e | 180 | .per_device_auto = sizeof(struct timer_dev_priv), |
c8a7ba9e | 181 | }; |