[u-boot.git] / drivers / spi / pl022_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2012
 * Armando Visconti, STMicroelectronics, [email protected].
 *
 * (C) Copyright 2018
 * Quentin Schulz, Bootlin, [email protected]
 *
 * Driver for ARM PL022 SPI Controller.
 */

#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <fdtdec.h>
#include <linux/io.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <spi.h>
#include <linux/printk.h>

#define SSP_CR0		0x000
#define SSP_CR1		0x004
#define SSP_DR		0x008
#define SSP_SR		0x00C
#define SSP_CPSR	0x010
#define SSP_IMSC	0x014
#define SSP_RIS		0x018
#define SSP_MIS		0x01C
#define SSP_ICR		0x020
#define SSP_DMACR	0x024
#define SSP_CSR		0x030 /* vendor extension */
#define SSP_ITCR	0x080
#define SSP_ITIP	0x084
#define SSP_ITOP	0x088
#define SSP_TDR		0x08C

#define SSP_PID0	0xFE0
#define SSP_PID1	0xFE4
#define SSP_PID2	0xFE8
#define SSP_PID3	0xFEC

#define SSP_CID0	0xFF0
#define SSP_CID1	0xFF4
#define SSP_CID2	0xFF8
#define SSP_CID3	0xFFC

/* SSP Control Register 0  - SSP_CR0 */
#define SSP_CR0_SPO		(0x1 << 6)
#define SSP_CR0_SPH		(0x1 << 7)
#define SSP_CR0_BIT_MODE(x)	((x) - 1)
#define SSP_SCR_MIN		(0x00)
#define SSP_SCR_MAX		(0xFF)
#define SSP_SCR_SHFT		8
#define DFLT_CLKRATE		2

/* SSP Control Register 1  - SSP_CR1 */
#define SSP_CR1_MASK_SSE	(0x1 << 1)

#define SSP_CPSR_MIN		(0x02)
#define SSP_CPSR_MAX		(0xFE)
#define DFLT_PRESCALE		(0x40)

/* SSP Status Register - SSP_SR */
#define SSP_SR_MASK_TFE		(0x1 << 0) /* Transmit FIFO empty */
#define SSP_SR_MASK_TNF		(0x1 << 1) /* Transmit FIFO not full */
#define SSP_SR_MASK_RNE		(0x1 << 2) /* Receive FIFO not empty */
#define SSP_SR_MASK_RFF		(0x1 << 3) /* Receive FIFO full */
#define SSP_SR_MASK_BSY		(0x1 << 4) /* Busy Flag */

struct pl022_spi_pdata {
	fdt_addr_t addr;
	fdt_size_t size;
	unsigned int freq;
#if CONFIG_IS_ENABLED(DM_GPIO)
	struct gpio_desc cs_gpio;
#endif
};

struct pl022_spi_slave {
	void *base;
	unsigned int freq;
};

/*
 * ARM PL022 exists in different 'flavors'.
 * This drivers currently support the standard variant (0x00041022), that has a
 * 16bit wide and 8 locations deep TX/RX FIFO.
 */
static int pl022_is_supported(struct pl022_spi_slave *ps)
{
	/* PL022 version is 0x00041022 */
	if ((readw(ps->base + SSP_PID0) == 0x22) &&
	    (readw(ps->base + SSP_PID1) == 0x10) &&
	    ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
	    (readw(ps->base + SSP_PID3) == 0x00))
		return 1;

	return 0;
}

static int pl022_spi_probe(struct udevice *bus)
{
	struct pl022_spi_pdata *plat = dev_get_plat(bus);
	struct pl022_spi_slave *ps = dev_get_priv(bus);

	ps->base = ioremap(plat->addr, plat->size);
	ps->freq = plat->freq;

	/* Check the PL022 version */
	if (!pl022_is_supported(ps))
		return -ENOTSUPP;

	/* 8 bits per word, high polarity and default clock rate */
	writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
	writew(DFLT_PRESCALE, ps->base + SSP_CPSR);

	return 0;
}

static void pl022_spi_flush(struct pl022_spi_slave *ps)
{
	do {
		while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
			readw(ps->base + SSP_DR);
	} while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
}

static int pl022_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct pl022_spi_slave *ps = dev_get_priv(bus);
	u16 reg;

	/* Enable the SPI hardware */
	reg = readw(ps->base + SSP_CR1);
	reg |= SSP_CR1_MASK_SSE;
	writew(reg, ps->base + SSP_CR1);

	pl022_spi_flush(ps);

	return 0;
}

static int pl022_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct pl022_spi_slave *ps = dev_get_priv(bus);
	u16 reg;

	pl022_spi_flush(ps);

	/* Disable the SPI hardware */
	reg = readw(ps->base + SSP_CR1);
	reg &= ~SSP_CR1_MASK_SSE;
	writew(reg, ps->base + SSP_CR1);

	return 0;
}

static void pl022_spi_set_cs(struct udevice *dev, bool on)
{
#if CONFIG_IS_ENABLED(DM_GPIO)
	struct udevice *bus = dev->parent;
	struct pl022_spi_pdata *plat = dev_get_plat(bus);

	if (dm_gpio_is_valid(&plat->cs_gpio))
		dm_gpio_set_value(&plat->cs_gpio, on ? 1 : 0);
#endif
}

static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
			  const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct pl022_spi_slave *ps = dev_get_priv(bus);
	u32		len_tx = 0, len_rx = 0, len;
	u32		ret = 0;
	const u8	*txp = dout;
	u8		*rxp = din, value;

	if (bitlen == 0)
		/* Finish any previously submitted transfers */
		goto done;

	/*
	 * TODO: The controller can do non-multiple-of-8 bit
	 * transfers, but this driver currently doesn't support it.
	 *
	 * It's also not clear how such transfers are supposed to be
	 * represented as a stream of bytes...this is a limitation of
	 * the current SPI interface.
	 */
	if (bitlen % 8) {
		/* Errors always terminate an ongoing transfer */
		flags |= SPI_XFER_END;
		ret = -1;
		goto done;
	}

	if (flags & SPI_XFER_BEGIN)
		pl022_spi_set_cs(dev, true);

	len = bitlen / 8;

	while (len_tx < len) {
		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
			value = txp ? *txp++ : 0;
			writew(value, ps->base + SSP_DR);
			len_tx++;
		}

		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
			value = readw(ps->base + SSP_DR);
			if (rxp)
				*rxp++ = value;
			len_rx++;
		}
	}

	while (len_rx < len_tx) {
		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
			value = readw(ps->base + SSP_DR);
			if (rxp)
				*rxp++ = value;
			len_rx++;
		}
	}

done:
	if (flags & SPI_XFER_END)
		pl022_spi_set_cs(dev, false);

	return ret;
}

static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
{
	return rate / (cpsdvsr * (1 + scr));
}

static int pl022_spi_set_speed(struct udevice *bus, uint speed)
{
	struct pl022_spi_slave *ps = dev_get_priv(bus);
	u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
	    best_cpsr = cpsr;
	u32 min, max, best_freq = 0, tmp;
	u32 rate = ps->freq;
	bool found = false;

	max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
	min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);

	if (speed > max || speed < min) {
		pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
		       speed, min, max);
		return -EINVAL;
	}

	while (cpsr <= SSP_CPSR_MAX && !found) {
		while (scr <= SSP_SCR_MAX) {
			tmp = spi_rate(rate, cpsr, scr);

			if (abs(speed - tmp) < abs(speed - best_freq)) {
				best_freq = tmp;
				best_cpsr = cpsr;
				best_scr = scr;

				if (tmp == speed) {
					found = true;
					break;
				}
			}

			scr++;
		}
		cpsr += 2;
		scr = SSP_SCR_MIN;
	}

	writew(best_cpsr, ps->base + SSP_CPSR);
	cr0 = readw(ps->base + SSP_CR0);
	writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);

	return 0;
}

static int pl022_spi_set_mode(struct udevice *bus, uint mode)
{
	struct pl022_spi_slave *ps = dev_get_priv(bus);
	u16 reg;

	reg = readw(ps->base + SSP_CR0);
	reg &= ~(SSP_CR0_SPH | SSP_CR0_SPO);
	if (mode & SPI_CPHA)
		reg |= SSP_CR0_SPH;
	if (mode & SPI_CPOL)
		reg |= SSP_CR0_SPO;
	writew(reg, ps->base + SSP_CR0);

	return 0;
}

static int pl022_cs_info(struct udevice *bus, uint cs,
			 struct spi_cs_info *info)
{
	return 0;
}

static const struct dm_spi_ops pl022_spi_ops = {
	.claim_bus      = pl022_spi_claim_bus,
	.release_bus    = pl022_spi_release_bus,
	.xfer           = pl022_spi_xfer,
	.set_speed      = pl022_spi_set_speed,
	.set_mode       = pl022_spi_set_mode,
	.cs_info        = pl022_cs_info,
};

#if CONFIG_IS_ENABLED(OF_REAL)
static int pl022_spi_of_to_plat(struct udevice *bus)
{
	struct pl022_spi_pdata *plat = dev_get_plat(bus);
	const void *fdt = gd->fdt_blob;
	int node = dev_of_offset(bus);
	struct clk clkdev;
	int ret;

	plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);

	ret = clk_get_by_index(bus, 0, &clkdev);
	if (ret)
		return ret;

	plat->freq = clk_get_rate(&clkdev);

#if CONFIG_IS_ENABLED(DM_GPIO)
	ret = gpio_request_by_name(bus, "cs-gpios", 0, &plat->cs_gpio,
				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
	if (ret < 0 && ret != -ENOENT)
		return ret;
#endif

	return 0;
}

static const struct udevice_id pl022_spi_ids[] = {
	{ .compatible = "arm,pl022" },
	{ }
};
#endif

U_BOOT_DRIVER(pl022_spi) = {
	.name   = "pl022_spi",
	.id     = UCLASS_SPI,
#if CONFIG_IS_ENABLED(OF_REAL)
	.of_match = pl022_spi_ids,
	.of_to_plat = pl022_spi_of_to_plat,
#endif
	.ops    = &pl022_spi_ops,
	.plat_auto	= sizeof(struct pl022_spi_pdata),
	.priv_auto	= sizeof(struct pl022_spi_slave),
	.probe  = pl022_spi_probe,
};
Commit	Line	Data
8a4791fa QS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2012
eae488b7	4	* Armando Visconti, STMicroelectronics, [email protected].
8a4791fa QS	5	*
	6	* (C) Copyright 2018
	7	* Quentin Schulz, Bootlin, [email protected]
	8	*
	9	* Driver for ARM PL022 SPI Controller.
	10	*/
	11
8a4791fa	12	#include <clk.h>
8a4791fa	13	#include <dm.h>
47d9ae54	14	#include <dm/device_compat.h>
03612861	15	#include <fdtdec.h>
8a4791fa	16	#include <linux/io.h>
401d1c4f	17	#include <asm/global_data.h>
47d9ae54	18	#include <asm/gpio.h>
8a4791fa	19	#include <spi.h>
1e94b46f	20	#include <linux/printk.h>
8a4791fa QS	21
	22	#define SSP_CR0 0x000
	23	#define SSP_CR1 0x004
	24	#define SSP_DR 0x008
	25	#define SSP_SR 0x00C
	26	#define SSP_CPSR 0x010
	27	#define SSP_IMSC 0x014
	28	#define SSP_RIS 0x018
	29	#define SSP_MIS 0x01C
	30	#define SSP_ICR 0x020
	31	#define SSP_DMACR 0x024
	32	#define SSP_CSR 0x030 /* vendor extension */
	33	#define SSP_ITCR 0x080
	34	#define SSP_ITIP 0x084
	35	#define SSP_ITOP 0x088
	36	#define SSP_TDR 0x08C
	37
	38	#define SSP_PID0 0xFE0
	39	#define SSP_PID1 0xFE4
	40	#define SSP_PID2 0xFE8
	41	#define SSP_PID3 0xFEC
	42
	43	#define SSP_CID0 0xFF0
	44	#define SSP_CID1 0xFF4
	45	#define SSP_CID2 0xFF8
	46	#define SSP_CID3 0xFFC
	47
	48	/* SSP Control Register 0 - SSP_CR0 */
	49	#define SSP_CR0_SPO (0x1 << 6)
	50	#define SSP_CR0_SPH (0x1 << 7)
	51	#define SSP_CR0_BIT_MODE(x) ((x) - 1)
	52	#define SSP_SCR_MIN (0x00)
	53	#define SSP_SCR_MAX (0xFF)
	54	#define SSP_SCR_SHFT 8
	55	#define DFLT_CLKRATE 2
	56
	57	/* SSP Control Register 1 - SSP_CR1 */
	58	#define SSP_CR1_MASK_SSE (0x1 << 1)
	59
	60	#define SSP_CPSR_MIN (0x02)
	61	#define SSP_CPSR_MAX (0xFE)
	62	#define DFLT_PRESCALE (0x40)
	63
	64	/* SSP Status Register - SSP_SR */
	65	#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */
	66	#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */
	67	#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */
	68	#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */
	69	#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */
	70
03612861 SH	71	struct pl022_spi_pdata {
	72	fdt_addr_t addr;
	73	fdt_size_t size;
	74	unsigned int freq;
47d9ae54 LF	75	#if CONFIG_IS_ENABLED(DM_GPIO)
	76	struct gpio_desc cs_gpio;
	77	#endif
03612861 SH	78	};
03612861 SH	79
8a4791fa QS	80	struct pl022_spi_slave {
8a4791fa QS	81	void *base;
8a4791fa	82	unsigned int freq;
8a4791fa QS	83	};
	84
	85	/*
	86	* ARM PL022 exists in different 'flavors'.
	87	* This drivers currently support the standard variant (0x00041022), that has a
	88	* 16bit wide and 8 locations deep TX/RX FIFO.
	89	*/
	90	static int pl022_is_supported(struct pl022_spi_slave *ps)
	91	{
	92	/* PL022 version is 0x00041022 */
	93	if ((readw(ps->base + SSP_PID0) == 0x22) &&
	94	(readw(ps->base + SSP_PID1) == 0x10) &&
	95	((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
	96	(readw(ps->base + SSP_PID3) == 0x00))
	97	return 1;
	98
	99	return 0;
	100	}
	101
8a4791fa QS	102	static int pl022_spi_probe(struct udevice *bus)
8a4791fa QS	103	{
c69cda25	104	struct pl022_spi_pdata *plat = dev_get_plat(bus);
8a4791fa QS	105	struct pl022_spi_slave *ps = dev_get_priv(bus);
	106
	107	ps->base = ioremap(plat->addr, plat->size);
8a4791fa	108	ps->freq = plat->freq;
8a4791fa QS	109
	110	/* Check the PL022 version */
	111	if (!pl022_is_supported(ps))
	112	return -ENOTSUPP;
	113
	114	/* 8 bits per word, high polarity and default clock rate */
	115	writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
	116	writew(DFLT_PRESCALE, ps->base + SSP_CPSR);
	117
	118	return 0;
	119	}
	120
47c32734	121	static void pl022_spi_flush(struct pl022_spi_slave *ps)
8a4791fa QS	122	{
	123	do {
	124	while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
	125	readw(ps->base + SSP_DR);
	126	} while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
	127	}
	128
	129	static int pl022_spi_claim_bus(struct udevice *dev)
	130	{
	131	struct udevice *bus = dev->parent;
	132	struct pl022_spi_slave *ps = dev_get_priv(bus);
	133	u16 reg;
	134
	135	/* Enable the SPI hardware */
	136	reg = readw(ps->base + SSP_CR1);
	137	reg \|= SSP_CR1_MASK_SSE;
	138	writew(reg, ps->base + SSP_CR1);
	139
47c32734	140	pl022_spi_flush(ps);
8a4791fa QS	141
	142	return 0;
	143	}
	144
	145	static int pl022_spi_release_bus(struct udevice *dev)
	146	{
	147	struct udevice *bus = dev->parent;
	148	struct pl022_spi_slave *ps = dev_get_priv(bus);
	149	u16 reg;
	150
47c32734	151	pl022_spi_flush(ps);
8a4791fa QS	152
	153	/* Disable the SPI hardware */
	154	reg = readw(ps->base + SSP_CR1);
	155	reg &= ~SSP_CR1_MASK_SSE;
	156	writew(reg, ps->base + SSP_CR1);
	157
	158	return 0;
	159	}
	160
47d9ae54 LF	161	static void pl022_spi_set_cs(struct udevice *dev, bool on)
	162	{
	163	#if CONFIG_IS_ENABLED(DM_GPIO)
	164	struct udevice *bus = dev->parent;
	165	struct pl022_spi_pdata *plat = dev_get_plat(bus);
	166
	167	if (dm_gpio_is_valid(&plat->cs_gpio))
	168	dm_gpio_set_value(&plat->cs_gpio, on ? 1 : 0);
	169	#endif
	170	}
	171
8a4791fa QS	172	static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
	173	const void dout, void din, unsigned long flags)
	174	{
	175	struct udevice *bus = dev->parent;
	176	struct pl022_spi_slave *ps = dev_get_priv(bus);
	177	u32 len_tx = 0, len_rx = 0, len;
	178	u32 ret = 0;
	179	const u8 *txp = dout;
	180	u8 *rxp = din, value;
	181
	182	if (bitlen == 0)
	183	/* Finish any previously submitted transfers */
47d9ae54	184	goto done;
8a4791fa QS	185
	186	/*
	187	* TODO: The controller can do non-multiple-of-8 bit
	188	* transfers, but this driver currently doesn't support it.
	189	*
	190	* It's also not clear how such transfers are supposed to be
	191	* represented as a stream of bytes...this is a limitation of
	192	* the current SPI interface.
	193	*/
	194	if (bitlen % 8) {
	195	/* Errors always terminate an ongoing transfer */
	196	flags \|= SPI_XFER_END;
47d9ae54 LF	197	ret = -1;
47d9ae54 LF	198	goto done;
8a4791fa QS	199	}
8a4791fa QS	200
47d9ae54 LF	201	if (flags & SPI_XFER_BEGIN)
	202	pl022_spi_set_cs(dev, true);
	203
8a4791fa QS	204	len = bitlen / 8;
	205
	206	while (len_tx < len) {
	207	if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
	208	value = txp ? *txp++ : 0;
	209	writew(value, ps->base + SSP_DR);
	210	len_tx++;
	211	}
	212
	213	if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
	214	value = readw(ps->base + SSP_DR);
	215	if (rxp)
	216	*rxp++ = value;
	217	len_rx++;
	218	}
	219	}
	220
	221	while (len_rx < len_tx) {
	222	if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
	223	value = readw(ps->base + SSP_DR);
	224	if (rxp)
	225	*rxp++ = value;
	226	len_rx++;
	227	}
	228	}
	229
47d9ae54 LF	230	done:
	231	if (flags & SPI_XFER_END)
	232	pl022_spi_set_cs(dev, false);
	233
8a4791fa QS	234	return ret;
	235	}
	236
	237	static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
	238	{
	239	return rate / (cpsdvsr * (1 + scr));
	240	}
	241
	242	static int pl022_spi_set_speed(struct udevice *bus, uint speed)
	243	{
	244	struct pl022_spi_slave *ps = dev_get_priv(bus);
	245	u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
	246	best_cpsr = cpsr;
	247	u32 min, max, best_freq = 0, tmp;
8a4791fa	248	u32 rate = ps->freq;
8a4791fa QS	249	bool found = false;
	250
	251	max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
	252	min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);
	253
	254	if (speed > max \|\| speed < min) {
	255	pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
	256	speed, min, max);
	257	return -EINVAL;
	258	}
	259
	260	while (cpsr <= SSP_CPSR_MAX && !found) {
	261	while (scr <= SSP_SCR_MAX) {
	262	tmp = spi_rate(rate, cpsr, scr);
	263
	264	if (abs(speed - tmp) < abs(speed - best_freq)) {
	265	best_freq = tmp;
	266	best_cpsr = cpsr;
	267	best_scr = scr;
	268
	269	if (tmp == speed) {
	270	found = true;
	271	break;
	272	}
	273	}
	274
	275	scr++;
	276	}
	277	cpsr += 2;
	278	scr = SSP_SCR_MIN;
	279	}
	280
	281	writew(best_cpsr, ps->base + SSP_CPSR);
	282	cr0 = readw(ps->base + SSP_CR0);
	283	writew(cr0 \| (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);
	284
	285	return 0;
	286	}
	287
	288	static int pl022_spi_set_mode(struct udevice *bus, uint mode)
	289	{
	290	struct pl022_spi_slave *ps = dev_get_priv(bus);
	291	u16 reg;
	292
	293	reg = readw(ps->base + SSP_CR0);
	294	reg &= ~(SSP_CR0_SPH \| SSP_CR0_SPO);
	295	if (mode & SPI_CPHA)
	296	reg \|= SSP_CR0_SPH;
	297	if (mode & SPI_CPOL)
	298	reg \|= SSP_CR0_SPO;
	299	writew(reg, ps->base + SSP_CR0);
	300
	301	return 0;
	302	}
	303
	304	static int pl022_cs_info(struct udevice *bus, uint cs,
	305	struct spi_cs_info *info)
	306	{
	307	return 0;
	308	}
	309
	310	static const struct dm_spi_ops pl022_spi_ops = {
	311	.claim_bus = pl022_spi_claim_bus,
	312	.release_bus = pl022_spi_release_bus,
313	.xfer = pl022_spi_xfer,
314	.set_speed = pl022_spi_set_speed,
315	.set_mode = pl022_spi_set_mode,
316	.cs_info = pl022_cs_info,
317	};
318
95397385	319	#if CONFIG_IS_ENABLED(OF_REAL)
d1998a9f	320	static int pl022_spi_of_to_plat(struct udevice *bus)
3deb1f73	321	{
0fd3d911	322	struct pl022_spi_pdata *plat = dev_get_plat(bus);
3deb1f73 JT	323	const void *fdt = gd->fdt_blob;
	324	int node = dev_of_offset(bus);
	325	struct clk clkdev;
	326	int ret;
	327
	328	plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);
	329
	330	ret = clk_get_by_index(bus, 0, &clkdev);
	331	if (ret)
	332	return ret;
	333
	334	plat->freq = clk_get_rate(&clkdev);
	335
47d9ae54 LF	336	#if CONFIG_IS_ENABLED(DM_GPIO)
	337	ret = gpio_request_by_name(bus, "cs-gpios", 0, &plat->cs_gpio,
	338	GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE);
	339	if (ret < 0 && ret != -ENOENT)
	340	return ret;
	341	#endif
	342
3deb1f73 JT	343	return 0;
	344	}
	345
8a4791fa	346	static const struct udevice_id pl022_spi_ids[] = {
ad77009d	347	{ .compatible = "arm,pl022" },
8a4791fa QS	348	{ }
	349	};
	350	#endif
	351
	352	U_BOOT_DRIVER(pl022_spi) = {
	353	.name = "pl022_spi",
	354	.id = UCLASS_SPI,
95397385	355	#if CONFIG_IS_ENABLED(OF_REAL)
8a4791fa	356	.of_match = pl022_spi_ids,
d1998a9f	357	.of_to_plat = pl022_spi_of_to_plat,
8a4791fa	358	#endif
3deb1f73	359	.ops = &pl022_spi_ops,
caa4daa2	360	.plat_auto = sizeof(struct pl022_spi_pdata),
41575d8e	361	.priv_auto = sizeof(struct pl022_spi_slave),
8a4791fa QS	362	.probe = pl022_spi_probe,
8a4791fa QS	363	};