[u-boot.git] / board / ti / am335x / mux.c

/*
 * mux.c
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <config.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#include "../common/board_detect.h"
#include "board.h"

static struct module_pin_mux uart0_pin_mux[] = {
	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
	{-1},
};

static struct module_pin_mux uart1_pin_mux[] = {
	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART1_RXD */
	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},		/* UART1_TXD */
	{-1},
};

static struct module_pin_mux uart2_pin_mux[] = {
	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
	{-1},
};

static struct module_pin_mux uart3_pin_mux[] = {
	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
	{-1},
};

static struct module_pin_mux uart4_pin_mux[] = {
	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
	{-1},
};

static struct module_pin_mux uart5_pin_mux[] = {
	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
	{-1},
};

static struct module_pin_mux mmc0_pin_mux[] = {
	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
	{OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* GPIO0_6 */
	{-1},
};

static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
	{-1},
};

static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
	{-1},
};

static struct module_pin_mux mmc1_pin_mux[] = {
	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_CD */
	{-1},
};

static struct module_pin_mux i2c0_pin_mux[] = {
	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
	{-1},
};

static struct module_pin_mux i2c1_pin_mux[] = {
	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
			PULLUDEN | SLEWCTRL)},	/* I2C_DATA */
	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
			PULLUDEN | SLEWCTRL)},	/* I2C_SCLK */
	{-1},
};

static struct module_pin_mux i2c2_pin_mux[] = {
	{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE |
			PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* I2C_DATA */
	{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE |
			PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* I2C_SCLK */
	{-1},
};

static struct module_pin_mux spi0_pin_mux[] = {
	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
	{-1},
};

static struct module_pin_mux gpio0_7_pin_mux[] = {
	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)},	/* GPIO0_7 */
	{-1},
};

static struct module_pin_mux gpio0_18_pin_mux[] = {
	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)},	/* GPIO0_18 */
	{-1},
};

static struct module_pin_mux rgmii1_pin_mux[] = {
	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
	{-1},
};

static struct module_pin_mux mii1_pin_mux[] = {
	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
	{-1},
};

static struct module_pin_mux rmii1_pin_mux[] = {
	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* MII1_CRS */
	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* MII1_RXERR */
	{OFFSET(mii1_txen), MODE(1)},			/* MII1_TXEN */
	{OFFSET(mii1_txd1), MODE(1)},			/* MII1_TXD1 */
	{OFFSET(mii1_txd0), MODE(1)},			/* MII1_TXD0 */
	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* MII1_RXD1 */
	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* MII1_RXD0 */
	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REFCLK */
	{-1},
};

#ifdef CONFIG_MTD_RAW_NAND
static struct module_pin_mux nand_pin_mux[] = {
	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0  */
	{OFFSET(gpmc_ad1),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1  */
	{OFFSET(gpmc_ad2),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2  */
	{OFFSET(gpmc_ad3),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3  */
	{OFFSET(gpmc_ad4),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4  */
	{OFFSET(gpmc_ad5),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5  */
	{OFFSET(gpmc_ad6),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6  */
	{OFFSET(gpmc_ad7),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7  */
#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
	{OFFSET(gpmc_ad8),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8  */
	{OFFSET(gpmc_ad9),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9  */
	{OFFSET(gpmc_ad10),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
	{OFFSET(gpmc_ad11),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
	{OFFSET(gpmc_ad12),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
	{OFFSET(gpmc_ad13),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
	{OFFSET(gpmc_ad14),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
	{OFFSET(gpmc_ad15),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
#endif
	{OFFSET(gpmc_wait0),	(MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
	{OFFSET(gpmc_wpn),	(MODE(7) | PULLUP_EN)},		   /* nWP */
	{OFFSET(gpmc_csn0),	(MODE(0) | PULLUP_EN)},		   /* nCS */
	{OFFSET(gpmc_wen),	(MODE(0) | PULLDOWN_EN)},	   /* WEN */
	{OFFSET(gpmc_oen_ren),	(MODE(0) | PULLDOWN_EN)},	   /* OE */
	{OFFSET(gpmc_advn_ale),	(MODE(0) | PULLDOWN_EN)},	   /* ADV_ALE */
	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)},	   /* BE_CLE */
	{-1},
};
#elif defined(CONFIG_NOR)
static struct module_pin_mux bone_norcape_pin_mux[] = {
	{OFFSET(gpmc_a0), MODE(0) | PULLUDDIS},			/* NOR_A0 */
	{OFFSET(gpmc_a1), MODE(0) | PULLUDDIS},			/* NOR_A1 */
	{OFFSET(gpmc_a2), MODE(0) | PULLUDDIS},			/* NOR_A2 */
	{OFFSET(gpmc_a3), MODE(0) | PULLUDDIS},			/* NOR_A3 */
	{OFFSET(gpmc_a4), MODE(0) | PULLUDDIS},			/* NOR_A4 */
	{OFFSET(gpmc_a5), MODE(0) | PULLUDDIS},			/* NOR_A5 */
	{OFFSET(gpmc_a6), MODE(0) | PULLUDDIS},			/* NOR_A6 */
	{OFFSET(gpmc_a7), MODE(0) | PULLUDDIS},			/* NOR_A7 */
	{OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD0 */
	{OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD1 */
	{OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD2 */
	{OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD3 */
	{OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD4 */
	{OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD5 */
	{OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD6 */
	{OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD7 */
	{OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD8 */
	{OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD9 */
	{OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD10 */
	{OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD11 */
	{OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD12 */
	{OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD13 */
	{OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD14 */
	{OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD15 */
	{OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN},     /* CE */
	{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
	{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
	{OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
	{OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN},    /* WEN */
	{OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
	{-1},
};
#endif

static struct module_pin_mux uart3_icev2_pin_mux[] = {
	{OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
	{OFFSET(mii1_rxd2), MODE(1) | PULLUDEN},		/* UART3_TXD */
	{-1},
};

#if defined(CONFIG_NOR_BOOT)
void enable_norboot_pin_mux(void)
{
	configure_module_pin_mux(bone_norcape_pin_mux);
}
#endif

void enable_uart0_pin_mux(void)
{
	configure_module_pin_mux(uart0_pin_mux);
}

void enable_uart1_pin_mux(void)
{
	configure_module_pin_mux(uart1_pin_mux);
}

void enable_uart2_pin_mux(void)
{
	configure_module_pin_mux(uart2_pin_mux);
}

void enable_uart3_pin_mux(void)
{
	configure_module_pin_mux(uart3_pin_mux);
}

void enable_uart4_pin_mux(void)
{
	configure_module_pin_mux(uart4_pin_mux);
}

void enable_uart5_pin_mux(void)
{
	configure_module_pin_mux(uart5_pin_mux);
}

void enable_i2c0_pin_mux(void)
{
	configure_module_pin_mux(i2c0_pin_mux);
}

void enable_i2c2_pin_mux(void)
{
	configure_module_pin_mux(i2c2_pin_mux);
}

/*
 * The AM335x GP EVM, if daughter card(s) are connected, can have 8
 * different profiles.  These profiles determine what peripherals are
 * valid and need pinmux to be configured.
 */
#define PROFILE_NONE	0x0
#define PROFILE_0	(1 << 0)
#define PROFILE_1	(1 << 1)
#define PROFILE_2	(1 << 2)
#define PROFILE_3	(1 << 3)
#define PROFILE_4	(1 << 4)
#define PROFILE_5	(1 << 5)
#define PROFILE_6	(1 << 6)
#define PROFILE_7	(1 << 7)
#define PROFILE_MASK	0x7
#define PROFILE_ALL	0xFF

/* CPLD registers */
#define I2C_CPLD_ADDR	0x35
#define CFG_REG		0x10

static unsigned short detect_daughter_board_profile(void)
{
	unsigned short val;
	struct udevice *dev = NULL;
	int rc;

	rc = i2c_get_chip_for_busnum(0, I2C_CPLD_ADDR, 1, &dev);
	if (rc)
		return PROFILE_NONE;
	rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2);
	if (rc)
		return PROFILE_NONE;
	return (1 << (val & PROFILE_MASK));
}

void enable_board_pin_mux(void)
{
	/* Do board-specific muxes. */
	if (board_is_bone()) {
		/* Beaglebone pinmux */
		configure_module_pin_mux(mii1_pin_mux);
		configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_MTD_RAW_NAND)
		configure_module_pin_mux(nand_pin_mux);
#elif defined(CONFIG_NOR)
		configure_module_pin_mux(bone_norcape_pin_mux);
#else
		configure_module_pin_mux(mmc1_pin_mux);
#endif
		configure_module_pin_mux(i2c2_pin_mux);
	} else if (board_is_gp_evm()) {
		/* General Purpose EVM */
		unsigned short profile = detect_daughter_board_profile();
		configure_module_pin_mux(rgmii1_pin_mux);
		configure_module_pin_mux(mmc0_pin_mux);
		/* In profile #2 i2c1 and spi0 conflict. */
		if (profile & ~PROFILE_2)
			configure_module_pin_mux(i2c1_pin_mux);
		/* Profiles 2 & 3 don't have NAND */
#ifdef CONFIG_MTD_RAW_NAND
		if (profile & ~(PROFILE_2 | PROFILE_3))
			configure_module_pin_mux(nand_pin_mux);
#endif
		else if (profile == PROFILE_2) {
			configure_module_pin_mux(mmc1_pin_mux);
			configure_module_pin_mux(spi0_pin_mux);
		}
	} else if (board_is_idk()) {
		/* Industrial Motor Control (IDK) */
		configure_module_pin_mux(mii1_pin_mux);
		configure_module_pin_mux(mmc0_no_cd_pin_mux);
	} else if (board_is_evm_sk()) {
		/* Starter Kit EVM */
		configure_module_pin_mux(i2c1_pin_mux);
		configure_module_pin_mux(gpio0_7_pin_mux);
		configure_module_pin_mux(rgmii1_pin_mux);
		configure_module_pin_mux(mmc0_pin_mux_sk_evm);
	} else if (board_is_bone_lt()) {
		if (board_is_bben()) {
			char subtype_id = board_ti_get_config()[1];

			/* SanCloud Beaglebone LT Enhanced pinmux */
			configure_module_pin_mux(rgmii1_pin_mux);

			if (subtype_id == 'L')
				configure_module_pin_mux(spi0_pin_mux);
		} else {
			/* Beaglebone LT pinmux */
			configure_module_pin_mux(mii1_pin_mux);
		}
		/* Beaglebone LT pinmux */
		configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_EMMC_BOOT)
		configure_module_pin_mux(nand_pin_mux);
#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
		configure_module_pin_mux(bone_norcape_pin_mux);
#else
		configure_module_pin_mux(mmc1_pin_mux);
#endif
		configure_module_pin_mux(i2c2_pin_mux);
	} else if (board_is_pb()) {
		configure_module_pin_mux(mii1_pin_mux);
		configure_module_pin_mux(mmc0_pin_mux);
	} else if (board_is_icev2()) {
		configure_module_pin_mux(mmc0_pin_mux);
		configure_module_pin_mux(gpio0_18_pin_mux);
		configure_module_pin_mux(uart3_icev2_pin_mux);
		configure_module_pin_mux(rmii1_pin_mux);
		configure_module_pin_mux(spi0_pin_mux);
	} else {
		/* Unknown board. We might still be able to boot. */
		puts("Bad EEPROM or unknown board, cannot configure pinmux.");
	}
}
Commit	Line	Data
5289e83a CN	1	/*
	2	* mux.c
	3	*
a94a4071	4	* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5289e83a CN	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
03de305e	16	#include <config.h>
db7dd810	17	#include <asm/arch/sys_proto.h>
5289e83a	18	#include <asm/arch/hardware.h>
7f26a5a2	19	#include <asm/arch/mux.h>
5289e83a	20	#include <asm/io.h>
036fd65a	21	#include <i2c.h>
770e68c0	22	#include "../common/board_detect.h"
e363426e	23	#include "board.h"
5289e83a	24
5289e83a CN	25	static struct module_pin_mux uart0_pin_mux[] = {
	26	{OFFSET(uart0_rxd), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* UART0_RXD */
	27	{OFFSET(uart0_txd), (MODE(0) \| PULLUDEN)}, /* UART0_TXD */
	28	{-1},
	29	};
	30
6422b70b AB	31	static struct module_pin_mux uart1_pin_mux[] = {
	32	{OFFSET(uart1_rxd), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* UART1_RXD */
	33	{OFFSET(uart1_txd), (MODE(0) \| PULLUDEN)}, /* UART1_TXD */
	34	{-1},
	35	};
	36
	37	static struct module_pin_mux uart2_pin_mux[] = {
	38	{OFFSET(spi0_sclk), (MODE(1) \| PULLUP_EN \| RXACTIVE)}, /* UART2_RXD */
	39	{OFFSET(spi0_d0), (MODE(1) \| PULLUDEN)}, /* UART2_TXD */
	40	{-1},
	41	};
	42
	43	static struct module_pin_mux uart3_pin_mux[] = {
	44	{OFFSET(spi0_cs1), (MODE(1) \| PULLUP_EN \| RXACTIVE)}, /* UART3_RXD */
	45	{OFFSET(ecap0_in_pwm0_out), (MODE(1) \| PULLUDEN)}, /* UART3_TXD */
	46	{-1},
	47	};
	48
	49	static struct module_pin_mux uart4_pin_mux[] = {
	50	{OFFSET(gpmc_wait0), (MODE(6) \| PULLUP_EN \| RXACTIVE)}, /* UART4_RXD */
	51	{OFFSET(gpmc_wpn), (MODE(6) \| PULLUDEN)}, /* UART4_TXD */
	52	{-1},
	53	};
	54
	55	static struct module_pin_mux uart5_pin_mux[] = {
	56	{OFFSET(lcd_data9), (MODE(4) \| PULLUP_EN \| RXACTIVE)}, /* UART5_RXD */
	57	{OFFSET(lcd_data8), (MODE(4) \| PULLUDEN)}, /* UART5_TXD */
	58	{-1},
	59	};
	60
876bdd6d CN	61	static struct module_pin_mux mmc0_pin_mux[] = {
	62	{OFFSET(mmc0_dat3), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT3 */
	63	{OFFSET(mmc0_dat2), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT2 */
	64	{OFFSET(mmc0_dat1), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT1 */
	65	{OFFSET(mmc0_dat0), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT0 */
	66	{OFFSET(mmc0_clk), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_CLK */
	67	{OFFSET(mmc0_cmd), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_CMD */
	68	{OFFSET(mcasp0_aclkr), (MODE(4) \| RXACTIVE)}, /* MMC0_WP */
9f13b6d1	69	{OFFSET(spi0_cs1), (MODE(7) \| RXACTIVE \| PULLUP_EN)}, /* GPIO0_6 */
876bdd6d CN	70	{-1},
876bdd6d CN	71	};
db7dd810	72
a956bdcb MF	73	static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
	74	{OFFSET(mmc0_dat3), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT3 */
	75	{OFFSET(mmc0_dat2), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT2 */
	76	{OFFSET(mmc0_dat1), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT1 */
	77	{OFFSET(mmc0_dat0), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT0 */
	78	{OFFSET(mmc0_clk), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_CLK */
	79	{OFFSET(mmc0_cmd), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_CMD */
	80	{OFFSET(mcasp0_aclkr), (MODE(4) \| RXACTIVE)}, /* MMC0_WP */
	81	{-1},
	82	};
	83
db7dd810 TR	84	static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
	85	{OFFSET(mmc0_dat3), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT3 */
	86	{OFFSET(mmc0_dat2), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT2 */
	87	{OFFSET(mmc0_dat1), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT1 */
	88	{OFFSET(mmc0_dat0), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT0 */
	89	{OFFSET(mmc0_clk), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_CLK */
	90	{OFFSET(mmc0_cmd), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_CMD */
	91	{OFFSET(spi0_cs1), (MODE(5) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_CD */
	92	{-1},
	93	};
876bdd6d	94
6bfca503	95	static struct module_pin_mux mmc1_pin_mux[] = {
c5646270 JJH	96	{OFFSET(gpmc_ad7), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT7 */
	97	{OFFSET(gpmc_ad6), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT6 */
	98	{OFFSET(gpmc_ad5), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT5 */
	99	{OFFSET(gpmc_ad4), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT4 */
6bfca503 TR	100	{OFFSET(gpmc_ad3), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT3 */
	101	{OFFSET(gpmc_ad2), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT2 */
	102	{OFFSET(gpmc_ad1), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT1 */
	103	{OFFSET(gpmc_ad0), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT0 */
	104	{OFFSET(gpmc_csn1), (MODE(2) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_CLK */
	105	{OFFSET(gpmc_csn2), (MODE(2) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_CMD */
	106	{OFFSET(gpmc_csn0), (MODE(7) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_WP */
	107	{OFFSET(gpmc_advn_ale), (MODE(7) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_CD */
	108	{-1},
	109	};
	110
b4116ede PR	111	static struct module_pin_mux i2c0_pin_mux[] = {
	112	{OFFSET(i2c0_sda), (MODE(0) \| RXACTIVE \|
	113	PULLUDEN \| SLEWCTRL)}, /* I2C_DATA */
	114	{OFFSET(i2c0_scl), (MODE(0) \| RXACTIVE \|
	115	PULLUDEN \| SLEWCTRL)}, /* I2C_SCLK */
	116	{-1},
	117	};
	118
d3decdeb SS	119	static struct module_pin_mux i2c1_pin_mux[] = {
	120	{OFFSET(spi0_d1), (MODE(2) \| RXACTIVE \|
	121	PULLUDEN \| SLEWCTRL)}, /* I2C_DATA */
	122	{OFFSET(spi0_cs0), (MODE(2) \| RXACTIVE \|
	123	PULLUDEN \| SLEWCTRL)}, /* I2C_SCLK */
	124	{-1},
	125	};
	126
d705527a KM	127	static struct module_pin_mux i2c2_pin_mux[] = {
	128	{OFFSET(uart1_ctsn), (MODE(3) \| RXACTIVE \|
	129	PULLUDEN \| PULLUP_EN \| SLEWCTRL)}, /* I2C_DATA */
	130	{OFFSET(uart1_rtsn), (MODE(3) \| RXACTIVE \|
	131	PULLUDEN \| PULLUP_EN \| SLEWCTRL)}, /* I2C_SCLK */
	132	{-1},
	133	};
	134
a4a99fff TR	135	static struct module_pin_mux spi0_pin_mux[] = {
	136	{OFFSET(spi0_sclk), (MODE(0) \| RXACTIVE \| PULLUDEN)}, /* SPI0_SCLK */
	137	{OFFSET(spi0_d0), (MODE(0) \| RXACTIVE \|
	138	PULLUDEN \| PULLUP_EN)}, /* SPI0_D0 */
	139	{OFFSET(spi0_d1), (MODE(0) \| RXACTIVE \| PULLUDEN)}, /* SPI0_D1 */
	140	{OFFSET(spi0_cs0), (MODE(0) \| RXACTIVE \|
	141	PULLUDEN \| PULLUP_EN)}, /* SPI0_CS0 */
	142	{-1},
	143	};
	144
65d750be TR	145	static struct module_pin_mux gpio0_7_pin_mux[] = {
	146	{OFFSET(ecap0_in_pwm0_out), (MODE(7) \| PULLUDEN)}, /* GPIO0_7 */
	147	{-1},
	148	};
	149
866b178b LV	150	static struct module_pin_mux gpio0_18_pin_mux[] = {
	151	{OFFSET(usb0_drvvbus), (MODE(7) \| PULLUDEN)}, /* GPIO0_18 */
	152	{-1},
	153	};
	154
89017e15 CN	155	static struct module_pin_mux rgmii1_pin_mux[] = {
	156	{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
	157	{OFFSET(mii1_rxdv), MODE(2) \| RXACTIVE}, /* RGMII1_RCTL */
	158	{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
	159	{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
	160	{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
	161	{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
	162	{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
	163	{OFFSET(mii1_rxclk), MODE(2) \| RXACTIVE}, /* RGMII1_RCLK */
	164	{OFFSET(mii1_rxd3), MODE(2) \| RXACTIVE}, /* RGMII1_RD3 */
	165	{OFFSET(mii1_rxd2), MODE(2) \| RXACTIVE}, /* RGMII1_RD2 */
	166	{OFFSET(mii1_rxd1), MODE(2) \| RXACTIVE}, /* RGMII1_RD1 */
	167	{OFFSET(mii1_rxd0), MODE(2) \| RXACTIVE}, /* RGMII1_RD0 */
	168	{OFFSET(mdio_data), MODE(0) \| RXACTIVE \| PULLUP_EN},/* MDIO_DATA */
	169	{OFFSET(mdio_clk), MODE(0) \| PULLUP_EN}, /* MDIO_CLK */
	170	{-1},
	171	};
	172
	173	static struct module_pin_mux mii1_pin_mux[] = {
	174	{OFFSET(mii1_rxerr), MODE(0) \| RXACTIVE}, /* MII1_RXERR */
	175	{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
	176	{OFFSET(mii1_rxdv), MODE(0) \| RXACTIVE}, /* MII1_RXDV */
	177	{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
	178	{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
	179	{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
	180	{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
	181	{OFFSET(mii1_txclk), MODE(0) \| RXACTIVE}, /* MII1_TXCLK */
	182	{OFFSET(mii1_rxclk), MODE(0) \| RXACTIVE}, /* MII1_RXCLK */
	183	{OFFSET(mii1_rxd3), MODE(0) \| RXACTIVE}, /* MII1_RXD3 */
	184	{OFFSET(mii1_rxd2), MODE(0) \| RXACTIVE}, /* MII1_RXD2 */
	185	{OFFSET(mii1_rxd1), MODE(0) \| RXACTIVE}, /* MII1_RXD1 */
	186	{OFFSET(mii1_rxd0), MODE(0) \| RXACTIVE}, /* MII1_RXD0 */
	187	{OFFSET(mdio_data), MODE(0) \| RXACTIVE \| PULLUP_EN}, /* MDIO_DATA */
	188	{OFFSET(mdio_clk), MODE(0) \| PULLUP_EN}, /* MDIO_CLK */
	189	{-1},
	190	};
	191
866b178b LV	192	static struct module_pin_mux rmii1_pin_mux[] = {
	193	{OFFSET(mdio_clk), MODE(0) \| PULLUP_EN}, /* MDIO_CLK */
	194	{OFFSET(mdio_data), MODE(0) \| RXACTIVE \| PULLUP_EN}, /* MDIO_DATA */
	195	{OFFSET(mii1_crs), MODE(1) \| RXACTIVE}, /* MII1_CRS */
	196	{OFFSET(mii1_rxerr), MODE(1) \| RXACTIVE}, /* MII1_RXERR */
	197	{OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */
	198	{OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */
	199	{OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */
	200	{OFFSET(mii1_rxd1), MODE(1) \| RXACTIVE}, /* MII1_RXD1 */
	201	{OFFSET(mii1_rxd0), MODE(1) \| RXACTIVE}, /* MII1_RXD0 */
	202	{OFFSET(rmii1_refclk), MODE(0) \| RXACTIVE}, /* RMII1_REFCLK */
	203	{-1},
	204	};
	205
88718be3	206	#ifdef CONFIG_MTD_RAW_NAND
70fb65b0	207	static struct module_pin_mux nand_pin_mux[] = {
85eb0de2	208	{OFFSET(gpmc_ad0), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD0 */
	209	{OFFSET(gpmc_ad1), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD1 */
	210	{OFFSET(gpmc_ad2), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD2 */
	211	{OFFSET(gpmc_ad3), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD3 */
	212	{OFFSET(gpmc_ad4), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD4 */
	213	{OFFSET(gpmc_ad5), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD5 */
	214	{OFFSET(gpmc_ad6), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD6 */
	215	{OFFSET(gpmc_ad7), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD7 */
	216	#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
	217	{OFFSET(gpmc_ad8), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD8 */
	218	{OFFSET(gpmc_ad9), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD9 */
	219	{OFFSET(gpmc_ad10), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD10 */
	220	{OFFSET(gpmc_ad11), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD11 */
	221	{OFFSET(gpmc_ad12), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD12 */
	222	{OFFSET(gpmc_ad13), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD13 */
	223	{OFFSET(gpmc_ad14), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD14 */
	224	{OFFSET(gpmc_ad15), (MODE(0) \| PULLUDDIS \| RXACTIVE)}, /* AD15 */
	225	#endif
	226	{OFFSET(gpmc_wait0), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* nWAIT */
	227	{OFFSET(gpmc_wpn), (MODE(7) \| PULLUP_EN)}, /* nWP */
	228	{OFFSET(gpmc_csn0), (MODE(0) \| PULLUP_EN)}, /* nCS */
	229	{OFFSET(gpmc_wen), (MODE(0) \| PULLDOWN_EN)}, /* WEN */
	230	{OFFSET(gpmc_oen_ren), (MODE(0) \| PULLDOWN_EN)}, /* OE */
	231	{OFFSET(gpmc_advn_ale), (MODE(0) \| PULLDOWN_EN)}, /* ADV_ALE */
	232	{OFFSET(gpmc_be0n_cle), (MODE(0) \| PULLDOWN_EN)}, /* BE_CLE */
70fb65b0 IY	233	{-1},
70fb65b0 IY	234	};
3df3bc1e	235	#elif defined(CONFIG_NOR)
cd8845d7	236	static struct module_pin_mux bone_norcape_pin_mux[] = {
3df3bc1e	237	{OFFSET(gpmc_a0), MODE(0) \| PULLUDDIS}, /* NOR_A0 */
	238	{OFFSET(gpmc_a1), MODE(0) \| PULLUDDIS}, /* NOR_A1 */
	239	{OFFSET(gpmc_a2), MODE(0) \| PULLUDDIS}, /* NOR_A2 */
	240	{OFFSET(gpmc_a3), MODE(0) \| PULLUDDIS}, /* NOR_A3 */
	241	{OFFSET(gpmc_a4), MODE(0) \| PULLUDDIS}, /* NOR_A4 */
	242	{OFFSET(gpmc_a5), MODE(0) \| PULLUDDIS}, /* NOR_A5 */
	243	{OFFSET(gpmc_a6), MODE(0) \| PULLUDDIS}, /* NOR_A6 */
	244	{OFFSET(gpmc_a7), MODE(0) \| PULLUDDIS}, /* NOR_A7 */
	245	{OFFSET(gpmc_ad0), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD0 */
	246	{OFFSET(gpmc_ad1), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD1 */
	247	{OFFSET(gpmc_ad2), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD2 */
	248	{OFFSET(gpmc_ad3), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD3 */
	249	{OFFSET(gpmc_ad4), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD4 */
	250	{OFFSET(gpmc_ad5), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD5 */
	251	{OFFSET(gpmc_ad6), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD6 */
	252	{OFFSET(gpmc_ad7), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD7 */
	253	{OFFSET(gpmc_ad8), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD8 */
	254	{OFFSET(gpmc_ad9), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD9 */
	255	{OFFSET(gpmc_ad10), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD10 */
	256	{OFFSET(gpmc_ad11), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD11 */
	257	{OFFSET(gpmc_ad12), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD12 */
	258	{OFFSET(gpmc_ad13), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD13 */
	259	{OFFSET(gpmc_ad14), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD14 */
	260	{OFFSET(gpmc_ad15), MODE(0) \| PULLUDDIS \| RXACTIVE}, /* NOR_AD15 */
	261	{OFFSET(gpmc_csn0), MODE(0) \| PULLUDEN \| PULLUP_EN}, /* CE */
	262	{OFFSET(gpmc_advn_ale), MODE(0) \| PULLUDEN \| PULLDOWN_EN}, /* ALE */
	263	{OFFSET(gpmc_oen_ren), MODE(0) \| PULLUDEN \| PULLDOWN_EN},/* OEn_REN */
	264	{OFFSET(gpmc_be0n_cle), MODE(0) \| PULLUDEN \| PULLDOWN_EN},/* unused */
	265	{OFFSET(gpmc_wen), MODE(0) \| PULLUDEN \| PULLDOWN_EN}, /* WEN */
	266	{OFFSET(gpmc_wait0), MODE(0) \| PULLUDEN \| PULLUP_EN \| RXACTIVE},/WAIT/
cd8845d7 SK	267	{-1},
	268	};
	269	#endif
	270
866b178b LV	271	static struct module_pin_mux uart3_icev2_pin_mux[] = {
	272	{OFFSET(mii1_rxd3), (MODE(1) \| PULLUP_EN \| RXACTIVE)}, /* UART3_RXD */
	273	{OFFSET(mii1_rxd2), MODE(1) \| PULLUDEN}, /* UART3_TXD */
	274	{-1},
	275	};
	276
0660481a	277	#if defined(CONFIG_NOR_BOOT)
0660481a HS	278	void enable_norboot_pin_mux(void)
0660481a HS	279	{
3df3bc1e	280	configure_module_pin_mux(bone_norcape_pin_mux);
0660481a HS	281	}
0660481a HS	282	#endif
cd8845d7	283
5289e83a CN	284	void enable_uart0_pin_mux(void)
	285	{
	286	configure_module_pin_mux(uart0_pin_mux);
	287	}
876bdd6d	288
6422b70b AB	289	void enable_uart1_pin_mux(void)
	290	{
	291	configure_module_pin_mux(uart1_pin_mux);
	292	}
	293
	294	void enable_uart2_pin_mux(void)
	295	{
	296	configure_module_pin_mux(uart2_pin_mux);
	297	}
	298
	299	void enable_uart3_pin_mux(void)
	300	{
	301	configure_module_pin_mux(uart3_pin_mux);
	302	}
	303
	304	void enable_uart4_pin_mux(void)
	305	{
	306	configure_module_pin_mux(uart4_pin_mux);
	307	}
	308
	309	void enable_uart5_pin_mux(void)
	310	{
	311	configure_module_pin_mux(uart5_pin_mux);
	312	}
b4116ede PR	313
	314	void enable_i2c0_pin_mux(void)
	315	{
	316	configure_module_pin_mux(i2c0_pin_mux);
	317	}
d3decdeb	318
d705527a KM	319	void enable_i2c2_pin_mux(void)
	320	{
	321	configure_module_pin_mux(i2c2_pin_mux);
	322	}
	323
036fd65a TR	324	/*
	325	* The AM335x GP EVM, if daughter card(s) are connected, can have 8
	326	* different profiles. These profiles determine what peripherals are
	327	* valid and need pinmux to be configured.
	328	*/
	329	#define PROFILE_NONE 0x0
	330	#define PROFILE_0 (1 << 0)
	331	#define PROFILE_1 (1 << 1)
	332	#define PROFILE_2 (1 << 2)
	333	#define PROFILE_3 (1 << 3)
	334	#define PROFILE_4 (1 << 4)
	335	#define PROFILE_5 (1 << 5)
	336	#define PROFILE_6 (1 << 6)
	337	#define PROFILE_7 (1 << 7)
	338	#define PROFILE_MASK 0x7
	339	#define PROFILE_ALL 0xFF
	340
	341	/* CPLD registers */
	342	#define I2C_CPLD_ADDR 0x35
	343	#define CFG_REG 0x10
	344
	345	static unsigned short detect_daughter_board_profile(void)
d3decdeb	346	{
036fd65a	347	unsigned short val;
1514244c JJH	348	struct udevice *dev = NULL;
1514244c JJH	349	int rc;
036fd65a	350
1514244c JJH	351	rc = i2c_get_chip_for_busnum(0, I2C_CPLD_ADDR, 1, &dev);
	352	if (rc)
	353	return PROFILE_NONE;
	354	rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2);
	355	if (rc)
	356	return PROFILE_NONE;
036fd65a TR	357	return (1 << (val & PROFILE_MASK));
	358	}
	359
770e68c0	360	void enable_board_pin_mux(void)
036fd65a TR	361	{
036fd65a TR	362	/* Do board-specific muxes. */
770e68c0	363	if (board_is_bone()) {
db7dd810 TR	364	/* Beaglebone pinmux */
	365	configure_module_pin_mux(mii1_pin_mux);
	366	configure_module_pin_mux(mmc0_pin_mux);
88718be3	367	#if defined(CONFIG_MTD_RAW_NAND)
85eb0de2	368	configure_module_pin_mux(nand_pin_mux);
3df3bc1e	369	#elif defined(CONFIG_NOR)
cd8845d7	370	configure_module_pin_mux(bone_norcape_pin_mux);
85eb0de2	371	#else
85eb0de2	372	configure_module_pin_mux(mmc1_pin_mux);
cd8845d7	373	#endif
d705527a	374	configure_module_pin_mux(i2c2_pin_mux);
770e68c0	375	} else if (board_is_gp_evm()) {
db7dd810	376	/* General Purpose EVM */
036fd65a	377	unsigned short profile = detect_daughter_board_profile();
db7dd810 TR	378	configure_module_pin_mux(rgmii1_pin_mux);
db7dd810 TR	379	configure_module_pin_mux(mmc0_pin_mux);
036fd65a TR	380	/* In profile #2 i2c1 and spi0 conflict. */
	381	if (profile & ~PROFILE_2)
	382	configure_module_pin_mux(i2c1_pin_mux);
70fb65b0	383	/* Profiles 2 & 3 don't have NAND */
88718be3	384	#ifdef CONFIG_MTD_RAW_NAND
70fb65b0 IY	385	if (profile & ~(PROFILE_2 \| PROFILE_3))
70fb65b0 IY	386	configure_module_pin_mux(nand_pin_mux);
85eb0de2	387	#endif
6bfca503 TR	388	else if (profile == PROFILE_2) {
6bfca503 TR	389	configure_module_pin_mux(mmc1_pin_mux);
a4a99fff	390	configure_module_pin_mux(spi0_pin_mux);
6bfca503	391	}
770e68c0	392	} else if (board_is_idk()) {
1286b7f6	393	/* Industrial Motor Control (IDK) */
a956bdcb MF	394	configure_module_pin_mux(mii1_pin_mux);
a956bdcb MF	395	configure_module_pin_mux(mmc0_no_cd_pin_mux);
770e68c0	396	} else if (board_is_evm_sk()) {
db7dd810	397	/* Starter Kit EVM */
036fd65a	398	configure_module_pin_mux(i2c1_pin_mux);
db7dd810 TR	399	configure_module_pin_mux(gpio0_7_pin_mux);
	400	configure_module_pin_mux(rgmii1_pin_mux);
	401	configure_module_pin_mux(mmc0_pin_mux_sk_evm);
770e68c0	402	} else if (board_is_bone_lt()) {
ad6054f1	403	if (board_is_bben()) {
21acb843 PB	404	char subtype_id = board_ti_get_config()[1];
21acb843 PB	405
ad6054f1 KK	406	/* SanCloud Beaglebone LT Enhanced pinmux */
ad6054f1 KK	407	configure_module_pin_mux(rgmii1_pin_mux);
21acb843 PB	408
	409	if (subtype_id == 'L')
	410	configure_module_pin_mux(spi0_pin_mux);
ad6054f1 KK	411	} else {
	412	/* Beaglebone LT pinmux */
	413	configure_module_pin_mux(mii1_pin_mux);
	414	}
9cd7b4cd	415	/* Beaglebone LT pinmux */
9cd7b4cd	416	configure_module_pin_mux(mmc0_pin_mux);
88718be3	417	#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_EMMC_BOOT)
85eb0de2	418	configure_module_pin_mux(nand_pin_mux);
b6ab5504	419	#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
3df3bc1e	420	configure_module_pin_mux(bone_norcape_pin_mux);
85eb0de2	421	#else
9cd7b4cd	422	configure_module_pin_mux(mmc1_pin_mux);
85eb0de2	423	#endif
d705527a	424	configure_module_pin_mux(i2c2_pin_mux);
eff0c977 JK	425	} else if (board_is_pb()) {
	426	configure_module_pin_mux(mii1_pin_mux);
	427	configure_module_pin_mux(mmc0_pin_mux);
866b178b LV	428	} else if (board_is_icev2()) {
	429	configure_module_pin_mux(mmc0_pin_mux);
	430	configure_module_pin_mux(gpio0_18_pin_mux);
	431	configure_module_pin_mux(uart3_icev2_pin_mux);
	432	configure_module_pin_mux(rmii1_pin_mux);
	433	configure_module_pin_mux(spi0_pin_mux);
db7dd810	434	} else {
c19a28bc A	435	/* Unknown board. We might still be able to boot. */
c19a28bc A	436	puts("Bad EEPROM or unknown board, cannot configure pinmux.");
db7dd810	437	}
65d750be	438	}