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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
affae2bf WD |
2 | /* |
3 | * (C) Copyright 2002 | |
4 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
affae2bf WD |
5 | */ |
6 | ||
1eb69ae4 | 7 | #include <cpu_func.h> |
9b94ac61 | 8 | #include <asm/cache.h> |
138105ef | 9 | #include <watchdog.h> |
0db5bca8 | 10 | |
729c1fe6 RV |
11 | static ulong maybe_watchdog_reset(ulong flushed) |
12 | { | |
13 | flushed += CONFIG_SYS_CACHELINE_SIZE; | |
14 | if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) { | |
29caf930 | 15 | schedule(); |
729c1fe6 RV |
16 | flushed = 0; |
17 | } | |
18 | return flushed; | |
19 | } | |
20 | ||
e39cd81c | 21 | void flush_cache(ulong start_addr, ulong size) |
affae2bf | 22 | { |
e39cd81c | 23 | ulong addr, start, end; |
729c1fe6 | 24 | ulong flushed = 0; |
affae2bf | 25 | |
e39cd81c DL |
26 | start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); |
27 | end = start_addr + size - 1; | |
affae2bf | 28 | |
bced7cce KG |
29 | for (addr = start; (addr <= end) && (addr >= start); |
30 | addr += CONFIG_SYS_CACHELINE_SIZE) { | |
e39cd81c | 31 | asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); |
729c1fe6 | 32 | flushed = maybe_watchdog_reset(flushed); |
affae2bf | 33 | } |
e39cd81c DL |
34 | /* wait for all dcbst to complete on bus */ |
35 | asm volatile("sync" : : : "memory"); | |
36 | ||
bced7cce KG |
37 | for (addr = start; (addr <= end) && (addr >= start); |
38 | addr += CONFIG_SYS_CACHELINE_SIZE) { | |
e39cd81c | 39 | asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); |
729c1fe6 | 40 | flushed = maybe_watchdog_reset(flushed); |
e39cd81c DL |
41 | } |
42 | asm volatile("sync" : : : "memory"); | |
43 | /* flush prefetch queue */ | |
44 | asm volatile("isync" : : : "memory"); | |
affae2bf | 45 | } |