[u-boot.git] / cmd / pci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <[email protected]>
 *
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 * Wolfgang Grandegger, DENX Software Engineering, [email protected].
 */

/*
 * PCI routines
 */

#include <common.h>
#include <bootretry.h>
#include <cli.h>
#include <command.h>
#include <console.h>
#include <dm.h>
#include <init.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

struct pci_reg_info {
	const char *name;
	enum pci_size_t size;
	u8 offset;
};

static int pci_byte_size(enum pci_size_t size)
{
	switch (size) {
	case PCI_SIZE_8:
		return 1;
	case PCI_SIZE_16:
		return 2;
	case PCI_SIZE_32:
	default:
		return 4;
	}
}

static int pci_field_width(enum pci_size_t size)
{
	return pci_byte_size(size) * 2;
}

static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
{
	for (; regs->name; regs++) {
		unsigned long val;

		dm_pci_read_config(dev, regs->offset, &val, regs->size);
		printf("  %s =%*s%#.*lx\n", regs->name,
		       (int)(28 - strlen(regs->name)), "",
		       pci_field_width(regs->size), val);
	}
}

static int pci_bar_show(struct udevice *dev)
{
	u8 header_type;
	int bar_cnt, bar_id, mem_type;
	bool is_64, is_io;
	u32 base_low, base_high;
	u32 size_low, size_high;
	u64 base, size;
	u32 reg_addr;
	int prefetchable;

	dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);

	if (header_type == PCI_HEADER_TYPE_CARDBUS) {
		printf("CardBus doesn't support BARs\n");
		return -ENOSYS;
	}

	bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;

	printf("ID   Base                Size                Width  Type\n");
	printf("----------------------------------------------------------\n");

	bar_id = 0;
	reg_addr = PCI_BASE_ADDRESS_0;
	while (bar_cnt) {
		dm_pci_read_config32(dev, reg_addr, &base_low);
		dm_pci_write_config32(dev, reg_addr, 0xffffffff);
		dm_pci_read_config32(dev, reg_addr, &size_low);
		dm_pci_write_config32(dev, reg_addr, base_low);
		reg_addr += 4;

		base = base_low & ~0xf;
		size = size_low & ~0xf;
		base_high = 0x0;
		size_high = 0xffffffff;
		is_64 = 0;
		prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
		is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
		mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;

		if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
			dm_pci_read_config32(dev, reg_addr, &base_high);
			dm_pci_write_config32(dev, reg_addr, 0xffffffff);
			dm_pci_read_config32(dev, reg_addr, &size_high);
			dm_pci_write_config32(dev, reg_addr, base_high);
			bar_cnt--;
			reg_addr += 4;
			is_64 = 1;
		}

		base = base | ((u64)base_high << 32);
		size = size | ((u64)size_high << 32);

		if ((!is_64 && size_low) || (is_64 && size)) {
			size = ~size + 1;
			printf(" %d   %#018llx  %#018llx  %d     %s   %s\n",
			       bar_id, (unsigned long long)base,
			       (unsigned long long)size, is_64 ? 64 : 32,
			       is_io ? "I/O" : "MEM",
			       prefetchable ? "Prefetchable" : "");
		}

		bar_id++;
		bar_cnt--;
	}

	return 0;
}

static struct pci_reg_info regs_start[] = {
	{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
	{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
	{ "command register ID", PCI_SIZE_16, PCI_COMMAND },
	{ "status register", PCI_SIZE_16, PCI_STATUS },
	{ "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
	{},
};

static struct pci_reg_info regs_rest[] = {
	{ "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
	{ "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
	{ "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
	{ "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
	{ "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
	{ "BIST", PCI_SIZE_8, PCI_BIST },
	{ "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
	{},
};

static struct pci_reg_info regs_normal[] = {
	{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
	{ "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
	{ "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
	{ "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
	{ "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
	{ "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
	{ "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
	{ "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
	{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
	{ "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
	{ "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
	{},
};

static struct pci_reg_info regs_bridge[] = {
	{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
	{ "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
	{ "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
	{ "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
	{ "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
	{ "IO base", PCI_SIZE_8, PCI_IO_BASE },
	{ "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
	{ "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
	{ "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
	{ "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
	{ "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
	{ "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
	{ "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
	{ "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
	{ "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
	{ "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
	{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
	{ "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
	{},
};

static struct pci_reg_info regs_cardbus[] = {
	{ "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
	{ "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
	{ "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
	{ "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
	{ "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
	{ "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
	{ "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
	{ "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
	{ "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
	{ "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
	{ "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
	{ "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
	{ "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
	{ "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
	{ "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
	{ "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
	{ "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
	{ "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
	{ "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
	{ "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
	{ "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
	{ "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
	{},
};

/**
 * pci_header_show() - Show the header of the specified PCI device.
 *
 * @dev: Bus+Device+Function number
 */
static void pci_header_show(struct udevice *dev)
{
	unsigned long class, header_type;

	dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
	dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
	pci_show_regs(dev, regs_start);
	printf("  class code =                  0x%.2x (%s)\n", (int)class,
	       pci_class_str(class));
	pci_show_regs(dev, regs_rest);

	switch (header_type & 0x03) {
	case PCI_HEADER_TYPE_NORMAL:	/* "normal" PCI device */
		pci_show_regs(dev, regs_normal);
		break;
	case PCI_HEADER_TYPE_BRIDGE:	/* PCI-to-PCI bridge */
		pci_show_regs(dev, regs_bridge);
		break;
	case PCI_HEADER_TYPE_CARDBUS:	/* PCI-to-CardBus bridge */
		pci_show_regs(dev, regs_cardbus);
		break;

	default:
		printf("unknown header\n");
		break;
    }
}

static void pciinfo_header(int busnum, bool short_listing)
{
	printf("Scanning PCI devices on bus %d\n", busnum);

	if (short_listing) {
		printf("BusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n");
		printf("_____________________________________________________________\n");
	}
}

/**
 * pci_header_show_brief() - Show the short-form PCI device header
 *
 * Reads and prints the header of the specified PCI device in short form.
 *
 * @dev: PCI device to show
 */
static void pci_header_show_brief(struct udevice *dev)
{
	ulong vendor, device;
	ulong class, subclass;

	dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
	dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
	dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
	dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);

	printf("0x%.4lx     0x%.4lx     %-23s 0x%.2lx\n",
	       vendor, device,
	       pci_class_str(class), subclass);
}

static void pciinfo(struct udevice *bus, bool short_listing)
{
	struct udevice *dev;

	pciinfo_header(dev_seq(bus), short_listing);

	for (device_find_first_child(bus, &dev);
	     dev;
	     device_find_next_child(&dev)) {
		struct pci_child_plat *pplat;

		pplat = dev_get_parent_plat(dev);
		if (short_listing) {
			printf("%02x.%02x.%02x   ", dev_seq(bus),
			       PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
			pci_header_show_brief(dev);
		} else {
			printf("\nFound PCI device %02x.%02x.%02x:\n",
			       dev_seq(bus),
			       PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
			pci_header_show(dev);
		}
	}
}

/**
 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
 *
 * @name: Device string in the form "bus.device.function" where each is in hex
 * @return encoded pci_dev_t or -1 if the string was invalid
 */
static pci_dev_t get_pci_dev(char *name)
{
	char cnum[12];
	int len, i, iold, n;
	int bdfs[3] = {0,0,0};

	len = strlen(name);
	if (len > 8)
		return -1;
	for (i = 0, iold = 0, n = 0; i < len; i++) {
		if (name[i] == '.') {
			memcpy(cnum, &name[iold], i - iold);
			cnum[i - iold] = '\0';
			bdfs[n++] = hextoul(cnum, NULL);
			iold = i + 1;
		}
	}
	strcpy(cnum, &name[iold]);
	if (n == 0)
		n = 1;
	bdfs[n] = hextoul(cnum, NULL);

	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
}

static int pci_cfg_display(struct udevice *dev, ulong addr,
			   enum pci_size_t size, ulong length)
{
#define DISP_LINE_LEN	16
	ulong i, nbytes, linebytes;
	int byte_size;
	int rc = 0;

	byte_size = pci_byte_size(size);
	if (length == 0)
		length = 0x40 / byte_size; /* Standard PCI config space */

	/* Print the lines.
	 * once, and all accesses are with the specified bus width.
	 */
	nbytes = length * byte_size;
	do {
		printf("%08lx:", addr);
		linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
		for (i = 0; i < linebytes; i += byte_size) {
			unsigned long val;

			dm_pci_read_config(dev, addr, &val, size);
			printf(" %0*lx", pci_field_width(size), val);
			addr += byte_size;
		}
		printf("\n");
		nbytes -= linebytes;
		if (ctrlc()) {
			rc = 1;
			break;
		}
	} while (nbytes > 0);

	return (rc);
}

static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
			  ulong value, int incrflag)
{
	ulong	i;
	int	nbytes;
	ulong val;

	/* Print the address, followed by value.  Then accept input for
	 * the next value.  A non-converted value exits.
	 */
	do {
		printf("%08lx:", addr);
		dm_pci_read_config(dev, addr, &val, size);
		printf(" %0*lx", pci_field_width(size), val);

		nbytes = cli_readline(" ? ");
		if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
			/* <CR> pressed as only input, don't modify current
			 * location and move to next. "-" pressed will go back.
			 */
			if (incrflag)
				addr += nbytes ? -size : size;
			nbytes = 1;
			/* good enough to not time out */
			bootretry_reset_cmd_timeout();
		}
#ifdef CONFIG_BOOT_RETRY_TIME
		else if (nbytes == -2) {
			break;	/* timed out, exit the command	*/
		}
#endif
		else {
			char *endp;
			i = hextoul(console_buffer, &endp);
			nbytes = endp - console_buffer;
			if (nbytes) {
				/* good enough to not time out
				 */
				bootretry_reset_cmd_timeout();
				dm_pci_write_config(dev, addr, i, size);
				if (incrflag)
					addr += size;
			}
		}
	} while (nbytes);

	return 0;
}

static const struct pci_flag_info {
	uint flag;
	const char *name;
} pci_flag_info[] = {
	{ PCI_REGION_IO, "io" },
	{ PCI_REGION_PREFETCH, "prefetch" },
	{ PCI_REGION_SYS_MEMORY, "sysmem" },
	{ PCI_REGION_RO, "readonly" },
	{ PCI_REGION_IO, "io" },
};

static void pci_show_regions(struct udevice *bus)
{
	struct pci_controller *hose = dev_get_uclass_priv(bus);
	const struct pci_region *reg;
	int i, j;

	if (!hose) {
		printf("Bus '%s' is not a PCI controller\n", bus->name);
		return;
	}

	printf("#   %-18s %-18s %-18s  %s\n", "Bus start", "Phys start", "Size",
	       "Flags");
	for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
		printf("%d   %#018llx %#018llx %#018llx  ", i,
		       (unsigned long long)reg->bus_start,
		       (unsigned long long)reg->phys_start,
		       (unsigned long long)reg->size);
		if (!(reg->flags & PCI_REGION_TYPE))
			printf("mem ");
		for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
			if (reg->flags & pci_flag_info[j].flag)
				printf("%s ", pci_flag_info[j].name);
		}
		printf("\n");
	}
}

/* PCI Configuration Space access commands
 *
 * Syntax:
 *	pci display[.b, .w, .l] bus.device.function} [addr] [len]
 *	pci next[.b, .w, .l] bus.device.function [addr]
 *      pci modify[.b, .w, .l] bus.device.function [addr]
 *      pci write[.b, .w, .l] bus.device.function addr value
 */
static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	ulong addr = 0, value = 0, cmd_size = 0;
	enum pci_size_t size = PCI_SIZE_32;
	struct udevice *dev, *bus;
	int busnum = 0;
	pci_dev_t bdf = 0;
	char cmd = 's';
	int ret = 0;

	if (argc > 1)
		cmd = argv[1][0];

	switch (cmd) {
	case 'd':		/* display */
	case 'n':		/* next */
	case 'm':		/* modify */
	case 'w':		/* write */
		/* Check for a size specification. */
		cmd_size = cmd_get_data_size(argv[1], 4);
		size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
		if (argc > 3)
			addr = hextoul(argv[3], NULL);
		if (argc > 4)
			value = hextoul(argv[4], NULL);
	case 'h':		/* header */
	case 'b':		/* bars */
		if (argc < 3)
			goto usage;
		if ((bdf = get_pci_dev(argv[2])) == -1)
			return 1;
		break;
	case 'e':
		pci_init();
		return 0;
	case 'r': /* no break */
	default:		/* scan bus */
		value = 1; /* short listing */
		if (argc > 1) {
			if (cmd != 'r' && argv[argc-1][0] == 'l') {
				value = 0;
				argc--;
			}
			if (argc > 1)
				busnum = hextoul(argv[1], NULL);
		}
		ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
		if (ret) {
			printf("No such bus\n");
			return CMD_RET_FAILURE;
		}
		if (cmd == 'r')
			pci_show_regions(bus);
		else
			pciinfo(bus, value);
		return 0;
	}

	ret = dm_pci_bus_find_bdf(bdf, &dev);
	if (ret) {
		printf("No such device\n");
		return CMD_RET_FAILURE;
	}

	switch (argv[1][0]) {
	case 'h':		/* header */
		pci_header_show(dev);
		break;
	case 'd':		/* display */
		return pci_cfg_display(dev, addr, size, value);
	case 'n':		/* next */
		if (argc < 4)
			goto usage;
		ret = pci_cfg_modify(dev, addr, size, value, 0);
		break;
	case 'm':		/* modify */
		if (argc < 4)
			goto usage;
		ret = pci_cfg_modify(dev, addr, size, value, 1);
		break;
	case 'w':		/* write */
		if (argc < 5)
			goto usage;
		ret = dm_pci_write_config(dev, addr, value, size);
		break;
	case 'b':		/* bars */
		return pci_bar_show(dev);
	default:
		ret = CMD_RET_USAGE;
		break;
	}

	return ret;
 usage:
	return CMD_RET_USAGE;
}

/***************************************************/

#ifdef CONFIG_SYS_LONGHELP
static char pci_help_text[] =
	"[bus] [long]\n"
	"    - short or long list of PCI devices on bus 'bus'\n"
	"pci enum\n"
	"    - Enumerate PCI buses\n"
	"pci header b.d.f\n"
	"    - show header of PCI device 'bus.device.function'\n"
	"pci bar b.d.f\n"
	"    - show BARs base and size for device b.d.f'\n"
	"pci regions\n"
	"    - show PCI regions\n"
	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	"    - display PCI configuration space (CFG)\n"
	"pci next[.b, .w, .l] b.d.f address\n"
	"    - modify, read and keep CFG address\n"
	"pci modify[.b, .w, .l] b.d.f address\n"
	"    -  modify, auto increment CFG address\n"
	"pci write[.b, .w, .l] b.d.f address value\n"
	"    - write to CFG address";
#endif

U_BOOT_CMD(
	pci,	5,	1,	do_pci,
	"list and access PCI Configuration Space", pci_help_text
);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c609719b WD	2	/*
	3	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Andreas Heppel <[email protected]>
	5	*
	6	* (C) Copyright 2002
	7	* Wolfgang Denk, DENX Software Engineering, [email protected].
	8	* Wolfgang Grandegger, DENX Software Engineering, [email protected].
c609719b WD	9	*/
	10
	11	/*
	12	* PCI routines
	13	*/
	14
	15	#include <common.h>
0098e179	16	#include <bootretry.h>
18d66533	17	#include <cli.h>
c609719b	18	#include <command.h>
24b852a7	19	#include <console.h>
cab24b34	20	#include <dm.h>
691d719d	21	#include <init.h>
c609719b WD	22	#include <asm/processor.h>
c609719b WD	23	#include <asm/io.h>
c609719b WD	24	#include <pci.h>
c609719b WD	25
07a58870 SG	26	struct pci_reg_info {
	27	const char *name;
	28	enum pci_size_t size;
	29	u8 offset;
	30	};
	31
72ef5b60	32	static int pci_byte_size(enum pci_size_t size)
07a58870 SG	33	{
	34	switch (size) {
	35	case PCI_SIZE_8:
72ef5b60	36	return 1;
07a58870	37	case PCI_SIZE_16:
72ef5b60	38	return 2;
07a58870 SG	39	case PCI_SIZE_32:
07a58870 SG	40	default:
72ef5b60	41	return 4;
07a58870 SG	42	}
	43	}
	44
72ef5b60 SG	45	static int pci_field_width(enum pci_size_t size)
	46	{
	47	return pci_byte_size(size) * 2;
	48	}
	49
cab24b34 SG	50	static void pci_show_regs(struct udevice dev, struct pci_reg_info regs)
	51	{
	52	for (; regs->name; regs++) {
	53	unsigned long val;
	54
	55	dm_pci_read_config(dev, regs->offset, &val, regs->size);
	56	printf(" %s =%s%#.lx\n", regs->name,
	57	(int)(28 - strlen(regs->name)), "",
	58	pci_field_width(regs->size), val);
	59	}
	60	}
07a58870	61
f5164f6b	62	static int pci_bar_show(struct udevice *dev)
e5f96a87 YY	63	{
	64	u8 header_type;
	65	int bar_cnt, bar_id, mem_type;
	66	bool is_64, is_io;
	67	u32 base_low, base_high;
	68	u32 size_low, size_high;
	69	u64 base, size;
	70	u32 reg_addr;
	71	int prefetchable;
	72
	73	dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
	74
	75	if (header_type == PCI_HEADER_TYPE_CARDBUS) {
	76	printf("CardBus doesn't support BARs\n");
	77	return -ENOSYS;
	78	}
	79
	80	bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
	81
	82	printf("ID Base Size Width Type\n");
	83	printf("----------------------------------------------------------\n");
	84
	85	bar_id = 0;
	86	reg_addr = PCI_BASE_ADDRESS_0;
	87	while (bar_cnt) {
	88	dm_pci_read_config32(dev, reg_addr, &base_low);
	89	dm_pci_write_config32(dev, reg_addr, 0xffffffff);
	90	dm_pci_read_config32(dev, reg_addr, &size_low);
	91	dm_pci_write_config32(dev, reg_addr, base_low);
	92	reg_addr += 4;
	93
	94	base = base_low & ~0xf;
	95	size = size_low & ~0xf;
	96	base_high = 0x0;
	97	size_high = 0xffffffff;
	98	is_64 = 0;
	99	prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
	100	is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
	101	mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
	102
	103	if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
	104	dm_pci_read_config32(dev, reg_addr, &base_high);
	105	dm_pci_write_config32(dev, reg_addr, 0xffffffff);
	106	dm_pci_read_config32(dev, reg_addr, &size_high);
	107	dm_pci_write_config32(dev, reg_addr, base_high);
	108	bar_cnt--;
	109	reg_addr += 4;
	110	is_64 = 1;
	111	}
	112
	113	base = base \| ((u64)base_high << 32);
	114	size = size \| ((u64)size_high << 32);
	115
	116	if ((!is_64 && size_low) \|\| (is_64 && size)) {
	117	size = ~size + 1;
4ebeb4c5	118	printf(" %d %#018llx %#018llx %d %s %s\n",
84d7f916 SG	119	bar_id, (unsigned long long)base,
84d7f916 SG	120	(unsigned long long)size, is_64 ? 64 : 32,
e5f96a87 YY	121	is_io ? "I/O" : "MEM",
	122	prefetchable ? "Prefetchable" : "");
	123	}
	124
	125	bar_id++;
	126	bar_cnt--;
	127	}
	128
	129	return 0;
	130	}
e5f96a87	131
07a58870 SG	132	static struct pci_reg_info regs_start[] = {
	133	{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
	134	{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
	135	{ "command register ID", PCI_SIZE_16, PCI_COMMAND },
	136	{ "status register", PCI_SIZE_16, PCI_STATUS },
	137	{ "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
	138	{},
	139	};
	140
	141	static struct pci_reg_info regs_rest[] = {
	142	{ "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
	143	{ "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
	144	{ "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
	145	{ "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
	146	{ "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
	147	{ "BIST", PCI_SIZE_8, PCI_BIST },
	148	{ "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
	149	{},
	150	};
	151
	152	static struct pci_reg_info regs_normal[] = {
	153	{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
	154	{ "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
	155	{ "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
	156	{ "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
	157	{ "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
	158	{ "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
	159	{ "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
	160	{ "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
	161	{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
	162	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
	163	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
	164	{ "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
	165	{ "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
	166	{},
	167	};
	168
	169	static struct pci_reg_info regs_bridge[] = {
	170	{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
	171	{ "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
	172	{ "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
	173	{ "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
	174	{ "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
	175	{ "IO base", PCI_SIZE_8, PCI_IO_BASE },
	176	{ "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
	177	{ "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
	178	{ "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
	179	{ "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
	180	{ "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
	181	{ "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
	182	{ "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
	183	{ "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
	184	{ "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
	185	{ "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
	186	{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
	187	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
	188	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
	189	{ "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
	190	{},
	191	};
	192
	193	static struct pci_reg_info regs_cardbus[] = {
	194	{ "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
	195	{ "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
196	{ "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
197	{ "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
198	{ "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
199	{ "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
200	{ "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
201	{ "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
202	{ "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
203	{ "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
204	{ "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
205	{ "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
206	{ "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
207	{ "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
208	{ "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
209	{ "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
210	{ "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
211	{ "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
212	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
213	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
214	{ "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
215	{ "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
216	{ "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
217	{ "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
218	{},
219	};
220
c2be0700 SG	221	/**
c2be0700 SG	222	* pci_header_show() - Show the header of the specified PCI device.
c609719b	223	*
c2be0700	224	* @dev: Bus+Device+Function number
c609719b	225	*/
a95f8ee9	226	static void pci_header_show(struct udevice *dev)
c609719b	227	{
cab24b34 SG	228	unsigned long class, header_type;
	229
	230	dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
	231	dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
07a58870	232	pci_show_regs(dev, regs_start);
cab24b34	233	printf(" class code = 0x%.2x (%s)\n", (int)class,
07a58870 SG	234	pci_class_str(class));
07a58870 SG	235	pci_show_regs(dev, regs_rest);
c609719b	236
7c7a23bd WD	237	switch (header_type & 0x03) {
7c7a23bd WD	238	case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
07a58870	239	pci_show_regs(dev, regs_normal);
7c7a23bd	240	break;
7c7a23bd	241	case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
07a58870	242	pci_show_regs(dev, regs_bridge);
7c7a23bd	243	break;
7c7a23bd	244	case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
07a58870	245	pci_show_regs(dev, regs_cardbus);
7c7a23bd	246	break;
8bde7f77	247
7c7a23bd WD	248	default:
7c7a23bd WD	249	printf("unknown header\n");
8bde7f77	250	break;
c609719b	251	}
c609719b WD	252	}
c609719b WD	253
577fd581	254	static void pciinfo_header(int busnum, bool short_listing)
c4f32bb2 SG	255	{
	256	printf("Scanning PCI devices on bus %d\n", busnum);
	257
	258	if (short_listing) {
	259	printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
	260	printf("_____________________________________________________________\n");
	261	}
	262	}
	263
cab24b34 SG	264	/**
	265	* pci_header_show_brief() - Show the short-form PCI device header
	266	*
	267	* Reads and prints the header of the specified PCI device in short form.
	268	*
	269	* @dev: PCI device to show
	270	*/
	271	static void pci_header_show_brief(struct udevice *dev)
	272	{
	273	ulong vendor, device;
	274	ulong class, subclass;
	275
	276	dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
	277	dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
	278	dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
	279	dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
	280
	281	printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
	282	vendor, device,
	283	pci_class_str(class), subclass);
	284	}
	285
	286	static void pciinfo(struct udevice *bus, bool short_listing)
	287	{
	288	struct udevice *dev;
	289
8b85dfc6	290	pciinfo_header(dev_seq(bus), short_listing);
cab24b34 SG	291
	292	for (device_find_first_child(bus, &dev);
	293	dev;
	294	device_find_next_child(&dev)) {
8a8d24bd	295	struct pci_child_plat *pplat;
cab24b34	296
caa4daa2	297	pplat = dev_get_parent_plat(dev);
cab24b34	298	if (short_listing) {
8b85dfc6	299	printf("%02x.%02x.%02x ", dev_seq(bus),
cab24b34 SG	300	PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
	301	pci_header_show_brief(dev);
	302	} else {
8b85dfc6 SG	303	printf("\nFound PCI device %02x.%02x.%02x:\n",
8b85dfc6 SG	304	dev_seq(bus),
cab24b34 SG	305	PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
	306	pci_header_show(dev);
	307	}
	308	}
	309	}
	310
c2be0700 SG	311	/**
	312	* get_pci_dev() - Convert the "bus.device.function" identifier into a number
	313	*
	314	* @name: Device string in the form "bus.device.function" where each is in hex
	315	* @return encoded pci_dev_t or -1 if the string was invalid
c609719b	316	*/
c2be0700	317	static pci_dev_t get_pci_dev(char *name)
c609719b WD	318	{
	319	char cnum[12];
	320	int len, i, iold, n;
	321	int bdfs[3] = {0,0,0};
	322
	323	len = strlen(name);
	324	if (len > 8)
	325	return -1;
	326	for (i = 0, iold = 0, n = 0; i < len; i++) {
	327	if (name[i] == '.') {
	328	memcpy(cnum, &name[iold], i - iold);
	329	cnum[i - iold] = '\0';
7e5f460e	330	bdfs[n++] = hextoul(cnum, NULL);
c609719b WD	331	iold = i + 1;
	332	}
	333	}
	334	strcpy(cnum, &name[iold]);
	335	if (n == 0)
	336	n = 1;
7e5f460e	337	bdfs[n] = hextoul(cnum, NULL);
c2be0700	338
c609719b WD	339	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
	340	}
	341
cab24b34 SG	342	static int pci_cfg_display(struct udevice *dev, ulong addr,
cab24b34 SG	343	enum pci_size_t size, ulong length)
c609719b WD	344	{
	345	#define DISP_LINE_LEN 16
	346	ulong i, nbytes, linebytes;
72ef5b60	347	int byte_size;
c609719b WD	348	int rc = 0;
c609719b WD	349
72ef5b60	350	byte_size = pci_byte_size(size);
c609719b	351	if (length == 0)
72ef5b60	352	length = 0x40 / byte_size; /* Standard PCI config space */
c609719b WD	353
	354	/* Print the lines.
	355	* once, and all accesses are with the specified bus width.
	356	*/
72ef5b60	357	nbytes = length * byte_size;
c609719b	358	do {
c609719b	359	printf("%08lx:", addr);
72ef5b60 SG	360	linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
	361	for (i = 0; i < linebytes; i += byte_size) {
	362	unsigned long val;
	363
cab24b34	364	dm_pci_read_config(dev, addr, &val, size);
72ef5b60 SG	365	printf(" %0*lx", pci_field_width(size), val);
72ef5b60 SG	366	addr += byte_size;
c609719b WD	367	}
	368	printf("\n");
	369	nbytes -= linebytes;
	370	if (ctrlc()) {
	371	rc = 1;
	372	break;
	373	}
	374	} while (nbytes > 0);
	375
	376	return (rc);
	377	}
	378
cab24b34	379	static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
72ef5b60	380	ulong value, int incrflag)
c609719b WD	381	{
	382	ulong i;
	383	int nbytes;
72ef5b60	384	ulong val;
c609719b WD	385
	386	/* Print the address, followed by value. Then accept input for
	387	* the next value. A non-converted value exits.
	388	*/
	389	do {
	390	printf("%08lx:", addr);
cab24b34	391	dm_pci_read_config(dev, addr, &val, size);
72ef5b60	392	printf(" %0*lx", pci_field_width(size), val);
c609719b	393
e1bf824d	394	nbytes = cli_readline(" ? ");
c609719b WD	395	if (nbytes == 0 \|\| (nbytes == 1 && console_buffer[0] == '-')) {
	396	/* <CR> pressed as only input, don't modify current
	397	* location and move to next. "-" pressed will go back.
	398	*/
	399	if (incrflag)
	400	addr += nbytes ? -size : size;
	401	nbytes = 1;
b26440f1 SG	402	/* good enough to not time out */
b26440f1 SG	403	bootretry_reset_cmd_timeout();
c609719b WD	404	}
	405	#ifdef CONFIG_BOOT_RETRY_TIME
	406	else if (nbytes == -2) {
	407	break; /* timed out, exit the command */
	408	}
	409	#endif
	410	else {
	411	char *endp;
7e5f460e	412	i = hextoul(console_buffer, &endp);
c609719b WD	413	nbytes = endp - console_buffer;
c609719b WD	414	if (nbytes) {
c609719b WD	415	/* good enough to not time out
c609719b WD	416	*/
b26440f1	417	bootretry_reset_cmd_timeout();
cab24b34	418	dm_pci_write_config(dev, addr, i, size);
c609719b WD	419	if (incrflag)
	420	addr += size;
	421	}
	422	}
	423	} while (nbytes);
	424
	425	return 0;
	426	}
	427
b997a73e SG	428	static const struct pci_flag_info {
	429	uint flag;
	430	const char *name;
	431	} pci_flag_info[] = {
	432	{ PCI_REGION_IO, "io" },
	433	{ PCI_REGION_PREFETCH, "prefetch" },
	434	{ PCI_REGION_SYS_MEMORY, "sysmem" },
	435	{ PCI_REGION_RO, "readonly" },
	436	{ PCI_REGION_IO, "io" },
	437	};
	438
	439	static void pci_show_regions(struct udevice *bus)
	440	{
	441	struct pci_controller *hose = dev_get_uclass_priv(bus);
	442	const struct pci_region *reg;
	443	int i, j;
	444
	445	if (!hose) {
	446	printf("Bus '%s' is not a PCI controller\n", bus->name);
	447	return;
	448	}
	449
4ebeb4c5	450	printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
b997a73e SG	451	"Flags");
b997a73e SG	452	for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
4ebeb4c5	453	printf("%d %#018llx %#018llx %#018llx ", i,
b997a73e SG	454	(unsigned long long)reg->bus_start,
	455	(unsigned long long)reg->phys_start,
	456	(unsigned long long)reg->size);
	457	if (!(reg->flags & PCI_REGION_TYPE))
	458	printf("mem ");
	459	for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
	460	if (reg->flags & pci_flag_info[j].flag)
	461	printf("%s ", pci_flag_info[j].name);
	462	}
	463	printf("\n");
	464	}
	465	}
b997a73e	466
c609719b WD	467	/* PCI Configuration Space access commands
	468	*
	469	* Syntax:
	470	* pci display[.b, .w, .l] bus.device.function} [addr] [len]
	471	* pci next[.b, .w, .l] bus.device.function [addr]
	472	* pci modify[.b, .w, .l] bus.device.function [addr]
	473	* pci write[.b, .w, .l] bus.device.function addr value
	474	*/
09140113	475	static int do_pci(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
c609719b	476	{
72ef5b60 SG	477	ulong addr = 0, value = 0, cmd_size = 0;
72ef5b60 SG	478	enum pci_size_t size = PCI_SIZE_32;
cab24b34	479	struct udevice dev, bus;
ca7de76d	480	int busnum = 0;
c609719b WD	481	pci_dev_t bdf = 0;
c609719b WD	482	char cmd = 's';
bfa4191e	483	int ret = 0;
c609719b WD	484
	485	if (argc > 1)
	486	cmd = argv[1][0];
	487
	488	switch (cmd) {
	489	case 'd': /* display */
	490	case 'n': /* next */
	491	case 'm': /* modify */
	492	case 'w': /* write */
	493	/* Check for a size specification. */
72ef5b60 SG	494	cmd_size = cmd_get_data_size(argv[1], 4);
72ef5b60 SG	495	size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
c609719b	496	if (argc > 3)
7e5f460e	497	addr = hextoul(argv[3], NULL);
c609719b	498	if (argc > 4)
7e5f460e	499	value = hextoul(argv[4], NULL);
c609719b	500	case 'h': /* header */
e5f96a87	501	case 'b': /* bars */
c609719b WD	502	if (argc < 3)
	503	goto usage;
	504	if ((bdf = get_pci_dev(argv[2])) == -1)
	505	return 1;
	506	break;
96d61603	507	case 'e':
e578b92c SW	508	pci_init();
e578b92c SW	509	return 0;
b997a73e	510	case 'r': /* no break */
c609719b WD	511	default: /* scan bus */
c609719b WD	512	value = 1; /* short listing */
c609719b	513	if (argc > 1) {
b997a73e	514	if (cmd != 'r' && argv[argc-1][0] == 'l') {
c609719b WD	515	value = 0;
	516	argc--;
	517	}
	518	if (argc > 1)
7e5f460e	519	busnum = hextoul(argv[1], NULL);
c609719b	520	}
cab24b34 SG	521	ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
	522	if (ret) {
	523	printf("No such bus\n");
	524	return CMD_RET_FAILURE;
	525	}
b997a73e SG	526	if (cmd == 'r')
	527	pci_show_regions(bus);
	528	else
	529	pciinfo(bus, value);
c609719b WD	530	return 0;
	531	}
	532
f3f1faef	533	ret = dm_pci_bus_find_bdf(bdf, &dev);
cab24b34 SG	534	if (ret) {
	535	printf("No such device\n");
	536	return CMD_RET_FAILURE;
	537	}
32ec5b34	538
c609719b WD	539	switch (argv[1][0]) {
c609719b WD	540	case 'h': /* header */
32ec5b34	541	pci_header_show(dev);
bfa4191e	542	break;
c609719b	543	case 'd': /* display */
32ec5b34	544	return pci_cfg_display(dev, addr, size, value);
c609719b WD	545	case 'n': /* next */
	546	if (argc < 4)
	547	goto usage;
32ec5b34	548	ret = pci_cfg_modify(dev, addr, size, value, 0);
bfa4191e	549	break;
c609719b WD	550	case 'm': /* modify */
	551	if (argc < 4)
	552	goto usage;
32ec5b34	553	ret = pci_cfg_modify(dev, addr, size, value, 1);
bfa4191e	554	break;
c609719b WD	555	case 'w': /* write */
	556	if (argc < 5)
	557	goto usage;
cab24b34	558	ret = dm_pci_write_config(dev, addr, value, size);
bfa4191e	559	break;
e5f96a87 YY	560	case 'b': /* bars */
e5f96a87 YY	561	return pci_bar_show(dev);
bfa4191e SG	562	default:
	563	ret = CMD_RET_USAGE;
	564	break;
c609719b WD	565	}
c609719b WD	566
bfa4191e	567	return ret;
c609719b	568	usage:
4c12eeb8	569	return CMD_RET_USAGE;
c609719b WD	570	}
c609719b WD	571
8bde7f77 WD	572	/***************************************************/
8bde7f77 WD	573
088f1b19 KP	574	#ifdef CONFIG_SYS_LONGHELP
088f1b19 KP	575	static char pci_help_text[] =
8bde7f77 WD	576	"[bus] [long]\n"
8bde7f77 WD	577	" - short or long list of PCI devices on bus 'bus'\n"
96d61603	578	"pci enum\n"
e578b92c	579	" - Enumerate PCI buses\n"
8bde7f77 WD	580	"pci header b.d.f\n"
8bde7f77 WD	581	" - show header of PCI device 'bus.device.function'\n"
e5f96a87 YY	582	"pci bar b.d.f\n"
e5f96a87 YY	583	" - show BARs base and size for device b.d.f'\n"
b997a73e SG	584	"pci regions\n"
b997a73e SG	585	" - show PCI regions\n"
8bde7f77 WD	586	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	587	" - display PCI configuration space (CFG)\n"
	588	"pci next[.b, .w, .l] b.d.f address\n"
	589	" - modify, read and keep CFG address\n"
	590	"pci modify[.b, .w, .l] b.d.f address\n"
	591	" - modify, auto increment CFG address\n"
	592	"pci write[.b, .w, .l] b.d.f address value\n"
088f1b19 KP	593	" - write to CFG address";
	594	#endif
	595
	596	U_BOOT_CMD(
	597	pci, 5, 1, do_pci,
	598	"list and access PCI Configuration Space", pci_help_text
8bde7f77	599	);