[u-boot.git] / include / configs / alpr.h

/*
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_ALPR		1	    /* Board is ebony		*/
#define CONFIG_440GX		1	    /* Specifc GX support	*/
#define CONFIG_440		1	    /* ... PPC440 family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
#define CONFIG_LAST_STAGE_INIT	1	    /* call last_stage_init()	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
#define CONFIG_4xx_DCACHE		/* Enable i- and d-cache	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0			*/
#define CONFIG_SYS_FLASH_BASE		0xffe00000	/* start of FLASH		*/
#define CONFIG_SYS_MONITOR_BASE	0xfffc0000	/* start of monitor		*/
#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory		*/
#define	CONFIG_SYS_PCI_MEMSIZE		0x40000000	/* size of mapped pci memory	*/
#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM		*/
#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs		*/
#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000


#define CONFIG_SYS_FPGA_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM  1
#define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE    0x2000	    /* Size of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

#define CONFIG_SYS_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
#define CONFIG_SYS_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_CFI		1	/* The flash is CFI compatible		*/
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use common CFI driver		*/
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
#undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
#define CONFIG_SYS_SDRAM_TABLE	{ \
		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} }	/* Don't probe these addrs */

/*-----------------------------------------------------------------------
 * I2C EEPROM (PCF8594C)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
					/* 8 byte page write mode using */
					/* last 3 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run kernelx\" to boot the system;"			\
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth3\0"							\
	"hostname=alpr\0"						\
	"fdt_file=alpr/alpr.dtb\0"					\
	"fdt_addr=400000\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath} ${init}\0"		\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
		"mem=193M\0"						\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
		"bootm\0"						\
	"net_nfs_fdt=tftp 200000 ${bootfile};"				\
		"tftp ${fdt_addr} ${fdt_file};"				\
		"run nfsargs addip addtty;"				\
		"bootm 200000 - ${fdt_addr}\0"				\
	"rootpath=/opt/projects/alpr/nfs_root\0"			\
	"bootfile=/alpr/uImage\0"					\
	"kernel_addr=fff00000\0"					\
	"ramdisk_addr=fff10000\0"					\
	"load=tftp 100000 /alpr/u-boot/u-boot.bin\0"			\
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
		"cp.b 100000 fffc0000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load update\0"						\
	"ethprime=ppc_4xx_eth3\0"					\
	"ethact=ppc_4xx_eth3\0"						\
	"autoload=no\0"							\
	"ipconfig=dhcp;setenv serverip 11.0.0.152\0"			\
	"load_fpga=fpga load 0 ffe00000 10dd9a\0"			\
	"mtdargs=setenv bootargs root=/dev/mtdblock6 rw "		\
		"rootfstype=jffs2 init=/sbin/init\0"			\
	"kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
		";bootm 200000\0"					\
	"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip "	\
		"addtty;bootm 200000\0"					\
	"kernel1=setenv actkernel 'kernel1';run load_fpga "		\
		"kernel1_mtd\0"						\
	"kernel2=setenv actkernel 'kernel2';run load_fpga "		\
		"kernel2_mtd\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run kernel2"

#define CONFIG_BOOTDELAY	2	/* autoboot after 5 seconds	*/

#define CONFIG_BAUDRATE		115200

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0x02	/* dummy setting, no EMAC0 used	*/
#define CONFIG_PHY1_ADDR	0x03	/* dummy setting, no EMAC1 used	*/
#define CONFIG_PHY2_ADDR	0x01	/* PHY address for EMAC2	*/
#define CONFIG_PHY3_ADDR	0x02	/* PHY address for EMAC3	*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
#define CONFIG_M88E1111_PHY	1	/* needed for PHY specific setup*/
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#define CONFIG_CMD_PCI

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_ALT_MEMTEST		1	/* Enable more extensive memtest*/
#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC	1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */

#define CONFIG_SYS_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
#define CONFIG_PCI_BOOTDELAY	1       /* enable pci bootdelay variable*/

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
#define CONFIG_SYS_PCI_MASTER_INIT

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */

/*-----------------------------------------------------------------------
 * FPGA stuff
 *-----------------------------------------------------------------------*/
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#define CONFIG_SYS_FPGA_CHECK_CTRLC
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA_COUNT       1		/* Ich habe 2 ... aber in
					Reihe geschaltet -> sollte gehen,
					aufpassen mit Datasize ist jetzt
					halt doppelt so gross ... Seite 306
					ist das mit den multiple Device in PS
					Mode erklaert ...*/

/* FPGA program pin configuration */
#define CONFIG_SYS_GPIO_CLK		18	/* FPGA clk pin (cpu output)		*/
#define CONFIG_SYS_GPIO_DATA		19	/* FPGA data pin (cpu output)		*/
#define CONFIG_SYS_GPIO_STATUS		20	/* FPGA status pin (cpu input)		*/
#define CONFIG_SYS_GPIO_CONFIG		21	/* FPGA CONFIG pin (cpu output)		*/
#define CONFIG_SYS_GPIO_CON_DON	22	/* FPGA CONFIG_DONE pin (cpu input)	*/

#define CONFIG_SYS_GPIO_SEL_DPR	14	/* cpu output */
#define CONFIG_SYS_GPIO_SEL_AVR	15	/* cpu output */
#define CONFIG_SYS_GPIO_PROG_EN	23	/* cpu output */

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup
 *-----------------------------------------------------------------------*/
#define CONFIG_SYS_GPIO_SHUTDOWN	(0x80000000 >> 6)
#define CONFIG_SYS_GPIO_SSD_EMPTY	(0x80000000 >> 9)
#define CONFIG_SYS_GPIO_EREADY		(0x80000000 >> 26)
#define CONFIG_SYS_GPIO_REV0		(0x80000000 >> 14)
#define CONFIG_SYS_GPIO_REV1		(0x80000000 >> 15)

/*-----------------------------------------------------------------------
 * NAND-FLASH stuff
 *-----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE	4
#define CONFIG_SYS_NAND_BASE		0xF0000000	/* NAND FLASH Base Address	*/
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2,	\
				  CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
#define CONFIG_SYS_NAND_QUIET_TEST	1	/* don't warn upon unknown NAND flash	*/
#define CONFIG_SYS_NAND_MAX_OOBFREE	2
#define CONFIG_SYS_NAND_MAX_ECCPOS	56

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (NAND-FLASH) initialization					*/
#define CONFIG_SYS_EBC_PB1AP		0x01840380	/* TWT=3			*/
#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#endif	/* __CONFIG_H */
Commit	Line	Data
899620c2	1	/*
9462732a	2	* (C) Copyright 2006-2008
899620c2 SR	3	* Stefan Roese, DENX Software Engineering, [email protected].
899620c2 SR	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
899620c2 SR	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*-----------------------------------------------------------------------
	12	* High Level Configuration Options
	13	----------------------------------------------------------------------/
	14	#define CONFIG_ALPR 1 /* Board is ebony */
	15	#define CONFIG_440GX 1 /* Specifc GX support */
efa35cf1	16	#define CONFIG_440 1 /* ... PPC440 family */
899620c2	17	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
1c2ce226	18	#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
2ae18241 WD	19
	20	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
	21
1c2ce226	22	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
511e4f9e	23	#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
899620c2 SR	24
	25	/*-----------------------------------------------------------------------
	26	* Base addresses -- Note these are effective addresses where the
	27	* actual resources get mapped (not physical addresses)
	28	----------------------------------------------------------------------/
6d0f6bcf JCPV	29	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	30	#define CONFIG_SYS_FLASH_BASE 0xffe00000 /* start of FLASH */
	31	#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
	32	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	33	#define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
6d0f6bcf JCPV	34	#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
	35	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
	36	#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
	37	#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
	38	#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
	39
	40
	41	#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
	42	#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
899620c2 SR	43
	44	/*-----------------------------------------------------------------------
	45	* Initial RAM & stack pointer (placed in internal SRAM)
	46	----------------------------------------------------------------------/
6d0f6bcf JCPV	47	#define CONFIG_SYS_TEMP_STACK_OCM 1
	48	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	49	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
553f0982	50	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
899620c2	51
25ddd1fb	52	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096	53	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
899620c2	54
6d0f6bcf JCPV	55	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	56	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
899620c2 SR	57
	58	/*-----------------------------------------------------------------------
	59	* Serial Port
	60	----------------------------------------------------------------------/
550650dd SR	61	#define CONFIG_CONS_INDEX 2 /* Use UART1 */
	62	#define CONFIG_SYS_NS16550
	63	#define CONFIG_SYS_NS16550_SERIAL
	64	#define CONFIG_SYS_NS16550_REG_SIZE 1
	65	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	66
6d0f6bcf	67	#undef CONFIG_SYS_EXT_SERIAL_CLOCK
899620c2	68	#define CONFIG_BAUDRATE 115200
899620c2	69
6d0f6bcf	70	#define CONFIG_SYS_BAUDRATE_TABLE \
899620c2 SR	71	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
899620c2 SR	72
899620c2 SR	73	/*-----------------------------------------------------------------------
	74	* FLASH related
	75	----------------------------------------------------------------------/
6d0f6bcf	76	#define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */
00b1883a	77	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
6d0f6bcf JCPV	78	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	79	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	80	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	81	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	82	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
899620c2	83
5a1aceb0	84	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
899620c2	85
0e8d1586	86	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
6d0f6bcf	87	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586	88	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
899620c2 SR	89
899620c2 SR	90	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	91	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	92	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
899620c2 SR	93
	94	/*-----------------------------------------------------------------------
	95	* DDR SDRAM
	96	----------------------------------------------------------------------/
	97	#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
	98	#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
	99	#undef CONFIG_SDRAM_ECC /* enable ECC support */
6d0f6bcf	100	#define CONFIG_SYS_SDRAM_TABLE { \
899620c2 SR	101	{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
	102	{(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
	103
	104	/*-----------------------------------------------------------------------
	105	* I2C
	106	----------------------------------------------------------------------/
880540de DE	107	#define CONFIG_SYS_I2C
	108	#define CONFIG_SYS_I2C_PPC4XX
	109	#define CONFIG_SYS_I2C_PPC4XX_CH0
	110	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
	111	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
	112	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
899620c2 SR	113
	114	/*-----------------------------------------------------------------------
	115	* I2C EEPROM (PCF8594C)
	116	----------------------------------------------------------------------/
6d0f6bcf JCPV	117	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
6d0f6bcf JCPV	118	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
899620c2	119	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	120	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	121	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
899620c2 SR	122	/* 8 byte page write mode using */
899620c2 SR	123	/* last 3 bits of the address */
6d0f6bcf	124	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
899620c2 SR	125
899620c2 SR	126	#define CONFIG_PREBOOT "echo;" \
6304430e	127	"echo Type \"run kernelx\" to boot the system;" \
899620c2 SR	128	"echo"
	129
	130	#undef CONFIG_BOOTARGS
	131
	132	#define CONFIG_EXTRA_ENV_SETTINGS \
1c2ce226	133	"netdev=eth3\0" \
899620c2	134	"hostname=alpr\0" \
9462732a SR	135	"fdt_file=alpr/alpr.dtb\0" \
9462732a SR	136	"fdt_addr=400000\0" \
899620c2	137	"nfsargs=setenv bootargs root=/dev/nfs rw " \
6304430e	138	"nfsroot=${serverip}:${rootpath} ${init}\0" \
899620c2 SR	139	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	140	"addip=setenv bootargs ${bootargs} " \
	141	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	142	":${hostname}:${netdev}:off panic=1\0" \
1c2ce226 SR	143	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
1c2ce226 SR	144	"mem=193M\0" \
899620c2 SR	145	"flash_nfs=run nfsargs addip addtty;" \
	146	"bootm ${kernel_addr}\0" \
	147	"flash_self=run ramargs addip addtty;" \
	148	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	149	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
93e14596	150	"bootm\0" \
9462732a SR	151	"net_nfs_fdt=tftp 200000 ${bootfile};" \
	152	"tftp ${fdt_addr} ${fdt_file};" \
	153	"run nfsargs addip addtty;" \
	154	"bootm 200000 - ${fdt_addr}\0" \
1c2ce226 SR	155	"rootpath=/opt/projects/alpr/nfs_root\0" \
1c2ce226 SR	156	"bootfile=/alpr/uImage\0" \
899620c2 SR	157	"kernel_addr=fff00000\0" \
899620c2 SR	158	"ramdisk_addr=fff10000\0" \
1c2ce226	159	"load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
899620c2 SR	160	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	161	"cp.b 100000 fffc0000 40000;" \
	162	"setenv filesize;saveenv\0" \
d8ab58b2	163	"upd=run load update\0" \
f16c1da9 SR	164	"ethprime=ppc_4xx_eth3\0" \
	165	"ethact=ppc_4xx_eth3\0" \
	166	"autoload=no\0" \
	167	"ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
f16c1da9 SR	168	"load_fpga=fpga load 0 ffe00000 10dd9a\0" \
	169	"mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
	170	"rootfstype=jffs2 init=/sbin/init\0" \
	171	"kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
	172	";bootm 200000\0" \
	173	"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
	174	"addtty;bootm 200000\0" \
6304430e SR	175	"kernel1=setenv actkernel 'kernel1';run load_fpga " \
	176	"kernel1_mtd\0" \
	177	"kernel2=setenv actkernel 'kernel2';run load_fpga " \
	178	"kernel2_mtd\0" \
899620c2	179	""
f16c1da9 SR	180
f16c1da9 SR	181	#define CONFIG_BOOTCOMMAND "run kernel2"
899620c2	182
1c2ce226	183	#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
899620c2 SR	184
	185	#define CONFIG_BAUDRATE 115200
	186
	187	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	188	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
899620c2	189
96e21f86	190	#define CONFIG_PPC4xx_EMAC
899620c2	191	#define CONFIG_MII 1 /* MII PHY management */
899620c2 SR	192	#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
899620c2 SR	193	#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
1c2ce226 SR	194	#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
1c2ce226 SR	195	#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
899620c2 SR	196	#define CONFIG_HAS_ETH0
	197	#define CONFIG_HAS_ETH1
	198	#define CONFIG_HAS_ETH2
	199	#define CONFIG_HAS_ETH3
	200	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
ec0c2ec7	201	#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
899620c2	202	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
6d0f6bcf	203	#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
5bc528fa SR	204
5bc528fa SR	205	#define CONFIG_NETCONSOLE /* include NetConsole support */
899620c2	206
0b361c91	207
80ff4f99 JL	208	/*
	209	* BOOTP options
	210	*/
	211	#define CONFIG_BOOTP_BOOTFILESIZE
	212	#define CONFIG_BOOTP_BOOTPATH
	213	#define CONFIG_BOOTP_GATEWAY
	214	#define CONFIG_BOOTP_HOSTNAME
	215
	216
0b361c91 JL	217	/*
	218	* Command line configuration.
	219	*/
	220	#include <config_cmd_default.h>
	221
0b361c91	222	#define CONFIG_CMD_DHCP
0b361c91	223	#define CONFIG_CMD_EEPROM
0b361c91 JL	224	#define CONFIG_CMD_FPGA
0b361c91 JL	225	#define CONFIG_CMD_I2C
288991c9 SR	226	#undef CONFIG_CMD_LOADB
288991c9 SR	227	#undef CONFIG_CMD_LOADS
0b361c91 JL	228	#define CONFIG_CMD_MII
	229	#define CONFIG_CMD_NAND
	230	#define CONFIG_CMD_NET
8c92af7b	231	#undef CONFIG_CMD_NFS
288991c9	232	#define CONFIG_CMD_PCI
899620c2 SR	233
	234	#undef CONFIG_WATCHDOG /* watchdog disabled */
	235
	236	/*
	237	* Miscellaneous configurable options
	238	*/
6d0f6bcf	239	#define CONFIG_SYS_LONGHELP /* undef to save memory */
0b361c91	240	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	241	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
899620c2	242	#else
6d0f6bcf	243	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
899620c2	244	#endif
6d0f6bcf JCPV	245	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	246	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	247	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
899620c2	248
6d0f6bcf JCPV	249	#define CONFIG_SYS_ALT_MEMTEST 1 /* Enable more extensive memtest*/
	250	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
	251	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
899620c2	252
6d0f6bcf JCPV	253	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	254	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
899620c2	255
5bc528fa	256	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
899620c2	257	#define CONFIG_LOOPW 1 /* enable loopw command */
1636d1c8	258	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
899620c2	259	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
1c2ce226 SR	260	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
1c2ce226 SR	261
6d0f6bcf	262	#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
899620c2	263
899620c2 SR	264	/*-----------------------------------------------------------------------
	265	* PCI stuff
	266	*-----------------------------------------------------------------------
	267	*/
	268	/* General PCI */
	269	#define CONFIG_PCI /* include pci support */
842033e6	270	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
899620c2 SR	271	#define CONFIG_PCI_PNP /* do pci plug-and-play */
899620c2 SR	272	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	273	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
1c2ce226	274	#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
899620c2 SR	275
899620c2 SR	276	/* Board-specific PCI */
6d0f6bcf JCPV	277	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
6d0f6bcf JCPV	278	#define CONFIG_SYS_PCI_MASTER_INIT
899620c2	279
6d0f6bcf JCPV	280	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
6d0f6bcf JCPV	281	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
899620c2 SR	282
	283	/*-----------------------------------------------------------------------
	284	* FPGA stuff
1c2ce226	285	-----------------------------------------------------------------------/
0133502e MF	286	#define CONFIG_FPGA
	287	#define CONFIG_FPGA_ALTERA
	288	#define CONFIG_FPGA_CYCLON2
6d0f6bcf JCPV	289	#define CONFIG_SYS_FPGA_CHECK_CTRLC
6d0f6bcf JCPV	290	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
899620c2 SR	291	#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
	292	Reihe geschaltet -> sollte gehen,
	293	aufpassen mit Datasize ist jetzt
	294	halt doppelt so gross ... Seite 306
	295	ist das mit den multiple Device in PS
	296	Mode erklaert ...*/
	297
899620c2	298	/* FPGA program pin configuration */
6d0f6bcf JCPV	299	#define CONFIG_SYS_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
	300	#define CONFIG_SYS_GPIO_DATA 19 /* FPGA data pin (cpu output) */
	301	#define CONFIG_SYS_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
	302	#define CONFIG_SYS_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
	303	#define CONFIG_SYS_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
899620c2	304
6d0f6bcf JCPV	305	#define CONFIG_SYS_GPIO_SEL_DPR 14 /* cpu output */
	306	#define CONFIG_SYS_GPIO_SEL_AVR 15 /* cpu output */
	307	#define CONFIG_SYS_GPIO_PROG_EN 23 /* cpu output */
899620c2	308
1c2ce226 SR	309	/*-----------------------------------------------------------------------
	310	* Definitions for GPIO setup
	311	-----------------------------------------------------------------------/
6d0f6bcf JCPV	312	#define CONFIG_SYS_GPIO_SHUTDOWN (0x80000000 >> 6)
	313	#define CONFIG_SYS_GPIO_SSD_EMPTY (0x80000000 >> 9)
	314	#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 26)
	315	#define CONFIG_SYS_GPIO_REV0 (0x80000000 >> 14)
	316	#define CONFIG_SYS_GPIO_REV1 (0x80000000 >> 15)
1c2ce226 SR	317
1c2ce226 SR	318	/*-----------------------------------------------------------------------
899620c2	319	* NAND-FLASH stuff
1c2ce226	320	-----------------------------------------------------------------------/
6d0f6bcf	321	#define CONFIG_SYS_MAX_NAND_DEVICE 4
6d0f6bcf JCPV	322	#define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
	323	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
	324	CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
	325	#define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
68ec9c85 PK	326	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
68ec9c85 PK	327	#define CONFIG_SYS_NAND_MAX_ECCPOS 56
899620c2 SR	328
	329	/*-----------------------------------------------------------------------
	330	* External Bus Controller (EBC) Setup
	331	----------------------------------------------------------------------/
6d0f6bcf	332	#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
899620c2 SR	333
899620c2 SR	334	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
6d0f6bcf JCPV	335	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	336	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH \| 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
5bc528fa SR	337
5bc528fa SR	338	/* Memory Bank 1 (NAND-FLASH) initialization */
6d0f6bcf JCPV	339	#define CONFIG_SYS_EBC_PB1AP 0x01840380 /* TWT=3 */
6d0f6bcf JCPV	340	#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_BASE \| 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
899620c2 SR	341
	342	/*
	343	* For booting Linux, the board info and command line data
	344	* have to be in the first 8 MB of memory, since this is
	345	* the maximum mapped by the Linux kernel during initialization.
	346	*/
6d0f6bcf	347	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
899620c2	348
0b361c91	349	#if defined(CONFIG_CMD_KGDB)
899620c2	350	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
899620c2	351	#endif
9462732a SR	352
	353	/* pass open firmware flat tree */
	354	#define CONFIG_OF_LIBFDT 1
	355	#define CONFIG_OF_BOARD_SETUP 1
	356
899620c2	357	#endif /* __CONFIG_H */