]> Git Repo - u-boot.git/blame - board/eltec/bab7xx/misc.c
projects / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
powerpc: Minimal private libgcc to build on Debian
[u-boot.git] / board / eltec / bab7xx / misc.c
CommitLineData
e69b4b8f
WD		 1/*
2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <[email protected]>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* includes */
25#include <common.h>
26#include <linux/ctype.h>
27#include <pci.h>
28#include <net.h>
29#include <mpc106.h>
30#include <w83c553f.h>
31#include "srom.h"
32
33/* imports */
e69b4b8f
WD		 34extern int l2_cache_enable (int l2control);
35extern void *nvram_read (void *dest, const short src, size_t count);
36extern void nvram_write (short dest, const void *src, size_t count);
37
38/* globals */
39unsigned int ata_reset_time = 60;
40unsigned int scsi_reset_time = 10;
41unsigned int eltec_board;
42
43/* BAB750 uses SYM53C875(default) and BAB740 uses SYM53C860
44 * values fixed after board identification
45 */
46unsigned short scsi_dev_id = PCI_DEVICE_ID_NCR_53C875;
47unsigned int scsi_max_scsi_id = 15;
48unsigned char scsi_sym53c8xx_ccf = 0x13;
49
50/*----------------------------------------------------------------------------*/
51/*
52 * handle sroms on BAB740/750
53 * fix ether address
54 * L2 cache initialization
55 * ide dma control
56 */
57int misc_init_r (void)
58{
59 revinfo eerev;
77ddac94 60 char *ptr;
e69b4b8f
WD		 61 u_int i, l, initSrom, copyNv;
62 char buf[256];
63 char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
8bde7f77 64 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
e69b4b8f
WD		 65 pci_dev_t bdf;
66
67 char sromSYM[] = {
68#ifdef TULIP_BUG
69 /* 10BaseT, 100BaseTx no full duplex modes */
70 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
71 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
72 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
73 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
74 0x02, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00,
75 0x88, 0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61,
76 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
77 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
78 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
79 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
80 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
81 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
82 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
83 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
84 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
85 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0xe8
86#endif
87 /* 10BaseT, 10BaseT-FD, 100BaseTx, 100BaseTx-FD */
88 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
89 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
90 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
91 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
92 0x04, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00,
93 0x86, 0x02, 0x04, 0xaf, 0x08, 0xa5, 0x00, 0x88,
94 0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61, 0x80,
95 0x88, 0x04, 0x05, 0x27, 0x08, 0x25, 0x00, 0x61,
96 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
97 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
98 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
99 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
101 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
102 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
103 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x77
104 };
105
106 char sromMII[] = {
107 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
108 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
109 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x5b, 0x00,
110 0x2e, 0x4d, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
111 0x01, 0x95, 0x03, 0x00, 0x00, 0x04, 0x01, 0x08,
112 0x00, 0x00, 0x02, 0x08, 0x02, 0x00, 0x00, 0x78,
113 0xe0, 0x01, 0x00, 0x50, 0x00, 0x18, 0x80, 0x00,
114 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
116 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
117 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
118 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
120 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
122 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xde, 0x41
123 };
124
125 /*
126 * Check/Remake revision info
127 */
128 initSrom = 0;
129 copyNv = 0;
130
131 /* read out current revision srom contens */
132 el_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo),
8bde7f77 133 SECOND_DEVICE, FIRST_BLOCK);
e69b4b8f
WD		 134
135 /* read out current nvram shadow image */
6d0f6bcf 136 nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE);
e69b4b8f
WD		 137
138 if (strcmp (eerev.magic, "ELTEC") != 0)
139 {
8bde7f77 140 /* srom is not initialized -> create a default revision info */
77ddac94 141 for (i = 0, ptr = (char *)&eerev; i < sizeof(revinfo); i++)
8bde7f77
WD		 142 *ptr++ = 0x00;
143 strcpy(eerev.magic, "ELTEC");
144 eerev.revrev[0] = 1;
145 eerev.revrev[1] = 0;
146 eerev.size = 0x00E0;
147 eerev.category[0] = 0x01;
148
149 /* node id from dead e128 as default */
150 eerev.etheraddr[0] = 0x00;
151 eerev.etheraddr[1] = 0x00;
152 eerev.etheraddr[2] = 0x5B;
153 eerev.etheraddr[3] = 0x00;
154 eerev.etheraddr[4] = 0x2E;
155 eerev.etheraddr[5] = 0x4D;
156
157 /* cache config word for bab750 */
158 *(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH;
159
160 initSrom = 1; /* force dialog */
161 copyNv = 1; /* copy to nvram */
e69b4b8f
WD		 162 }
163
6d0f6bcf
JCPV		 164 if ((copyNv == 0) && (el_srom_checksum((u_char*)&eerev, CONFIG_SYS_SROM_SIZE) !=
165 el_srom_checksum((u_char*)buf, CONFIG_SYS_SROM_SIZE)))
e69b4b8f 166 {
8bde7f77
WD		 167 printf ("Invalid revision info copy in nvram !\n");
168 printf ("Press key:\n <c> to copy current revision info to nvram.\n");
169 printf (" <r> to reenter revision info.\n");
170 printf ("=> ");
171 if (0 != readline (NULL))
172 {
173 switch ((char)toupper(console_buffer[0]))
174 {
175 case 'C':
176 copyNv = 1;
177 break;
178 case 'R':
179 copyNv = 1;
180 initSrom = 1;
181 break;
182 }
183 }
e69b4b8f
WD		 184 }
185
186 if (initSrom)
187 {
8bde7f77
WD		 188 memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */
189 printf ("Enter revision number (0-9): %c ", eerev.revision[0][0]);
190 if (0 != readline (NULL))
191 {
192 eerev.revision[0][0] = (char)toupper(console_buffer[0]);
193 memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
194 }
195
196 printf ("Enter revision character (A-Z): %c ", eerev.revision[0][1]);
197 if (1 == readline (NULL))
198 {
199 eerev.revision[0][1] = (char)toupper(console_buffer[0]);
200 }
201
202 printf ("Enter board name (V-XXXX-XXXX): %s ", (char *)&eerev.board);
203 if (11 == readline (NULL))
204 {
205 for (i=0; i<11; i++)
206 eerev.board[i] = (char)toupper(console_buffer[i]);
207 eerev.board[11] = '\0';
208 }
209
210 printf ("Enter serial number: %s ", (char *)&eerev.serial );
211 if (6 == readline (NULL))
212 {
213 for (i=0; i<6; i++)
214 eerev.serial[i] = console_buffer[i];
215 eerev.serial[6] = '\0';
216 }
217
218 printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ",
219 eerev.etheraddr[0], eerev.etheraddr[1],
220 eerev.etheraddr[2], eerev.etheraddr[3],
221 eerev.etheraddr[4], eerev.etheraddr[5]);
222 if (12 == readline (NULL))
223 {
224 for (i=0; i<12; i+=2)
225 eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
226 hex[toupper(console_buffer[i+1])-'0']);
227 }
228
229 l = strlen ((char *)&eerev.text);
230 printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text );
231 if (0 != readline (NULL))
232 {
233 for (i = l; i<63; i++)
234 eerev.text[i] = console_buffer[i-l];
235 eerev.text[63] = '\0';
236 }
237
238 if (strstr ((char *)&eerev.board, "75") != NULL)
239 eltec_board = 750;
240 else
241 eltec_board = 740;
242
243 if (eltec_board == 750)
244 {
245 if (CPU_TYPE == CPU_TYPE_750)
246 *(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH;
247 else
248 *(int*)&eerev.res[0] = CLK2P5TO1_1MB_PB_0P5DH;
249
250 printf("Enter L2Cache config word with leading zero (HEX): %08X ",
251 *(int*)&eerev.res[0] );
252 if (0 != readline (NULL))
253 {
254 for (i=0; i<7; i+=2)
255 {
256 eerev.res[i>>1] =
257 (char)(16*hex[toupper(console_buffer[i])-'0'] +
258 hex[toupper(console_buffer[i+1])-'0']);
259 }
260 }
261
262 /* prepare network eeprom */
263 sromMII[20] = eerev.etheraddr[0];
264 sromMII[21] = eerev.etheraddr[1];
265 sromMII[22] = eerev.etheraddr[2];
266 sromMII[23] = eerev.etheraddr[3];
267 sromMII[24] = eerev.etheraddr[4];
268 sromMII[25] = eerev.etheraddr[5];
269 printf("\nSRom: Writing DEC21143 MII info .. ");
270
271 if (dc_srom_store ((u_short *)sromMII) == -1)
272 printf("FAILED\n");
273 else
274 printf("OK\n");
275 }
276
277 if (eltec_board == 740)
278 {
279 *(int *)&eerev.res[0] = 0;
280 sromSYM[20] = eerev.etheraddr[0];
281 sromSYM[21] = eerev.etheraddr[1];
282 sromSYM[22] = eerev.etheraddr[2];
283 sromSYM[23] = eerev.etheraddr[3];
284 sromSYM[24] = eerev.etheraddr[4];
285 sromSYM[25] = eerev.etheraddr[5];
286 printf("\nSRom: Writing DEC21143 SYM info .. ");
287
288 if (dc_srom_store ((u_short *)sromSYM) == -1)
289 printf("FAILED\n");
290 else
291 printf("OK\n");
292 }
293
294 /* update CRC */
295 eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size);
296
297 /* write new values */
298 printf("\nSRom: Writing revision info ...... ");
299 if (el_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev,
300 sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
301 printf("FAILED\n\n");
302 else
303 printf("OK\n\n");
304
305 /* write new values as shadow image to nvram */
6d0f6bcf 306 nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE);
e69b4b8f
WD		 307
308 } /*if (initSrom) */
309
310 /* copy current values as shadow image to nvram */
311 if (initSrom == 0 && copyNv == 1)
6d0f6bcf 312 nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE);
e69b4b8f
WD		 313
314 /* update environment */
315 sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
8bde7f77
WD		 316 eerev.etheraddr[0], eerev.etheraddr[1],
317 eerev.etheraddr[2], eerev.etheraddr[3],
318 eerev.etheraddr[4], eerev.etheraddr[5]);
e69b4b8f
WD		 319 setenv ("ethaddr", buf);
320
321 /* print actual board identification */
322 printf("Ident: %s Ser %s Rev %c%c\n",
8bde7f77
WD		 323 eerev.board, (char *)&eerev.serial,
324 eerev.revision[0][0], eerev.revision[0][1]);
e69b4b8f
WD		 325
326 /* global board ident */
327 if (strstr ((char *)&eerev.board, "75") != NULL)
8bde7f77 328 eltec_board = 750;
e69b4b8f 329 else
8bde7f77 330 eltec_board = 740;
e69b4b8f
WD		 331
332 /*
333 * L2 cache configuration
334 */
6d0f6bcf 335#if defined(CONFIG_SYS_L2_BAB7xx)
e69b4b8f
WD		 336 ptr = getenv("l2cache");
337 if (*ptr == '0')
338 {
8bde7f77 339 printf ("Cache: L2 NOT activated on BAB%d\n", eltec_board);
e69b4b8f
WD		 340 }
341 else
342 {
8bde7f77
WD		 343 printf ("Cache: L2 activated on BAB%d\n", eltec_board);
344 l2_cache_enable(*(int*)&eerev.res[0]);
e69b4b8f
WD		 345 }
346#endif
347
348 /*
349 * Reconfig ata reset timeout from environment
350 */
351 if ((ptr = getenv ("ata_reset_time")) != NULL)
352 {
8bde7f77 353 ata_reset_time = (int)simple_strtoul (ptr, NULL, 10);
e69b4b8f
WD		 354 }
355 else
356 {
8bde7f77
WD		 357 sprintf (buf, "%d", ata_reset_time);
358 setenv ("ata_reset_time", buf);
e69b4b8f
WD		 359 }
360
361 /*
362 * Reconfig scsi reset timeout from environment
363 */
364 if ((ptr = getenv ("scsi_reset_time")) != NULL)
365 {
8bde7f77 366 scsi_reset_time = (int)simple_strtoul (ptr, NULL, 10);
e69b4b8f
WD		 367 }
368 else
369 {
8bde7f77
WD		 370 sprintf (buf, "%d", scsi_reset_time);
371 setenv ("scsi_reset_time", buf);
e69b4b8f
WD		 372 }
373
374
375 if ((bdf = pci_find_device(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, 0)) > 0)
376 {
8bde7f77
WD		 377 if (pci_find_device(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, 0) > 0)
378 {
8ed44d91 379 /* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 MHz */
8bde7f77
WD		 380 scsi_dev_id = PCI_DEVICE_ID_NCR_53C860;
381 scsi_max_scsi_id = 7;
382 scsi_sym53c8xx_ccf = 0x15;
383 pci_write_config_byte (bdf, WINBOND_IDEIRCR, 0xb0);
384 }
385
386 if ((ptr = getenv ("ide_dma_off")) != NULL)
387 {
388 u_long dma_off = simple_strtoul (ptr, NULL, 10);
389 /*
390 * setup user defined registers
391 * s.a. linux/drivers/ide/sl82c105.c
392 */
393 bdf |= PCI_BDF(0,0,1); /* ide user reg at bdf function 1 */
394 if (dma_off & 1)
395 {
396 pci_write_config_byte (bdf, 0x46, 1);
397 printf("IDE: DMA off flag set: Bus 0 : Dev 0\n");
398 }
399 if (dma_off & 2)
400 {
401 pci_write_config_byte (bdf, 0x4a, 1);
402 printf("IDE: DMA off flag set: Bus 0 : Dev 1\n");
403 }
404 if (dma_off & 4)
405 {
406 pci_write_config_byte (bdf, 0x4e, 1);
407 printf("IDE: DMA off flag set: Bus 1 : Dev 0\n");
408 }
409 if (dma_off & 8)
410 {
411 pci_write_config_byte (bdf, 0x52, 1);
412 printf("IDE: DMA off flag set: Bus 1 : Dev 1\n");
413 }
414 }
e69b4b8f
WD		 415 }
416 return (0);
417}
418
419/*----------------------------------------------------------------------------*/
420/*
421 * BAB740 uses KENDIN KS8761 modem chip with not common setup values
422 */
423#ifdef CONFIG_TULIP_SELECT_MEDIA
424
425/* Register bits.
426 */
427#define BMR_SWR 0x00000001 /* Software Reset */
428#define STS_TS 0x00700000 /* Transmit Process State */
429#define STS_RS 0x000e0000 /* Receive Process State */
430#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
431#define OMR_SR 0x00000002 /* Start/Stop Receive */
432#define OMR_PS 0x00040000 /* Port Select */
433#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
434#define OMR_PM 0x00000080 /* Pass All Multicast */
435#define OMR_PR 0x00000040 /* Promiscuous Mode */
436#define OMR_PCS 0x00800000 /* PCS Function */
437#define OMR_TTM 0x00400000 /* Transmit Threshold Mode */
438
439/* Ethernet chip registers.
440 */
441#define DE4X5_BMR 0x000 /* Bus Mode Register */
442#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
443#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
444#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
445#define DE4X5_STS 0x028 /* Status Register */
446#define DE4X5_OMR 0x030 /* Operation Mode Register */
447#define DE4X5_SISR 0x060 /* SIA Status Register */
448#define DE4X5_SICR 0x068 /* SIA Connectivity Register */
449#define DE4X5_TXRX 0x070 /* SIA Transmit and Receive Register */
450#define DE4X5_GPPR 0x078 /* General Purpose Port register */
451#define DE4X5_APROM 0x048 /* Ethernet Address PROM */
452
453/*----------------------------------------------------------------------------*/
454
455static int INL(struct eth_device* dev, u_long addr)
456{
457 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
458}
459
460/*----------------------------------------------------------------------------*/
461
462static void OUTL(struct eth_device* dev, int command, u_long addr)
463{
464 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
465}
466
467/*----------------------------------------------------------------------------*/
468
469static void media_reg_init (
470 struct eth_device* dev,
471 u32 csr14,
472 u32 csr15_dir,
473 u32 csr15_v0,
474 u32 csr15_v1,
475 u32 csr6 )
476{
477 OUTL(dev, 0, DE4X5_OMR); /* CSR6 */
478 udelay(10 * 1000);
479 OUTL(dev, 0, DE4X5_SICR); /* CSR13 */
480 OUTL(dev, 1, DE4X5_SICR); /* CSR13 */
481 udelay(10 * 1000);
482 OUTL(dev, csr14, DE4X5_TXRX); /* CSR14 */
483 OUTL(dev, csr15_dir, DE4X5_GPPR); /* CSR15 */
484 OUTL(dev, csr15_v0, DE4X5_GPPR); /* CSR15 */
485 udelay(10 * 1000);
486 OUTL(dev, csr15_v1, DE4X5_GPPR); /* CSR15 */
487 OUTL(dev, 0x00000301, DE4X5_SISR); /* CSR12 */
488 OUTL(dev, csr6, DE4X5_OMR); /* CSR6 */
489}
490
491/*----------------------------------------------------------------------------*/
492
493void dc21x4x_select_media(struct eth_device* dev)
494{
495 int i, status, ext;
496 extern unsigned int eltec_board;
497
498 if (eltec_board == 740)
499 {
8bde7f77
WD		 500 printf("SYM media select "); /* BAB740 */
501 /* start autoneg. with 10 mbit */
502 media_reg_init (dev, 0x3ffff, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400080);
503 ext = status = 0;
504 for (i=0; i<2000+ext; i++)
505 {
506 status = INL(dev, DE4X5_SISR);
507 udelay(1000);
508 if (status & 0x2000) ext = 2000;
509 if ((status & 0x7000) == 0x5000) break;
510 }
511
512 /* autoneg. ok -> 100MB FD */
513 if ((status & 0x0100f000) == 0x0100d000)
514 {
515 media_reg_init (dev, 0x37f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40280);
516 printf("100baseTx-FD\n");
517 }
518 /* autoneg. ok -> 100MB HD */
519 else if ((status & 0x0080f000) == 0x0080d000)
520 {
521 media_reg_init (dev, 0x17f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40080);
522 printf("100baseTx\n");
523 }
524 /* autoneg. ok -> 10MB FD */
525 else if ((status & 0x0040f000) == 0x0040d000)
526 {
527 media_reg_init (dev, 0x07f7f, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400280);
528 printf("10baseT-FD\n");
529 }
530 /* autoneg. fail -> 10MB HD */
531 else
532 {
533 media_reg_init (dev, 0x7f7f, 0x08af0008, 0x00a10008, 0x00a50008,
534 (OMR_SDP | OMR_TTM | OMR_PM));
535 printf("10baseT\n");
536 }
e69b4b8f
WD		 537 }
538 else
539 {
8bde7f77
WD		 540 printf("MII media selected\n"); /* BAB750 */
541 OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); /* CSR6 */
e69b4b8f
WD		 542 }
543}
544#endif /* CONFIG_TULIP_SELECT_MEDIA */
545
546/*---------------------------------------------------------------------------*/
Empty description
This page took 0.222467 seconds and 4 git commands to generate.