[u-boot.git] / arch / arm / mach-omap2 / omap3 / board.c

/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <[email protected]>
 *      Shashi Ranjan <[email protected]>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <[email protected]>
 *      Syed Mohammed Khasim <[email protected]>
 *
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <dm.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/gpio.h>
#include <asm/omap_common.h>
#include <linux/compiler.h>

DECLARE_GLOBAL_DATA_PTR;

/* Declarations */
extern omap3_sysinfo sysinfo;
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
#endif

#ifdef CONFIG_DM_GPIO
static const struct omap_gpio_platdata omap34xx_gpio[] = {
	{ 0, OMAP34XX_GPIO1_BASE },
	{ 1, OMAP34XX_GPIO2_BASE },
	{ 2, OMAP34XX_GPIO3_BASE },
	{ 3, OMAP34XX_GPIO4_BASE },
	{ 4, OMAP34XX_GPIO5_BASE },
	{ 5, OMAP34XX_GPIO6_BASE },
};

U_BOOT_DEVICES(omap34xx_gpios) = {
	{ "gpio_omap", &omap34xx_gpio[0] },
	{ "gpio_omap", &omap34xx_gpio[1] },
	{ "gpio_omap", &omap34xx_gpio[2] },
	{ "gpio_omap", &omap34xx_gpio[3] },
	{ "gpio_omap", &omap34xx_gpio[4] },
	{ "gpio_omap", &omap34xx_gpio[5] },
};

#else

static const struct gpio_bank gpio_bank_34xx[6] = {
	{ (void *)OMAP34XX_GPIO1_BASE },
	{ (void *)OMAP34XX_GPIO2_BASE },
	{ (void *)OMAP34XX_GPIO3_BASE },
	{ (void *)OMAP34XX_GPIO4_BASE },
	{ (void *)OMAP34XX_GPIO5_BASE },
	{ (void *)OMAP34XX_GPIO6_BASE },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;

#endif

/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit(void)
{
	unsigned long i;

	/* configure non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory(void)
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

void early_system_init(void)
{
	hw_data_init();
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	watchdog_init();
	early_system_init();

	try_unlock_memory();

#ifndef CONFIG_SYS_L2CACHE_OFF
	/* Invalidate L2-cache from secure mode */
	omap3_invalidate_l2_cache_secure();
#endif

	set_muxconf_regs();
	sdelay(100);

	prcm_init();

	per_clocks_enable();

#ifdef CONFIG_USB_EHCI_OMAP
	ehci_clocks_enable();
#endif
}

#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
	early_system_init();
	mem_init();
}
#endif

/*
 * Routine: misc_init_r
 * Description: A basic misc_init_r that just displays the die ID
 */
int __weak misc_init_r(void)
{
	omap_die_id_display();

	return 0;
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
static void wait_for_command_complete(struct watchdog *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	setbits_le32(&prcm_base->fclken_wkup, 0x20);
	setbits_le32(&prcm_base->iclken_wkup, 0x20);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	int hw, strength = 1;

	if (argc < 2 || argc > 3)
		goto usage;

	if (strncmp(argv[1], "hw", 2) == 0) {
		hw = 1;
		if (argc == 3) {
			if (strncmp(argv[2], "bch8", 4) == 0)
				strength = 8;
			else if (strncmp(argv[2], "bch16", 5) == 0)
				strength = 16;
			else if (strncmp(argv[2], "hamming", 7) != 0)
				goto usage;
		}
	} else if (strncmp(argv[1], "sw", 2) == 0) {
		hw = 0;
		if (argc == 3) {
			if (strncmp(argv[2], "bch8", 4) == 0)
				strength = 8;
			else if (strncmp(argv[2], "hamming", 7) != 0)
				goto usage;
		}
	} else {
		goto usage;
	}

	return -omap_nand_switch_ecc(hw, strength);

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 3, 1,	do_switch_ecc,
	"switch OMAP3 NAND ECC calculation algorithm",
	"hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
	" and 8-bit/16-bit BCH\n"
	"                           ecc calculation (second parameter may"
	" be omitted).\n"
	"nandecc sw               - Switch to NAND software ecc algorithm."
);

#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */

static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
{
	u32 i, num_params = *parameters;
	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;

	/*
	 * copy the parameters to an un-cached area to avoid coherency
	 * issues
	 */
	for (i = 0; i < num_params; i++) {
		__raw_writel(*parameters, sram_scratch_space);
		parameters++;
		sram_scratch_space++;
	}

	/* Now make the PPA call */
	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}

void __weak omap3_set_aux_cr_secure(u32 acr)
{
	struct emu_hal_params emu_romcode_params;

	emu_romcode_params.num_params = 1;
	emu_romcode_params.param1 = acr;
	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
			       (u32 *)&emu_romcode_params);
}

void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
				 u32 cpu_rev_comb, u32 cpu_variant,
				 u32 cpu_rev)
{
	if (get_device_type() == GP_DEVICE)
		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);

	/* L2 Cache Auxiliary Control Register is not banked */
}

void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
			  u32 cpu_variant, u32 cpu_rev)
{
	/* Write ACR - affects secure banked bits */
	if (get_device_type() == GP_DEVICE)
		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
	else
		omap3_set_aux_cr_secure(acr);

	/* Write ACR - affects non-secure banked bits - some erratas need it */
	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}


#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;
	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);

}

/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
	if (get_device_type() == GP_DEVICE) {
		omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = 0;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
				       (u32 *)&emu_romcode_params);
	}
}

void v7_outer_cache_enable(void)
{

	/*
	 * Set L2EN
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in setting both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0x2, 0);
}

void omap3_outer_cache_disable(void)
{
	/*
	 * Clear L2EN
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in clearing both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0, 0x2);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
Commit	Line	Data
91eee546 DB	1	/*
	2	*
	3	* Common board functions for OMAP3 based boards.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Sunil Kumar <[email protected]>
	10	* Shashi Ranjan <[email protected]>
	11	*
	12	* Derived from Beagle Board and 3430 SDP code by
	13	* Richard Woodruff <[email protected]>
	14	* Syed Mohammed Khasim <[email protected]>
	15	*
	16	*
1a459660	17	* SPDX-License-Identifier: GPL-2.0+
91eee546 DB	18	*/
91eee546 DB	19	#include <common.h>
b3f4ca11	20	#include <dm.h>
47f7bcae	21	#include <spl.h>
91eee546 DB	22	#include <asm/io.h>
	23	#include <asm/arch/sys_proto.h>
	24	#include <asm/arch/mem.h>
06e758e7	25	#include <asm/cache.h>
45bf0585	26	#include <asm/armv7.h>
b3f4ca11	27	#include <asm/gpio.h>
bb085b87	28	#include <asm/omap_common.h>
8a87a3d7	29	#include <linux/compiler.h>
91eee546	30
6507f133 TR	31	DECLARE_GLOBAL_DATA_PTR;
6507f133 TR	32
45bf0585	33	/* Declarations */
91eee546	34	extern omap3_sysinfo sysinfo;
57f588be	35	#ifndef CONFIG_SYS_L2CACHE_OFF
45bf0585	36	static void omap3_invalidate_l2_cache_secure(void);
57f588be	37	#endif
91eee546	38
b3f4ca11 SG	39	#ifdef CONFIG_DM_GPIO
b3f4ca11 SG	40	static const struct omap_gpio_platdata omap34xx_gpio[] = {
0a9e3405 TR	41	{ 0, OMAP34XX_GPIO1_BASE },
	42	{ 1, OMAP34XX_GPIO2_BASE },
	43	{ 2, OMAP34XX_GPIO3_BASE },
	44	{ 3, OMAP34XX_GPIO4_BASE },
	45	{ 4, OMAP34XX_GPIO5_BASE },
	46	{ 5, OMAP34XX_GPIO6_BASE },
b3f4ca11 SG	47	};
b3f4ca11 SG	48
44913aa5	49	U_BOOT_DEVICES(omap34xx_gpios) = {
b3f4ca11 SG	50	{ "gpio_omap", &omap34xx_gpio[0] },
	51	{ "gpio_omap", &omap34xx_gpio[1] },
	52	{ "gpio_omap", &omap34xx_gpio[2] },
	53	{ "gpio_omap", &omap34xx_gpio[3] },
	54	{ "gpio_omap", &omap34xx_gpio[4] },
	55	{ "gpio_omap", &omap34xx_gpio[5] },
	56	};
	57
	58	#else
	59
25223a68	60	static const struct gpio_bank gpio_bank_34xx[6] = {
0a9e3405 TR	61	{ (void *)OMAP34XX_GPIO1_BASE },
	62	{ (void *)OMAP34XX_GPIO2_BASE },
	63	{ (void *)OMAP34XX_GPIO3_BASE },
	64	{ (void *)OMAP34XX_GPIO4_BASE },
	65	{ (void *)OMAP34XX_GPIO5_BASE },
	66	{ (void *)OMAP34XX_GPIO6_BASE },
25223a68 A	67	};
	68
	69	const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
	70
b3f4ca11 SG	71	#endif
b3f4ca11 SG	72
91eee546 DB	73	/******************************************************************************
	74	* Routine: secure_unlock
	75	* Description: Setup security registers for access
	76	* (GP Device only)
	77	*****************************************************************************/
	78	void secure_unlock_mem(void)
	79	{
97a099ea DB	80	struct pm pm_rt_ape_base = (struct pm )PM_RT_APE_BASE_ADDR_ARM;
	81	struct pm pm_gpmc_base = (struct pm )PM_GPMC_BASE_ADDR_ARM;
	82	struct pm pm_ocm_ram_base = (struct pm )PM_OCM_RAM_BASE_ADDR_ARM;
	83	struct pm pm_iva2_base = (struct pm )PM_IVA2_BASE_ADDR_ARM;
	84	struct sms sms_base = (struct sms )OMAP34XX_SMS_BASE;
91eee546 DB	85
	86	/* Protection Module Register Target APE (PM_RT) */
	87	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	88	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	89	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	90	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	91
	92	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	93	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	94	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	95
	96	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	97	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	98	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	99	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	100
	101	/* IVA Changes */
	102	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	103	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	104	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	105
	106	/* SDRC region 0 public */
	107	writel(UNLOCK_1, &sms_base->rg_att0);
	108	}
	109
	110	/******************************************************************************
	111	* Routine: secureworld_exit()
	112	* Description: If chip is EMU and boot type is external
	113	* configure secure registers and exit secure world
	114	* general use.
	115	*****************************************************************************/
fd3f401b	116	void secureworld_exit(void)
91eee546 DB	117	{
	118	unsigned long i;
	119
a4958313	120	/* configure non-secure access control register */
91eee546 DB	121	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	122	/* enabling co-processor CP10 and CP11 accesses in NS world */
	123	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	124	/*
	125	* allow allocation of locked TLBs and L2 lines in NS world
	126	* allow use of PLE registers in NS world also
	127	*/
	128	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	129	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
	130
	131	/* Enable ASA in ACR register */
	132	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	133	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	134	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	135
	136	/* Exiting secure world */
	137	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	138	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	139	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
	140	}
	141
91eee546 DB	142	/******************************************************************************
	143	* Routine: try_unlock_sram()
	144	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
	145	* general use.
	146	*****************************************************************************/
fd3f401b	147	void try_unlock_memory(void)
91eee546 DB	148	{
	149	int mode;
	150	int in_sdram = is_running_in_sdram();
	151
	152	/*
	153	* if GP device unlock device SRAM for general use
	154	* secure code breaks for Secure/Emulation device - HS/E/T
	155	*/
	156	mode = get_device_type();
	157	if (mode == GP_DEVICE)
	158	secure_unlock_mem();
	159
	160	/*
	161	* If device is EMU and boot is XIP external booting
	162	* Unlock firewalls and disable L2 and put chip
	163	* out of secure world
	164	*
	165	* Assuming memories are unlocked by the demon who put us in SDRAM
	166	*/
	167	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	168	&& (!in_sdram)) {
	169	secure_unlock_mem();
	170	secureworld_exit();
	171	}
	172
	173	return;
	174	}
	175
00bbe96e SP	176	void early_system_init(void)
	177	{
	178	hw_data_init();
	179	}
	180
91eee546 DB	181	/******************************************************************************
	182	* Routine: s_init
	183	* Description: Does early system init of muxing and clocks.
	184	* - Called path is with SRAM stack.
	185	*****************************************************************************/
	186	void s_init(void)
	187	{
91eee546	188	watchdog_init();
00bbe96e	189	early_system_init();
91eee546 DB	190
	191	try_unlock_memory();
	192
45bf0585 A	193	#ifndef CONFIG_SYS_L2CACHE_OFF
	194	/* Invalidate L2-cache from secure mode */
	195	omap3_invalidate_l2_cache_secure();
91eee546	196	#endif
91eee546 DB	197
91eee546 DB	198	set_muxconf_regs();
86623add	199	sdelay(100);
91eee546 DB	200
	201	prcm_init();
	202
	203	per_clocks_enable();
	204
95f87910 G	205	#ifdef CONFIG_USB_EHCI_OMAP
	206	ehci_clocks_enable();
	207	#endif
7ae8350f	208	}
95f87910	209
7ae8350f SG	210	#ifdef CONFIG_SPL_BUILD
	211	void board_init_f(ulong dummy)
	212	{
00bbe96e	213	early_system_init();
7ae8350f	214	mem_init();
91eee546	215	}
7ae8350f	216	#endif
91eee546	217
8a87a3d7 TR	218	/*
	219	* Routine: misc_init_r
	220	* Description: A basic misc_init_r that just displays the die ID
	221	*/
	222	int __weak misc_init_r(void)
	223	{
679f82c3	224	omap_die_id_display();
8a87a3d7 TR	225
	226	return 0;
	227	}
	228
91eee546 DB	229	/******************************************************************************
	230	* Routine: wait_for_command_complete
	231	* Description: Wait for posting to finish on watchdog
	232	*****************************************************************************/
98431d58	233	static void wait_for_command_complete(struct watchdog *wd_base)
91eee546 DB	234	{
	235	int pending = 1;
	236	do {
	237	pending = readl(&wd_base->wwps);
	238	} while (pending);
	239	}
	240
	241	/******************************************************************************
	242	* Routine: watchdog_init
	243	* Description: Shut down watch dogs
	244	*****************************************************************************/
	245	void watchdog_init(void)
	246	{
97a099ea DB	247	struct watchdog wd2_base = (struct watchdog )WD2_BASE;
97a099ea DB	248	struct prcm prcm_base = (struct prcm )PRCM_BASE;
91eee546 DB	249
	250	/*
	251	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	252	* either taken care of by ROM (HS/EMU) or not accessible (GP).
	253	* We need to take care of WD2-MPU or take a PRCM reset. WD3
	254	* should not be running and does not generate a PRCM reset.
	255	*/
	256
e7300f46 WD	257	setbits_le32(&prcm_base->fclken_wkup, 0x20);
e7300f46 WD	258	setbits_le32(&prcm_base->iclken_wkup, 0x20);
91eee546 DB	259	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
	260
	261	writel(WD_UNLOCK1, &wd2_base->wspr);
	262	wait_for_command_complete(wd2_base);
	263	writel(WD_UNLOCK2, &wd2_base->wspr);
	264	}
	265
91eee546 DB	266	/******************************************************************************
	267	* Dummy function to handle errors for EABI incompatibility
	268	*****************************************************************************/
	269	void abort(void)
	270	{
	271	}
	272
bb085b87	273	#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
91eee546 DB	274	/******************************************************************************
	275	* OMAP3 specific command to switch between NAND HW and SW ecc
	276	*****************************************************************************/
54841ab5	277	static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
91eee546	278	{
50075153 LM	279	int hw, strength = 1;
50075153 LM	280
da634ae3	281	if (argc < 2 \|\| argc > 3)
91eee546	282	goto usage;
da634ae3 AB	283
da634ae3 AB	284	if (strncmp(argv[1], "hw", 2) == 0) {
50075153 LM	285	hw = 1;
	286	if (argc == 3) {
	287	if (strncmp(argv[2], "bch8", 4) == 0)
	288	strength = 8;
3a504d96	289	else if (strncmp(argv[2], "bch16", 5) == 0)
50075153 LM	290	strength = 16;
50075153 LM	291	else if (strncmp(argv[2], "hamming", 7) != 0)
da634ae3 AB	292	goto usage;
	293	}
	294	} else if (strncmp(argv[1], "sw", 2) == 0) {
50075153 LM	295	hw = 0;
	296	if (argc == 3) {
	297	if (strncmp(argv[2], "bch8", 4) == 0)
	298	strength = 8;
	299	else if (strncmp(argv[2], "hamming", 7) != 0)
b050898e AC	300	goto usage;
b050898e AC	301	}
da634ae3	302	} else {
91eee546	303	goto usage;
da634ae3	304	}
91eee546	305
50075153	306	return -omap_nand_switch_ecc(hw, strength);
91eee546 DB	307
91eee546 DB	308	usage:
36003268	309	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	310	return 1;
	311	}
	312
	313	U_BOOT_CMD(
da634ae3	314	nandecc, 3, 1, do_switch_ecc,
a93c92cd	315	"switch OMAP3 NAND ECC calculation algorithm",
3a504d96 HS	316	"hw [hamming\|bch8\|bch16] - Switch between NAND hardware 1-bit hamming"
3a504d96 HS	317	" and 8-bit/16-bit BCH\n"
da634ae3 AB	318	" ecc calculation (second parameter may"
	319	" be omitted).\n"
	320	"nandecc sw - Switch to NAND software ecc algorithm."
a89c33db	321	);
91eee546	322
bb085b87	323	#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
6a6b62e3 SP	324
	325	#ifdef CONFIG_DISPLAY_BOARDINFO
	326	/**
	327	* Print board information
	328	*/
	329	int checkboard (void)
	330	{
	331	char *mem_s ;
	332
	333	if (is_mem_sdr())
	334	mem_s = "mSDR";
	335	else
	336	mem_s = "LPDDR";
	337
	338	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	339	sysinfo.nand_string);
	340
	341	return 0;
	342	}
	343	#endif /* CONFIG_DISPLAY_BOARDINFO */
45bf0585 A	344
	345	static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
	346	{
	347	u32 i, num_params = *parameters;
	348	u32 sram_scratch_space = (u32 )OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
	349
	350	/*
	351	* copy the parameters to an un-cached area to avoid coherency
	352	* issues
	353	*/
	354	for (i = 0; i < num_params; i++) {
	355	__raw_writel(*parameters, sram_scratch_space);
	356	parameters++;
	357	sram_scratch_space++;
	358	}
	359
	360	/* Now make the PPA call */
	361	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
	362	}
	363
cdef0b3f	364	void __weak omap3_set_aux_cr_secure(u32 acr)
45bf0585	365	{
cdef0b3f NM	366	struct emu_hal_params emu_romcode_params;
	367
	368	emu_romcode_params.num_params = 1;
	369	emu_romcode_params.param1 = acr;
	370	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	371	(u32 *)&emu_romcode_params);
45bf0585 A	372	}
45bf0585 A	373
19a75b8c SS	374	void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
	375	u32 cpu_rev_comb, u32 cpu_variant,
	376	u32 cpu_rev)
	377	{
	378	if (get_device_type() == GP_DEVICE)
	379	omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
	380
	381	/* L2 Cache Auxiliary Control Register is not banked */
	382	}
	383
cdef0b3f NM	384	void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
cdef0b3f NM	385	u32 cpu_variant, u32 cpu_rev)
45bf0585	386	{
cdef0b3f NM	387	/* Write ACR - affects secure banked bits */
	388	if (get_device_type() == GP_DEVICE)
	389	omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
	390	else
	391	omap3_set_aux_cr_secure(acr);
c6f90e14	392
cdef0b3f NM	393	/* Write ACR - affects non-secure banked bits - some erratas need it */
cdef0b3f NM	394	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
45bf0585 A	395	}
45bf0585 A	396
cdef0b3f	397
45bf0585	398	#ifndef CONFIG_SYS_L2CACHE_OFF
57f588be TR	399	static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
	400	{
	401	u32 acr;
	402
	403	/* Read ACR */
	404	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	405	acr &= ~clear_bits;
	406	acr \|= set_bits;
cdef0b3f	407	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
57f588be	408
57f588be TR	409	}
57f588be TR	410
45bf0585 A	411	/* Invalidate the entire L2 cache from secure mode */
	412	static void omap3_invalidate_l2_cache_secure(void)
	413	{
	414	if (get_device_type() == GP_DEVICE) {
49ec9490	415	omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
45bf0585 A	416	} else {
	417	struct emu_hal_params emu_romcode_params;
	418	emu_romcode_params.num_params = 1;
	419	emu_romcode_params.param1 = 0;
	420	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
	421	(u32 *)&emu_romcode_params);
	422	}
	423	}
	424
	425	void v7_outer_cache_enable(void)
	426	{
45bf0585 A	427
45bf0585 A	428	/*
cdef0b3f	429	* Set L2EN
45bf0585 A	430	* On some revisions L2EN bit is banked on some revisions it's not
	431	* No harm in setting both banked bits(in fact this is required
	432	* by an erratum)
	433	*/
	434	omap3_update_aux_cr(0x2, 0);
	435	}
	436
f1f2c3ca	437	void omap3_outer_cache_disable(void)
45bf0585	438	{
45bf0585	439	/*
cdef0b3f	440	* Clear L2EN
45bf0585 A	441	* On some revisions L2EN bit is banked on some revisions it's not
	442	* No harm in clearing both banked bits(in fact this is required
	443	* by an erratum)
	444	*/
	445	omap3_update_aux_cr(0, 0x2);
	446	}
e3fe6257	447	#endif /* !CONFIG_SYS_L2CACHE_OFF */