From 78cedfabd53b6f64e7e64fc84878d848e5df1d08 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 14 Feb 2020 11:46:40 -0800 Subject: [PATCH] target/arm: Flush high bits of sve register after AdvSIMD EXT Writes to AdvSIMD registers flush the bits above 128. Buglink: https://bugs.launchpad.net/bugs/1863247 Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7c26c3bfeb..620a429067 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6895,6 +6895,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_resl); write_vec_element(s, tcg_resh, rd, 1, MO_64); tcg_temp_free_i64(tcg_resh); + clear_vec_high(s, true, rd); } /* TBL/TBX -- 2.42.0