dataplane: endianness-aware accesses

dataplane: endianness-aware accesses

The vring.c code currently assumes that guest and host endianness match,
which is not true for a number of cases:

- emulating targets with a different endianness than the host
- bi-endian targets, where the correct endianness depends on the virtio
  device
- upcoming support for the virtio-1 standard mandates little-endian
  accesses even for big-endian targets and hosts

Make sure to use accessors that depend on the virtio device.

Note that dataplane now needs to be built per-target.

Cc: Stefan Hajnoczi <[email protected]>
Cc: Paolo Bonzini <[email protected]>
Cc: Fam Zheng <[email protected]>
Reviewed-by: David Gibson <[email protected]>
Tested-by: David Gibson <[email protected]>
Signed-off-by: Cornelia Huck <[email protected]>
Reviewed-by: Stefan Hajnoczi <[email protected]>
Message-id: 1422289602[email protected]
Signed-off-by: Stefan Hajnoczi <[email protected]>