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target/mips: Introduce 32 R5900 multimedia registers
authorFredrik Noring <[email protected]>
Thu, 17 Jan 2019 17:44:05 +0000 (18:44 +0100)
committerAleksandar Markovic <[email protected]>
Fri, 18 Jan 2019 15:53:28 +0000 (16:53 +0100)
commita168a796e1c251787fcdf2d9ca1e9e69cb86ffcd
tree3ce5635f8ee58d3e45ee71d21c1c325d62a7020btree | snapshot
parent294fc2ea7f8af913523bf004433704377d9ee7a8commit | diff
target/mips: Introduce 32 R5900 multimedia registers

The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.

Reviewed-by: Aleksandar Markovic <[email protected]>
Signed-off-by: Fredrik Noring <[email protected]>
Signed-off-by: Aleksandar Markovic <[email protected]>
target/mips/cpu.h diff | blob | blame | history
target/mips/translate.c diff | blob | blame | history
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