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target-mips: implement R6 multi-threading
authorYongbok Kim <[email protected]>
Wed, 3 Feb 2016 12:31:07 +0000 (12:31 +0000)
committerLeon Alrae <[email protected]>
Fri, 26 Feb 2016 08:59:17 +0000 (08:59 +0000)
commit01bc435b44b8802cc4697faa07d908684afbce4e
treeeb377fa81c980fba2f2c08941e43ba526d395041tree | snapshot
parentbee62662a312b99b4418b558a99b3963a4cbff07commit | diff
target-mips: implement R6 multi-threading

MIPS Release 6 provides multi-threading features which replace
pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new
CP0.Config5.VP (Virtual Processor) bit which indicates presence of
multi-threading support which includes CP0.GlobalNumber register and
DVP/EVP instructions.

Signed-off-by: Yongbok Kim <[email protected]>
Signed-off-by: Leon Alrae <[email protected]>
disas/mips.c diff | blob | blame | history
target-mips/cpu.c diff | blob | blame | history
target-mips/cpu.h diff | blob | blame | history
target-mips/helper.h diff | blob | blame | history
target-mips/op_helper.c diff | blob | blame | history
target-mips/translate.c diff | blob | blame | history
target-mips/translate_init.c diff | blob | blame | history
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