Gerd Hoffmann [Mon, 16 Dec 2013 09:11:28 +0000 (10:11 +0100)]
piix: gigabyte alignment for ram
Map 3G (i440fx) of memory below 4G, so the RAM pieces
are nicely aligned to gigabyte borders.
Keep old memory layout for (a) old machine types and (b) in case all
memory fits below 4G and thus we don't have to split RAM into pieces
in the first place. The later makes sure this change doesn't take
away memory from 32bit guests.
So, with i440fx and up to 3.5 GB of memory, all of it will be mapped
below 4G. With more than 3.5 GB of memory 3 GB will be mapped below
4G and the remaining amount will be mapped above 4G.
Alexander Graf [Fri, 20 Dec 2013 10:01:50 +0000 (11:01 +0100)]
PPC: Fix compilation with TCG debug
The recent VSX patches broken compilation of QEMU when configurated
with --enable-debug, as it was treating "target long" TCG variables
as "i64" which is not true for 32bit targets.
This patch fixes all the places that the compiler has found to use
the correct variable type and if necessary manually cast.
Aurelien Jarno [Sat, 21 Dec 2013 15:46:07 +0000 (16:46 +0100)]
Merge tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu
Patch queue for s390 - 2013-12-18
This covers mostly minor bug fixes and implements the SIGP START
hypercall which allows to start a remote CPU without changing its
state.
Cornelia Huck (1):
s390x/kvm: Fix diagnose handling.
Thomas Huth (7):
s390x/kvm: Removed duplicated SIGP defines
s390x/kvm: Removed s390_store_status stub
s390x/kvm: Fix coding style in handle_sigp()
s390x/kvm: Implemented SIGP START
s390x/kvm: Simplified the calculation of the SIGP order code
s390x/kvm: Fixed condition code for unknown SIGP orders
s390x/ioinst: CHSC has to set a condition code
* tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu:
s390x/ioinst: CHSC has to set a condition code
s390x/kvm: Fixed condition code for unknown SIGP orders
s390x/kvm: Simplified the calculation of the SIGP order code
s390x/kvm: Implemented SIGP START
s390x/kvm: Fix coding style in handle_sigp()
s390x/kvm: Removed s390_store_status stub
s390x/kvm: Removed duplicated SIGP defines
s390x/kvm: Fix diagnose handling.
Anthony Liguori [Fri, 20 Dec 2013 01:03:17 +0000 (17:03 -0800)]
Merge remote-tracking branch 'agraf/tags/signed-ppc-for-upstream' into staging
Patch queue for ppc - 2013-12-20
Alexander Graf (3):
PPC: Use default pci bus name for grackle and heathrow
roms: Flush icache when writing roms to guest memory
PPC: Add VSX to hflags
Alexey Kardashevskiy (5):
powerpc: add PVR mask support
target-ppc: move POWER7+ to a separate family
spapr-rtas: replace return code constants with macros
spapr-rtas: add ibm, (get|set)-system-parameter
spapr: make sure RMA is in first mode of first memory node
Greg Kurz (1):
target-ppc: add stubs for KVM breakpoints
Paolo Bonzini (1):
spapr: tie spapr-nvram to -pflash
Paul Mackerras (1):
spapr: limit numa memory regions by ram size
* agraf/tags/signed-ppc-for-upstream: (32 commits)
spapr: limit numa memory regions by ram size
spapr: make sure RMA is in first mode of first memory node
device_tree: qemu_fdt_setprop: Rename val_array arg
device_tree: s/qemu_devtree/qemu_fdt globally
PPC: Add VSX to hflags
Add xxsldwi
Add xxspltw
Add xxsel
Add xxmrgh/xxmrgl
Add Power7 VSX Logical Instructions
Add VSX Vector Move Instructions
Add VSX Scalar Move Instructions
roms: Flush icache when writing roms to guest memory
spapr: tie spapr-nvram to -pflash
PPC: Use default pci bus name for grackle and heathrow
spapr-rtas: add ibm, (get|set)-system-parameter
spapr-rtas: replace return code constants with macros
target-ppc: move POWER7+ to a separate family
Add stxvw4x
Add stxsdx
...
spapr: make sure RMA is in first mode of first memory node
The SPAPR specification says that the RMA starts at the LPAR's logical
address 0 and is the first logical memory block reported in
the LPAR’s device tree.
So SLOF only maps the first block and that block needs to span
the full RMA.
This makes sure that the RMA area is where SLOF expects it.
Looking at the implementation, this doesn't really have a lot to do
with arrays. Its just a pointer to a buffer and is passed through
to the wrapped fn (qemu_fdt_setprop) unchanged. So rename to make it
consistent with libfdt, which in the wrapped function just calls it
"val".
Alexander Graf [Wed, 18 Dec 2013 08:21:02 +0000 (09:21 +0100)]
PPC: Add VSX to hflags
We generate different code depending on whether MSR_VSX is set or
clear, so it needs to be part of our hflags too which indicate whether
we're still in the same translation block cache bucket.
Tom Musta [Fri, 1 Nov 2013 13:21:21 +0000 (08:21 -0500)]
Add xxsel
This patch adds the VSX Select (xxsel) instruction.
The xxsel instruction has four VSR operands. Thus the xC
instruction decoder is added.
The xxsel instruction is massively overloaded in the opcode
table since only bits 26 and 27 are opcode bits. This
overloading is done in matrix fashion with two macros
(GEN_XXSEL_ROW and GEN_XX_SEL).
A common generator macro (VSX_SCALAR_MOVE) is added since these
instructions vary only slightly from each other.
Macros to support VSX XX2 and XX3 form opcodes are also added.
These macros handle the overloading of "opcode 2" space (instruction
bits 26:30) caused by AX and BX bits (29 and 30, respectively).
V3: Per feedback from Paolo Bonzini, moved the sign mask into a
temporary and used andc.
Alexander Graf [Wed, 11 Dec 2013 13:17:44 +0000 (14:17 +0100)]
roms: Flush icache when writing roms to guest memory
We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're basically emulating the cache
off phase on very early system bootup.
That phase is usually responsible for clearing the instruction cache for
anything it writes into cachable memory, to ensure that after reboot we
don't happen to execute stale bits from the instruction cache.
So we need to invalidate the icache every time we write a rom into guest
address space. We do not need to do this for every DMA since the guest
expects it has to flush the icache manually in that case.
This fixes random reboot issues on e5500 (booke ppc) for me.
Paolo Bonzini [Fri, 22 Nov 2013 09:27:40 +0000 (10:27 +0100)]
spapr: tie spapr-nvram to -pflash
spapr-nvram's drive property is currently connected to a non-existent
"-machine nvram=<drivename>" option. Instead, tie it to -pflash like
other non-volatile RAM devices. This provides the following possibilities
for adding a backend for the sPAPR non-volatile RAM:
Alexander Graf [Wed, 4 Dec 2013 11:42:32 +0000 (12:42 +0100)]
PPC: Use default pci bus name for grackle and heathrow
There's no good reason to call our bus "pci" rather than let the default
bus name take over ("pci.0").
The big downside to calling it different from anyone else is that tools
that pass -device get confused. They are looking for a bus "pci.0" rather
than "pci".
To make life easier for everyone, let's just drop the name override.
This adds very basic handlers for ibm,get-system-parameter and
ibm,set-system-parameter RTAS calls.
The only parameter handled at the moment is
"platform-processor-diagnostics-run-mode" which is always disabled and
does not support changing. This is expected to make
"ppc64_cpu --run-mode=1" happy.
So far POWER7+ was a part of POWER7 family. However it has a different
PVR base value so in order to support PVR masks, it needs a separate
family class.
This adds a new family class, PVR base and mask values and moves
Power7+ v2.1 CPU to a new family. The class init function is copied
from the POWER7 family.
This defines a firmware name for the new family as "PowerPC,POWER7+"
instead of previously used "PowerPC,POWER7" from the POWER7 family.
The reason for that is that the Sapphire firmware (a h0st firmware)
uses "PowerPC,POWER7+" already and since no specification defines
exactly the CPU nodes naming in the device tree, we better stay
in sync with the host firmware.
Tom Musta [Tue, 22 Oct 2013 11:09:35 +0000 (22:09 +1100)]
Add xxpermdi
This patch adds the xxpermdi instruction. The instruction
uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
and BX). This results in overloading of the opcode table
with aliases, which can be seen in the GEN_XX3FORM_DM
macro.
Tom Musta [Tue, 22 Oct 2013 11:07:41 +0000 (22:07 +1100)]
Add VSR to Global Registers
This patch adds VSX VSRs to the the list of global register indices.
More specifically, it adds the lower halves of the first 32 VSRs to
the list of global register indices. The upper halves of the first
32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs
are already defined via the cpu_avrh[] and cpu_avrl[] arrays.
Tom Musta [Tue, 22 Oct 2013 11:06:46 +0000 (22:06 +1100)]
Add VSX Instruction Decoders
This patch adds decoders for the VSX fields XT, XS, XA, XB and
DM. The first four are split fields and a general helper for
these types of fields is also added.
Tom Musta [Tue, 22 Oct 2013 11:05:46 +0000 (22:05 +1100)]
Declare and Enable VSX
This patch adds the flag POWERPC_FLAG_VSX to the list of defined
flags and also adds this flag to the list of supported features of
the Power7 and Power8 CPUs. Additionally, the VSX instructions
are added to the list of TCG-enabled instruction.
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU list. Also, new CPU versions of already supported
CPU won't break the existing code.
This adds PVR value/mask support for KVM, i.e. for -cpu host option.
As CPU family class name for POWER7 is "POWER7-family", there is no need
to touch aliases.
Greg Kurz [Wed, 11 Dec 2013 13:15:34 +0000 (14:15 +0100)]
target-ppc: add stubs for KVM breakpoints
The latest update to v3.13-rc3 (bf63839f) breaks the
ppc build with KVM:
kvm-all.o: In function `kvm_update_guest_debug':
kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'
kvm-all.o: In function `kvm_insert_breakpoint':
kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint'
kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint'
kvm-all.o: In function `kvm_remove_breakpoint':
kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint'
kvm-all.o: In function `kvm_remove_all_breakpoints':
kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints'
Anthony Liguori [Thu, 19 Dec 2013 19:56:33 +0000 (11:56 -0800)]
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131217' into staging
target-arm queue:
* AES instruction support for 32 bit ARM
* pflash01: much better emulation of 2x16bit and similar configs
where multiple flash devices are banked together
* fixed CBAR handling on Zynq, Highbank
* initial AArch64 KVM control support
* first two chunks of patches for A64 instruction emulation
* new board: canon-a1100 (Canon DIGIC SoC)
* new board: cubieboard (Allwinner A10 SoC)
# gpg: Signature made Tue 17 Dec 2013 12:18:39 PM PST using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found
# By Alexander Graf (14) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-20131217: (62 commits)
MAINTAINERS: add myself to maintain allwinner-a10
hw/arm: add cubieboard support
hw/arm: add allwinner a10 SoC support
hw/intc: add allwinner A10 interrupt controller
hw/timer: add allwinner a10 timer
vmstate: Add support for an array of ptimer_state *
MAINTAINERS: Document 'Canon DIGIC' machine
hw/arm/digic: add NOR ROM support
hw/arm/digic: add UART support
hw/arm/digic: add timer support
hw/arm/digic: prepare DIGIC-based boards support
hw/arm: add very initial support for Canon DIGIC SoC
target-arm: A64: add support for logical (immediate) insns
target-arm: A64: add support for 1-src CLS insn
host-utils: add clrsb32/64 - count leading redundant sign bits
target-arm: A64: add support for bitfield insns
target-arm: A64: add support for 1-src REV insns
target-arm: A64: add support for 1-src RBIT insn
target-arm: A64: add support for 1-src data processing and CLZ
target-arm: A64: add support for 2-src shift reg insns
...
Thomas Huth [Tue, 17 Dec 2013 18:50:01 +0000 (19:50 +0100)]
s390x/ioinst: CHSC has to set a condition code
I missed to set the CC in the CHSC instruction when I refactored
the CC setting in the IO instructions with the following commit: 5d9bf1c07c1369ab3506fc82cc65a10f4415d867
s390/ioinst: Moved the CC setting to the IO instruction handlers
This patch now restores the correct behaviour of CHSC by setting the
condition code 0 at the end of the instruction.
Thomas Huth [Tue, 17 Dec 2013 13:22:08 +0000 (14:22 +0100)]
s390x/kvm: Simplified the calculation of the SIGP order code
We've already got a helper function for calculating the
base/displacement of RS formatted instructions, so we can
get rid of the manual calculation of the SIGP order code.
Cornelia Huck [Tue, 17 Dec 2013 17:27:33 +0000 (18:27 +0100)]
s390x/kvm: Fix diagnose handling.
The instruction intercept handler for diagnose used only the displacement
when trying to calculate the function code. This is only correct for base
0, however; we need to perform a complete base/displacement address
calculation and use bits 48-63 as the function code.
Peter Maydell [Tue, 17 Dec 2013 19:42:37 +0000 (19:42 +0000)]
vmstate: Add support for an array of ptimer_state *
Add support for defining a vmstate field which is an array
of pointers to structures, and use this to define a
VMSTATE_PTIMER_ARRAY() which allows an array of ptimer_state*
to be used by devices.
Antony Pavlov [Tue, 17 Dec 2013 19:42:36 +0000 (19:42 +0000)]
hw/arm: add very initial support for Canon DIGIC SoC
DIGIC is Canon Inc.'s name for a family of SoC
for digital cameras and camcorders.
There is no publicly available specification for
DIGIC chips. All information about DIGIC chip
internals is based on reverse engineering efforts
made by CHDK (http://chdk.wikia.com) and
Magic Lantern (http://www.magiclantern.fm) projects
contributors.
Alexander Graf [Tue, 17 Dec 2013 19:42:36 +0000 (19:42 +0000)]
target-arm: A64: add support for logical (immediate) insns
This patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted to new decoder, function renaming,
removed a TCG temp variable] Signed-off-by: Claudio Fontana <[email protected]>
[PMM: cleaned up some unnecessary code in logic_imm_decode_wmask
and added clarifying commentary on what it's actually doing.
Dropped an ext32u that's not needed if we've just done an AND.] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:35 +0000 (19:42 +0000)]
target-arm: A64: add support for 1-src RBIT insn
This adds support for the C5.6.147 RBIT instruction.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted to new decoder, use bswap64,
make RBIT part standalone from the rest of the patch,
splitting REV into a separate patch] Signed-off-by: Claudio Fontana <[email protected]> Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:34 +0000 (19:42 +0000)]
target-arm: A64: add support for 2-src data processing and DIV
This patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted to new decoder adding the 2-src decoding level,
always zero-extend result in 32bit mode] Signed-off-by: Claudio Fontana <[email protected]> Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:34 +0000 (19:42 +0000)]
target-arm: A64: add support for EXTR
This patch adds emulation support for the EXTR instruction.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted for new decoder, removed a few temporaries,
fixed the 32bit bug, added checks for more
unallocated cases]
Alexander Graf [Tue, 17 Dec 2013 19:42:34 +0000 (19:42 +0000)]
target-arm: A64: add support for logical (shifted register)
Add support for the instructions described in "C3.5.10 Logical
(shifted register)".
We store the flags in the same locations as the 32 bit decoder.
This is slightly awkward when calculating 64 bit results, but seems
a better tradeoff than having to rework the whole 32 bit decoder
and also make 32 bit result calculation in A64 awkward.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: some refactoring to avoid hidden allocation of temps,
rework flags, use enums for shift types,
renaming of functions] Signed-off-by: Claudio Fontana <[email protected]>
[PMM: Use TCG's andc/orc/eqv ops rather than manually inverting] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Claudio Fontana [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for conditional select
This patch adds support for the instruction group "C3.5.6
Conditional select": CSEL, CSINC, CSINV, CSNEG.
Signed-off-by: Claudio Fontana <[email protected]>
[PMM: Improved code generated in the nomatch case as per RTH suggestions] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for compare and branch imm
This patch adds emulation for the compare and branch insns,
CBZ and CBNZ.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted to new decoder,
compare with immediate 0,
introduce read_cpu_reg to get the 0 extension on (!sf)] Signed-off-by: Claudio Fontana <[email protected]> Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for 'test and branch' imm
This patch adds emulation for the test and branch insns,
TBZ and TBNZ.
Signed-off-by: Alexander Graf <[email protected]>
[claudio:
adapted for new decoder
always compare with 0
remove a TCG temporary
] Signed-off-by: Claudio Fontana <[email protected]> Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for conditional branches
This patch adds emulation for the conditional branch (b.cond) instruction.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted to new decoder structure,
reused arm infrastructure for checking the flags] Signed-off-by: Claudio Fontana <[email protected]> Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for BR, BLR and RET insns
Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
and DPRS (which are system mode only).
Alexander Graf [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: add support for B and BL insns
Implement the B and BL instructions (PC relative branches and calls).
For convenience in managing TCG temporaries which might be generated
if a source register is the zero-register XZR, we provide a simple
mechanism for creating a new temp which is automatically freed at the
end of decode of the instruction.
Claudio Fontana [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: expand decoding skeleton for system instructions
Decode the various kinds of system instructions:
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
sync instructions, which include CLREX, DSB, DMB, ISB
msr_i, which move immediate to processor state field
sys, which include all SYS and SYSL instructions
msr, which move from a gp register to a system register
mrs, which move from a system register to a gp register
Provide implementations where they are trivial nops.
Claudio Fontana [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: provide skeleton for a64 insn decoding
Provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) section C3.
Alexander Graf [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: add stubs for a64 specific helpers
We will need helpers that only make sense with AArch64. Add
helper-a64.{c,h} files as stubs that we can fill with these
helpers in the following patches.
Peter Maydell [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
target-arm: A64: provide functions for accessing FPCR and FPSR
The information which AArch32 holds in the FPSCR is split for
AArch64 into two logically distinct registers, FPSR and FPCR.
Since they are carefully arranged to use non-overlapping bits,
we leave the underlying state in the same place, and provide
accessor functions which just update the appropriate bits
via vfp_get_fpscr() and vfp_set_fpscr().
Alexander Graf [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
target-arm: A64: add set_pc cpu method
When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch64 CPUs.
This covers user-mode, but for system mode emulation we will
need to check if the CPU is in an AArch32 execution state.
Peter Maydell [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()
The A32/T32 gen_intermediate_code_internal() is complicated because it
has to deal with:
* conditionally executed instructions
* Thumb IT blocks
* kernel helper page
* M profile exception-exit special casing
None of these apply to A64, so putting the "this is A64 so
call the A64 decoder" check in the middle of the A32/T32
loop is confusing and means the A64 decoder's handling of
things like conditional jump and singlestepping has to take
account of the conditional-execution jumps the main loop
might emit.
Refactor the code to give A64 its own gen_intermediate_code_internal
function instead.
Peter Maydell [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
default-configs: Add config for aarch64-softmmu
Add a config for aarch64-softmmu; this enables building of this target.
The resulting executable doesn't know about any 64 bit CPUs, but all
the 32 bit CPUs and board models work.
Mian M. Hamayun [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
hw/arm/boot: Add boot support for AArch64 processor
This commit adds support for booting a single AArch64 CPU by setting
appropriate registers. The bootloader includes placeholders for Board-ID
that are used to implement uniform indexing across different bootloaders.
Signed-off-by: Mian M. Hamayun <[email protected]> Signed-off-by: Peter Maydell <[email protected]>
Message-id: 1385645602[email protected]
[PMM:
* updated to use ARMInsnFixup style bootloader fragments
* dropped virt.c additions
* use runtime checks for "is this an AArch64 core" rather than ifdefs
* drop some unnecessary setting of registers in reset hook
] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Christoffer Dall <[email protected]>
Peter Maydell [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
hw/arm/boot: Allow easier swapping in of different loader code
For AArch64 we will obviously require a different set of
primary and secondary boot loader code fragments. However currently
we hardcode the offsets into the loader code where we must write
the entrypoint and other data into arm_load_kernel(). This makes it
hard to substitute a different loader fragment, so switch to a more
flexible scheme where instead of a raw array of instructions we use
an array of (instruction, fixup-type) pairs that indicate which
words need special action or data written into them.
Peter Maydell [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
configure: Enable KVM for aarch64 host/target combination
Enable KVM if the host and target CPU are both aarch64. Note
that host aarch64 + target arm is not valid for KVM acceleration:
the 64 bit kernel does not support the ioctl interface for
32 bit CPUs. 32 bit VMs on 64 bit hosts need to be created
using the 64 bit ioctl interface; when QEMU supports this it
will be on the arch64-softmmu target with a -cpu parameter for
a 32 bit CPU, which is still an aarch64/aarch64 combination
as far as configure is concerned.
Mian M. Hamayun [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
target-arm: Add minimal KVM AArch64 support
Add the bare minimum set of functions needed for control of an
AArch64 KVM vcpu:
* CPU initialization
* minimal get/put register functions which only handle the
basic state of the CPU
Signed-off-by: Mian M. Hamayun <[email protected]> Signed-off-by: Peter Maydell <[email protected]>
Message-id: 1385645602[email protected]
[PMM: significantly overhauled; most notably:
* code lives in kvm64.c rather than using #ifdefs
* support '-cpu host' rather than implicitly using whatever the
host's CPU is regardless of what the user requests
* fix bug attempting to get/set nonexistent X[31]
* fix bug writing 64 bit kernel pstate into uint32_t env field
] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Christoffer Dall <[email protected]>
Peter Maydell [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
target-arm: Clean up handling of AArch64 PSTATE
The env->pstate field is a little odd since it doesn't strictly
speaking represent an architectural register. However it's convenient
for QEMU to use it to hold the various PSTATE architectural bits
in the same format the architecture specifies for SPSR registers
(since this is the same format the kernel uses for signal handlers
and the KVM register). Add some structure to how we deal with it:
* document what env->pstate is
* add some #defines for various bits in it
* add helpers for reading/writing it taking account of caching
of NZCV, and use them where appropriate
* reset it on startup
Peter Maydell [Tue, 17 Dec 2013 19:42:29 +0000 (19:42 +0000)]
target-arm/kvm: Split 32 bit only code into its own file
Split ARM KVM support code which is 32 bit specific out into its
own file, which we only compile on 32 bit hosts. This will give
us a place to add the 64 bit support code without adding lots of
ifdefs to kvm.c.
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.
Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the intended value is now
actually used.
So I have kind of tested this. I booted an ARM kernel on Highbank with
the stock Highbank DTB. It doesn't boot (and I will be doing something
wrong), but before this patch I got this:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at /workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 __arm_ioremap_pfn_caller+0x180/0x198()
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.13.0-rc1-next-20131126-dirty #2
[<c0015164>] (unwind_backtrace) from [<c00118c0>] (show_stack+0x10/0x14)
[<c00118c0>] (show_stack) from [<c02bd5fc>] (dump_stack+0x78/0x90)
[<c02bd5fc>] (dump_stack) from [<c001f110>] (warn_slowpath_common+0x68/0x84)
[<c001f110>] (warn_slowpath_common) from [<c001f1f4>] (warn_slowpath_null+0x1c/0x24)
[<c001f1f4>] (warn_slowpath_null) from [<c0017c6c>] (__arm_ioremap_pfn_caller+0x180/0x198)
[<c0017c6c>] (__arm_ioremap_pfn_caller) from [<c0017cd8>] (__arm_ioremap_caller+0x54/0x5c)
[<c0017cd8>] (__arm_ioremap_caller) from [<c0017d10>] (__arm_ioremap+0x18/0x1c)
[<c0017d10>] (__arm_ioremap) from [<c03913c0>] (highbank_init_irq+0x34/0x8c)
[<c03913c0>] (highbank_init_irq) from [<c038c228>] (init_IRQ+0x28/0x2c)
[<c038c228>] (init_IRQ) from [<c03899ec>] (start_kernel+0x234/0x398)
[<c03899ec>] (start_kernel) from [<00008074>] (0x8074)
---[ end trace 3406ff24bd97382f ]---
projects / qemu.git / log