target-sparc: fix FMOVr instruction

Like the MOVr instruction, the FMOVr instruction has the condition
encoded between bits 10 and 12.

Cc: Blue Swirl <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

hw/pl031: Use LOG_GUEST_ERROR

Use LOG_GUEST_ERROR rather than hw_error or direct fprintf.

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

hw/pl022: Use LOG_UNIMP and LOG_GUEST_ERROR

Use LOG_UNIMP and LOG_GUEST_ERROR where appropriate rather
than hw_error().

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

hw/pl011: Use LOG_UNIMP and LOG_GUEST_ERROR

Use the new LOG_UNIMP and LOG_GUEST_ERROR logging types rather
than hw_error().

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

hw/pl190: Use LOG_GUEST_ERROR

If the guest attempts an offset to a nonexistent register, just
log this via LOG_GUEST_ERROR rather than killing QEMU with a hw_error.

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

hw/pl041: Use LOG_UNIMP

Use the new LOG_UNIMP tracing to report unimplemented
features.

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

hw/pl181: Use LOG_UNIMP and LOG_GUEST_ERROR

Rather than a mix of direct printing to stderr and aborting
via hw_error(), use LOG_UNIMP and LOG_GUEST_ERROR.

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

hw/hw.h: Add include of qemu-log.h

Add an include of qemu-log.h to hw.h, so that device model
code has access to these logging functions without the need
to directly include qemu-log.h.

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

qemu-log: Add new log category for guest bugs

Add a new category for device models to log guest behaviour
which is likely to be a guest bug of some kind (accessing
nonexistent registers, reading 32 bit wide registers with
a byte access, etc). Making this its own log category allows
those who care (mostly guest OS authors) to see the complaints
without bothering most users.

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Remove cpu_tmp0 as a global

Subroutines do their own local temporary management.
Within disas_sparc_insn we limit the existance of the variable
to OP=2 insns, and delay initialization as late as is reasonable
for the specific XOP.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Make cpu_dst local to OP=2 insns

And initialize it such that it (may) write directly to rd.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Only use cpu_dst for eventual writes to a gpr

Use cpu_tmp0 for other stuff, like Write Priv Register.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Remove last uses of cpu_tmp64

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Remove cpu_tmp64 use from softint insns

The use of "tl" functions and a tmp64 is logically incompatible.
Use cpu_tmp0 instead.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Don't use a temporary for gen_dest_fpr_D

In all cases we don't have write-before-read problems.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Remove usage of cpu_tmp64 from most helper functions

Use a locally allocated temporary instead.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Tidy ldfsr, stfsr

Remove the last uses of cpu_tmp32.  Unify the code between sparc64
and sparc32 by using the proper "tl" functions.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Avoid cpu_tmp32 in Write Priv Register

No need to copy to a temporary to store 32 bits.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Avoid cpu_tmp32 in Read Priv Register

We don't need another temporary here.  Load directly into the
register we want to set.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Use get_temp_i32 in gen_dest_fpr_F

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Split out get_temp_i32

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Make the cpu_addr variable local to load/store handling

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Cleanup cpu_src[12] allocation

Now that get_temp_tl is used for get_src[12], we don't need to
pre-allocate these temporaries.

Fallout from this is moving some assignments around cas/casx to
avoid uninitialized variable warnings.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Finish conversion to gen_load_gpr

All users of gen_movl_{reg_TN,TN_reg} are removed.  At the same time,
make cpu_val a local variable for load/store disassembly.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Convert swap to gen_load/store_gpr

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Convert asi helpers to gen_*_gpr

Push the DisasContext down so that we can use gen_load/store_gpr
in sode gen_ldda_asi, gen_stda_ast, gen_cas_asi, gen_casx_asi.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Use gen_load_gpr in get_src[12]

This means we can avoid the incoming temporary, though the cleanup
of the existing temporaries is not performed in this patch.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Conversion to gen_*_gpr, part 1

Only handle the easy cases directly within disas_sparc_insn.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Add gen_load/store/dest_gpr

Infrastructure to be used to clean up handling of temporaries.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

exec: Make MIN_CODE_GEN_BUFFER_SIZE private to exec.c

It is used nowhere else, and the corresponding MAX_CODE_GEN_BUFFER_SIZE
also lives there.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

exec: Allocate code_gen_prologue from code_gen_buffer

We had a hack for arm and sparc, allocating code_gen_prologue to a
special section.  Which, honestly does no good under certain cases.
We've already got limits on code_gen_buffer_size to ensure that all
TBs can use direct branches between themselves; reuse this limit to
ensure the prologue is also reachable.

As a bonus, we get to avoid marking a page of the main executable's
data segment as executable.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

exec: Do not use absolute address hints for code_gen_buffer with -fpie

The hard-coded addresses inside alloc_code_gen_buffer only make sense
if we're building an executable that will actually run at the address
we've put into the linker scripts.

When we're building with -fpie, the executable will run at some
random location chosen by the kernel.  We get better placement for
the code_gen_buffer if we allow the kernel to place the memory,
as it will tend to to place it near the executable, based on the
PROT_EXEC bit.

Since code_gen_prologue is always inside the executable, this effect
is easily seen at the end of most TB, with the exit_tb opcode, and
with any calls to helper functions.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

exec: Don't make DEFAULT_CODE_GEN_BUFFER_SIZE too large

For ARM we cap the buffer size to 16MB.  Do not allocate 32MB in that case.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

exec: Split up and tidy code_gen_buffer

It now consists of:

A macro definition of MAX_CODE_GEN_BUFFER_SIZE with host-specific values,

A function size_code_gen_buffer that applies most of the reasoning for
choosing a buffer size,

Three variations of a function alloc_code_gen_buffer that contain all
of the logic for allocating executable memory via a given allocation
mechanism.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

create struct for machine initialization arguments

This should help us to:
- More easily add or remove machine initialization arguments without
  having to change every single machine init function;
- More easily make mechanical changes involving the machine init
  functions in the future;
- Let machine initialization forward the init arguments to other
  functions more easily.

This change was half-mechanical process: first the struct was added with
the local ram_size, boot_device, kernel_*, initrd_*, and cpu_model local
variable initialization to all functions. Then the compiler helped me
locate the local variables that are unused, so they could be removed.

Signed-off-by: Blue Swirl <[email protected]>

vga: remove CONFIG_BOCHS_VBE

Signed-off-by: Gerd Hoffmann <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

vga: add specs for standard vga

Signed-off-by: Gerd Hoffmann <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

vga: add mmio bar to standard vga

This patch adds a mmio bar to the qemu standard vga which allows to
access the standard vga registers and bochs dispi interface registers
via mmio.

Cc: Benjamin Herrenschmidt <[email protected]>
Signed-off-by: Gerd Hoffmann <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

vga: fix indention

Signed-off-by: Gerd Hoffmann <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tests/tcg: fix build

This broke when the tests were moved from tests/ to tests/tcg/.

On x86_64 host/i386-linux-user non-kvm guest, test-i386 and test-mmap are broken, but at least they build.

To build/run the tests:
$ cd $BUILD_PATH/tests/tcg
$ SRC_PATH=path/to/qemu make <target>

Signed-off-by: Catalin Patulea <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

allow make {dist, }clean work w/out configure

There's no reason to require configure to run before running a clean
target, so check MAKECMDGOALS before.

Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tci: fix build breakage for target-sparc

commit c28ae41 introduced GETPC() usage for sparc, which is currently
not defined when building with --enable-tcg-interpreter. Add sparc to
the list of targets we selectively define GETPC() for.

Signed-off-by: Michael Roth <[email protected]>
Reviewed-by: Stefan Weil <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

MAINTAINERS: Update email address for Stefan Hajnoczi

Switch to my new work email address from which I am contributing.

Signed-off-by: Stefan Hajnoczi <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

configure: Fix CONFIG_QEMU_HELPERDIR generation

We need to evaluate $libexecdir in configure, otherwise we literally end
up with "${prefix}/libexec" instead of the absolute path as
CONFIG_QEMU_HELPERDIR.

Signed-off-by: Jan Kiszka <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

qemu-options.hx: Change from recommending '?' to 'help'

Update the -help output and documentation so that it recommends
'help' rather than '?' for the various "list valid values for this
option" cases. '?' is deprecated (as it can fail confusingly if
not quoted), so it's better to steer users towards 'help'. ('?'
still works, for backwards compatibility.)

This is the -help option part of the change otherwise done in
commit c8057f9, since we are now past release 1.2 and free to
change our help text without worrying about breaking libvirt.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

Merge branch 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoipio/qemu

* 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoipio/qemu:
  linux-user: register align p{read, write}64
  linux-user: ppc: mark as long long aligned
  tcg: Remove TCG_TARGET_HAS_GUEST_BASE define
  configure: Remove unnecessary host_guest_base code
  linux-user: If loading fails, print error as string, not number
  linux-user: Fix siginfo handling
  alpha-linux-user: Fix sigaltstack structure definition
  linux-user: Implement gethostname
  linux-user: Perform more checks on iovec lists
  linux-user: fix multi-threaded /proc/self/maps
  linux-user: fix statfs

Merge branch 'trivial-patches' of git://github.com/stefanha/qemu

* 'trivial-patches' of git://github.com/stefanha/qemu:
  ui/vnc-jobs.c: Fix minor typos in comments
  net/tap-win32: Fix compiler warning caused by missing include statement
  configure: Remove unused parameters from main function
  target-arm/neon_helper: Remove obsolete FIXME comment
  targphys.h: Don't define target_phys_addr_t for user-mode emulators
  ui/vnc: Only report/use TIGHT_PNG encoding if enabled.

microblaze: Update PC before simulating syscall

Fixes a clone() emulation bug were the new thread starts
at the point of the syscall and thus clones in a loop.

Signed-off-by: Edgar E. Iglesias <[email protected]>

microblaze: Support setting of TLS ptr

Signed-off-by: Edgar E. Iglesias <[email protected]>

ui/vnc-jobs.c: Fix minor typos in comments

Fix some minor typos/grammar errors in comments.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Stefan Weil <[email protected]>
Signed-off-by: Stefan Hajnoczi <[email protected]>

net/tap-win32: Fix compiler warning caused by missing include statement

The include file for net_init_tap was missing:

net/tap-win32.c:703:
 warning: no previous prototype for ‘net_init_tap’

Signed-off-by: Stefan Weil <[email protected]>
Signed-off-by: Stefan Hajnoczi <[email protected]>

configure: Remove unused parameters from main function

This modification is required if compiler option -Wunused-parameter is activated.

Signed-off-by: Stefan Weil <[email protected]>
Signed-off-by: Stefan Hajnoczi <[email protected]>

target-arm/neon_helper: Remove obsolete FIXME comment

Commit 33ebc29 fixed the bugs in the implementation of VQRSHL,
but forgot to remove the FIXME comment...

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Stefan Hajnoczi <[email protected]>

targphys.h: Don't define target_phys_addr_t for user-mode emulators

Commit 4be403c accidentally defined the target_phys_addr_t type when
building user-mode emulators. Since the type doesn't really make
any sense except for system emulators, avoid defining it when building
in user mode.

Signed-off-by: Peter Maydell <[email protected]>
Acked-by: Andreas Färber <[email protected]>
Signed-off-by: Stefan Hajnoczi <[email protected]>

ui/vnc: Only report/use TIGHT_PNG encoding if enabled.

If TIGHT_PNG is not enabled by the --enable-vnc-png configure flag
then do not report to the client that it is supported.

Also, since TIGHT_PNG is the same as the TIGHT encoding but with the
filter/copy replaced with PNG data, adding it to the supported
encodings list when it is disabled will cause the TIGHT encoding to be
used even though the client requested TIGHT_PNG.

Signed-off-by: Joel Martin <[email protected]>
Signed-off-by: Stefan Hajnoczi <[email protected]>

target-arm/translate: Fix RRX operands

Instructions that both use the RRX second operand and update CS were
incorrect, as the Carry flag was updated too early. An example of such an
instruction would be:

ands r12,r13,RRX

Ands, because of the "s" flag will update the carry flag. But the RRX second
operand rotates through the C flag which should happen before the update.
Fixed the ordering of the two, the old carry is read by "r13,RRX" before being
updated.

Signed-off-by: Peter Crosthwaite <[email protected]>
Reported-by: Vinesh Peringat <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg: Optimize mulu2

Like add2, do operand ordering, constant folding, and dead operand
elimination.  The latter happens about 15% of all mulu2 during an
x86_64 bios boot.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg: Optimize half-dead add2/sub2

When x86_64 guest is not in 64-bit mode, the high-part of the 64-bit
add is dead.  When the host is 32-bit, we can simplify to 32-bit
arithmetic.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg: Constant fold add2 and sub2

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg: Do constant folding on double-word comparisons

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg: Split out subroutines from do_constant_folding_cond

We can re-use these for implementing double-word folding.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg: Optimize double-word comparisons against zero

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg: Use common code when failing to optimize

This saves a whole lot of repetitive code sequences.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg: Swap commutative double-word comparisons

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg: Canonicalize add2 operand ordering

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg: Split out swap_commutative as a subroutine

Reduces code duplication and prefers

  movcond d, c1, c2, const, s
to
  movcond d, c1, c2, s, const

It also prefers

  add r, r, c
over
  add r, c, r

when both inputs are known constants.  This doesn't matter for true add, as
we will fully constant fold that.  But it matters for a follow-on patch using
this routine for add2 which may not be fully foldable.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

target-mips: Pass MIPSCPU to mips_vpe_sleep()

Needed for moving halted field to CPUState.

Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

target-mips: Pass MIPSCPU to mips_tc_sleep()

Needed for changing mips_vpe_sleep() argument type to MIPSCPU.

Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

target-mips: Pass MIPSCPU to mips_vpe_is_wfi()

Needed for moving halted field to CPUState.
The variable name "c" is retained for MIPSCPU to leave "cpu" for CPUState.

Also change return type to bool while at it.

Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

target-mips: Pass MIPSCPU to mips_tc_wake()

Needed for changing mips_vpe_is_wfi() argument type to MIPSCPU.

Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

target-mips: Clean up other_cpu in helper_{d,e}vpe()

Free the variable name "other_cpu" for later use for MIPSCPU.

Fix off-by-one indentation while at it.

Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg-ia64: Implement deposit

Note that in the general reg=reg,reg case we're restricted
to 16-bit insertions.  This makes it easy to allow "any"
constant as input, as post-truncation it will fit into the
constant load insn for which we have room in the bundle.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg/ia64: slightly optimize TLB access code

It is possible to slightly optimize the TLB access code, by replacing
the movi + and instructions by a deposit instruction.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg/ia64: remove suboptimal register shifting in qemu_ld/st ops

Remove suboptimal register shifting in qemu_ld/st ops, introduced at the
CONFIG_TCG_PASS_AREG0 time.

As mem_idx is now loaded in register R58/R59 for the slow path, we have
to make sure to do it last, to not add additional register constraints.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg/ia64: implement movcond_i32/64

Implement movcond_i32/64 on ia64 hosts. It is not possible to have
immediate compare arguments without adding a new bundle, but it is
possible to have 22-bit immediate value arguments.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg/ia64: use stack for TCG temps

Use stack instead of temp_buf array in CPUState for TCG temps.

Signed-off-by: Blue Swirl <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg/arm: Implement movcond_i32

Implement movcond_i32 for ARM, as the sequence
  mov dst, v2   (implicitly done by the tcg common code)
  cmp c1, c2
  movCC dst, v1

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

tcg/arm: Factor out code to emit immediate or reg-reg op

The code to emit either an immediate cmp or a register cmp insn is
duplicated in several places; factor it out into its own function.

Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

Fix popcnt in long mode

Thanks to Andriy Gapon for initial problem report.

Signed-off-by: malc <[email protected]>

sun4u: Pass SPARCCPU to cpu_set_ivec_irq()

Needed for moving halted field to CPUState.

Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

sun4u: Pass SPARCCPU to cpu_kick_irq()

Needed for changing qemu_cpu_kick() argument type to CPUState.

Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

sun4u: Pass SPARCCPU to {,s,hs}tick_irq() and cpu_timer_create()

Needed for changing cpu_kick_irq() argument type to SPARCCPU.

Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

sun4m: Pass SPARCCPU to cpu_kick_irq()

Needed for changing qemu_cpu_kick() argument type to CPUState.

Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

sun4m: Pass SPARCCPU to cpu_set_irq()

Needed for changing cpu_kick_irq() argument type to SPARCCPU.

Signed-off-by: Andreas Färber <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Emit MOVR insns for setcond_i64 and movcond_64

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Emit BPr insns for brcond_i64

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Dump illegal opode contents

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Drop use of Bicc in favor of BPcc

Now that we're always sparcv9, we can not bother using Bicc for
32-bit branches and BPcc for 64-bit branches and instead always
use BPcc.

New interfaces allow less direct use of tcg_out32 and raw numbers
inside the qemu_ld/st routines.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Optimize setcond2 equality compare with 0.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Use Z constraint for %g0

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Fix add2/sub2

We must care not to clobber the high parts before we consume them.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Fix setcond

The set of comparisons that can immediately use the carry are LTU/GEU,
not LTU/LEU.  Don't swap operands when we need a temp register; the
register may already be in use from setcond2.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Fix qemu_st for 32-bit

The datalo variable is still live in the miss path.  Use another
when reconstructing the full data value.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Fix setcond2

Like brcond2, use tcg_high_cond.  Use movcc instead of branches.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Implement movcond.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

tcg-sparc: Fix brcond2

Much the same problem as recently fixed for hppa.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Don't compute full flags value so often

Avoid speculatively computing flags before every potentially trapping
operation and instead do the flags computation when a trap actually
occurs.  This gives approximately 30% speedup in emulation.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Avoid unnecessary local temporaries

Now that save_state never ends a BB, we don't need to copy
values into local temps around it.

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Optimize CC_OP_LOGIC conditions

Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

target-sparc: Fix optimized %icc comparisons

Signed-off-by: Richard Henderson <[email protected]>
Tested-by: Aurelien Jarno <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>