Recently PXA2xx lcd have stopped to be updated incrementally (picture
frozen). This patch fixes that by passing non min/max x/y, but rather
(correctly) x/y and w/h.
vmstate_pxa2xx_i2c incorrectly recursed to itself instead of going
to store slave device. Fix that stop stop qemu from segfaulting
during savevm for pxa2xx-based devices.
scoop: fix access to registers from second instance
Second instance of scoop contains registers shifted to 0x40 from the start
of the page. Instead of messing with register mapping, just limit register
address to 0x00..0x3f.
mainstone: fix name of the allocated memory for roms
Mainstone board has two flash chips (emulated by two ram regions), however
currently code tries to allocate them with the same name, which fails.
Fix that to make mainstone emulation work again.
Fred Boiteux [Sun, 9 Jan 2011 13:24:59 +0000 (14:24 +0100)]
add bepo (french dvorak) keyboard layout
I'm using the Qemu program with VNC I/O, and I had some problems with
my keyboard layout, so I've prepared a definition to be included in
Qemu, built from Xorg description.
floatx80_is_{quiet,signaling}_nan() functions are incorrectly detecting
the type of NaN, depending on SNAN_BIT_IS_ONE, one of the two is
returning the correct value, and the other true for any kind of NaN.
This patch fixes that by applying the same kind of comparison as for
other float formats, but taking into account the explicit bit.
Blue Swirl [Tue, 18 Jan 2011 21:34:51 +0000 (21:34 +0000)]
sparc: fix NaN handling
Fix several bugs in NaN handling:
* e in fcmpe* only changes qNaN handling
* FCC is unchanged if an exception is raised
* clear previous FTT before setting it
When reading cp0_count from a timer with a late trigger that should
already have expired, expire it and raise the timer irq.
This makes it possible for guest code (e.g, Linux) that first read
cp0_count, then compare it with cp0_compare and check for raised
timer interrupt lines to run reliably.
Stefan Weil [Sun, 16 Jan 2011 15:28:20 +0000 (16:28 +0100)]
bsd-user: Fix possible memory leaks and wrong realloc call
These errors were reported by cppcheck:
[bsd-user/elfload.c:1108]: (error) Common realloc mistake: "syms" nulled but not freed upon failure
[bsd-user/elfload.c:1076]: (error) Memory leak: s
[bsd-user/elfload.c:1079]: (error) Memory leak: syms
v2:
* The previous fix for memory leaks was incomplete (thanks to Peter Maydell for te hint).
* Fix wrong realloc usage, too.
Michael Tokarev [Mon, 18 Oct 2010 12:55:25 +0000 (16:55 +0400)]
USB keyboard emulation key mapping error
The USB keyboard emulation's translation table in hw/usb-hid.c doesn't
match the codes actually sent for the Logo (a.k.a. "Windows") or Menu
keys. This results in the guest OS not being able to receive these keys
at all when the USB keyboard emulation is being used.
In particular, both the keymap in /usr/share/kvm/keymaps/modifiers and
the evdev table in x_keymap.c map these keys to 0xdb, 0xdc, and 0xdd,
while usb_hid_usage_keys[] seems to be expecting them to be mapped to
0x7d, 0x7e, and 0x7f.
The attached patch seems to fix the problem, at least in my (limited)
testing.
http://bugs.debian.org/578846
http://bugs.debian.org/600593 (cloned from the above against different pkg)
https://bugs.launchpad.net/qemu/+bug/584139
Blue Swirl [Sun, 16 Jan 2011 08:32:27 +0000 (08:32 +0000)]
tcg/sparc64: fix segfault
With current OpenBSD, code_gen_buffer was mapped 8GB away from
text segment. Then any helpers were beyond the 2GB range of call
instruction genereated by TCG and so the calls would go nowhere,
leading to a segfault.
Fix by specifying an address for the code_gen_buffer,
hopefully free and nearby the helpers.
Blue Swirl [Sat, 15 Jan 2011 08:31:00 +0000 (08:31 +0000)]
monitor: fix a typo
Fix usage of wrong variable, spotted by clang:
/src/qemu/monitor.c:2278:36: warning: The left operand of '&' is a garbage value
prot = pde & (PG_USER_MASK | PG_RW_MASK |
Stefan Weil [Thu, 30 Dec 2010 12:04:57 +0000 (12:04 +0000)]
make_device_config: Fix non-fatal error message with dash and other shells
ORS=" " adds a blank to the name of the include file.
Some shells (e.g. dash) don't accept input redirection
(tr -d '\r' < $f) when $f ends with a blank, so they
print an error message instead of reading pci.mak.
This is a non-fatal error because pci.mak does not
contain an include line. It was introduced by commit 5d6b423c5cd6f9dfac30959ff1d5c088996719c3.
Using printf avoids adding a blank and is also supported
by older awk versions (this solution was suggested by
Paolo Bonzini, thank you).
Aurelien Jarno [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
MAINTAINERS: add entries for TCG
The MAINTAINERS file was lacking entries concerning the TCG code, add
them based on the git history.
For the common TCG code, is probably better to keep [email protected]
as this code can break easily, so it's better to get it reviewed by a few
persons.
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Restore IT bits when resuming after an exception
We were not correctly restoring the IT bits when resuming execution
after taking an unexpected exception in the middle of an IT block.
Fix this by tracking them along with PC changes and restoring in
gen_pc_load().
This fixes bug https://bugs.launchpad.net/qemu/+bug/581335
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
linux-user: ARM: clear the IT bits when invoking a signal handler
When invoking a signal handler for an ARM target, make sure the IT
bits in the CPSR are cleared. (This would otherwise cause incorrect
execution if the IT state was non-zero when an exception occured.
This bug has been masked previously because we weren't getting the
IT state bits at exception entry right anyway.)
Also use the proper cpsr_read()/cpsr_write() interface to update
the CPSR rather than manipulating CPUState fields directly.
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Remove redundant setting of IT bits before Thumb SWI
Remove a redundant call to gen_set_condexec() in the translation of Thumb
mode SWI. (SWI and WFI generate "exceptions" which happen after the
execution of the instruction, ie when PC and IT bits have updated.
So the condexec bits at this point are not correct. However, the code
that handles finishing the translation of the TB will write the correct
value of the condexec bits later, so the only effect was that a conditional
Thumb SWI would generate slightly worse code than necessary.)
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Translate with condexec bits from TB flags, not CPUState
When translating, the condexec bits for the TB are in the TB flags;
the CPUState condexec bits may be different.
This patch fixes https://bugs.launchpad.net/bugs/604872 where we might
segfault if we took an exception in the middle of a TB with an IT
block, because when we came to retranslate in cpu_restore_state()
the CPUState condexec bits would have advanced compared to the start
of the TB and we would generate different (wrong) code.
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Translate with VFP-enabled from TB flags, not CPUState
When translating code, whether the VFP unit is enabled for this TB
is stored in a bit in the TB flags. Use this rather than incorrectly
reading the FPEXC from the CPUState passed to translation.
Peter Maydell [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-arm: Don't generate code specific to current CPU mode for SRS
When translating the SRS instruction, handle the "store registers
to stack of current mode" case in the helper function rather than
inline. This means the generated code does not make assumptions
about the current CPU mode which might not be valid when the TB
is executed later.
Peter Maydell [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-arm: Add support for 'Standard FPSCR Value' as used by Neon
Add support to the ARM helper routines for a second fp_status value
which should be used for operations which the ARM ARM indicates use
"ARM standard floating-point arithmetic" rather than being controlled
by the rounding/flush/NaN settings in the FPSCR.
Peter Maydell [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-arm: Fix implementation of VRSQRTS
The implementation of the ARM VRSQRTS instruction (which calculates
(3 - op1 * op2) / 2) was missing the division operation. It also
did not handle the special cases of (0,inf) and (inf,0).
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
lsi53c895a: fix endianness issues
lsi_ram_read*() and lsi_ram_write*() are not consistent, one uses
leXX_to_cpu() the other uses nothing. As the comment above the RAM
declaration says: "Script ram is stored as 32-bit words in host
byteorder.", remove the leXX_to_cpu() calls.
This fixes the boot of an ARM versatile machine on MIPS and PowerPC
hosts.
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: simplify comparisons after a 'and' op
When a TCG variable is anded with a value and the compared with the same
value, we can simply invert the comparison and compare it with 0. The
generated code is smaller.
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: implement FPU exceptions
FPU exception support where not implemented on SH4. Implement them by
clearing the softfloat exceptions flags before an FP instruction (the
SH4 FPU also clear them before an instruction), and calling a function
to update the FPSCR register after an FP instruction. This function
update the corresponding FPSCR bits (both flags and cumulative flags)
and trigger exception if enabled.
Aurelien Jarno [Fri, 14 Jan 2011 19:39:17 +0000 (20:39 +0100)]
softfloat: fix default-NaN mode
When the default-NaN mode is enabled, it should return the default NaN
value, but it should anyway raise the invalid operation flag if one of
the operand is an sNaN.
I have checked that this behavior matches the ARM and SH4 manuals, as
well as real SH4 hardware.
Aurelien Jarno [Fri, 14 Jan 2011 19:39:17 +0000 (20:39 +0100)]
target-sh4: switch sh4 to softfloat
We need to be able to catch exceptions correctly and thus enable softfloat
on SH4.
As all machines except i386 and x86_64 are using softfloat, make it the
default and change the case to detect i386 and x86_64. Note that CRIS
doesn't have an FPU, so it can be configured with both softfloat-native
and softfloat.
Aurelien Jarno [Fri, 14 Jan 2011 19:21:22 +0000 (20:21 +0100)]
configure: fix broken test
Since commit d1807a4f836c27f6dc7061e53a834dd27f78e46a ./configure tries
to test files and directories with "test -f", which only test for regular
files. Test with "test -e", which looks for any kind of files.
This unbreak the configure script when not using a separate object
directory.
Paolo Bonzini [Thu, 23 Dec 2010 10:43:53 +0000 (11:43 +0100)]
do not pass bogus $(SRC_PATH) include paths to cc during configure
Non-existent -I paths are dropped silently by the compiler, but still
it is not polite to pass bogus options. Configure-time tests do not
need any include files from the source path, so only include -I flags
at make time (when they're properly expanded).
Paolo Bonzini [Thu, 23 Dec 2010 10:43:52 +0000 (11:43 +0100)]
test cc with the complete set of chosen flags
The "test the C compiler works ok" comes before a bunch of flags
are added for --cpu or just depending on the host. It helps
debugging if the test is done after these flags are (unconditionally)
added.
Paolo Bonzini [Thu, 23 Dec 2010 10:43:51 +0000 (11:43 +0100)]
fix sparse support (?)
I didn't test with sparse, but the old code using += before a variable
was set was wrong. Sparse support should probably be ripped out or
redone, but this at least keeps some sanity.
Sergei Gavrikov [Wed, 12 Jan 2011 13:57:18 +0000 (15:57 +0200)]
slirp: Use strcasecmp() to check tftp mode, tsize
According to RFC 1350 (TFTP Revision 2) the mode field can contain any
combination of upper and lower case; also RFC 2349 propagates that the
transfer size option ("tsize") is case in-sensitive too.
Current implementation of embedded TFTP server missed that what does
mess some TFTP clients. Fixed by using STRCASECMP(3) in the required
places.
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