Add a few DISAS_TARGET_* aliases to reduce the number of
calls to gen_eob() and gen_eob_inhibit_irq(). So far,
only update i386_tr_translate_insn for exiting the block
because of single-step or previous inhibit irq.
target/i386: Remove cur_eip argument to gen_exception
All callers pass s->base.pc_next - s->cs_base, which we can just
as well compute within the function. Note the special case of
EXCP_VSYSCALL in which s->cs_base wasn't subtracted, but cs_base
is always zero in 64-bit mode, when vsyscall is used.
Instead of returning the new pc, which is present in
DisasContext, return true if an insn was translated.
This is false when we detect a page crossing and must
undo the insn under translation.
There are cases that malicious virtual machine can cause CPU stuck (due
to event windows don't open up), e.g., infinite loop in microcode when
nested #AC (CVE-2015-5307). No event window means no event (NMI, SMI and
IRQ) can be delivered. It leads the CPU to be unavailable to host or
other VMs. Notify VM exit is introduced to mitigate such kind of
attacks, which will generate a VM exit if no event window occurs in VM
non-root mode for a specified amount of time (notify window).
A new KVM capability KVM_CAP_X86_NOTIFY_VMEXIT is exposed to user space
so that the user can query the capability and set the expected notify
window when creating VMs. The format of the argument when enabling this
capability is as follows:
Bit 63:32 - notify window specified in qemu command
Bit 31:0 - some flags (e.g. KVM_X86_NOTIFY_VMEXIT_ENABLED is set to
enable the feature.)
Users can configure the feature by a new (x86 only) accel property:
qemu -accel kvm,notify-vmexit=run|internal-error|disable,notify-window=n
The default option of notify-vmexit is run, which will enable the
capability and do nothing if the exit happens. The internal-error option
raises a KVM internal error if it happens. The disable option does not
enable the capability. The default value of notify-window is 0. It is valid
only when notify-vmexit is not disabled. The valid range of notify-window
is non-negative. It is even safe to set it to zero since there's an
internal hardware threshold to be added to ensure no false positive.
Because a notify VM exit may happen with VM_CONTEXT_INVALID set in exit
qualification (no cases are anticipated that would set this bit), which
means VM context is corrupted. It would be reflected in the flags of
KVM_EXIT_NOTIFY exit. If KVM_NOTIFY_CONTEXT_INVALID bit is set, raise a KVM
internal error unconditionally.
Paolo Bonzini [Thu, 29 Sep 2022 07:20:12 +0000 (15:20 +0800)]
kvm: allow target-specific accelerator properties
Several hypervisor capabilities in KVM are target-specific. When exposed
to QEMU users as accelerator properties (i.e. -accel kvm,prop=value), they
should not be available for all targets.
Add a hook for targets to add their own properties to -accel kvm, for
now no such property is defined.
i386: kvm: extend kvm_{get, put}_vcpu_events to support pending triple fault
For the direct triple faults, i.e. hardware detected and KVM morphed
to VM-Exit, KVM will never lose them. But for triple faults sythesized
by KVM, e.g. the RSM path, if KVM exits to userspace before the request
is serviced, userspace could migrate the VM and lose the triple fault.
A new flag KVM_VCPUEVENT_VALID_TRIPLE_FAULT is defined to signal that
the event.triple_fault_pending field contains a valid state if the
KVM_CAP_X86_TRIPLE_FAULT_EVENT capability is enabled.
Stefan Hajnoczi [Thu, 6 Oct 2022 11:11:56 +0000 (07:11 -0400)]
Merge tag 'pull-testing-gdbstub-plugins-gitdm-061022-3' of https://github.com/stsquad/qemu into staging
testing, gdbstub, plugin and gitdm updates
- cleanup scripts/ci/setup in advance of ppc64 runner
- ensure detected gdb reported to TCG tests
- update hexagon container with build deps
- move alpine container to tagged release
- fix overflow during qos-test test tree iteration
- allow bios blobs to be built with test cross compilers
- introduce monitor_puts for plain strings
- share disas code between monitor and plugins
- fix bug in execlog plugin
- add more tcg plugin documentation, reorg
- fix link to semihosting spec
- re-factor gdbstub to use AccelClass/Ops
- many gitdm updates
- fix race with plugin mutex lock and linux-user fork()
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# gpg: Signature made Thu 06 Oct 2022 06:54:30 EDT
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-testing-gdbstub-plugins-gitdm-061022-3' of https://github.com/stsquad/qemu: (52 commits)
plugins: add [pre|post]fork helpers to linux-user
contrib/gitdm: add Université Grenoble Alpes
contrib/gitdm: add Simon to individual contributors
contrib/gitdm: add China Telecom to the domain map
contrib/gitdm: add ISCAS to the academics group
contrib/gitdm: add WANG Xuerui to individual contributers
contrib/gitdm: add Paul to individual contributors
contrib/gitdm: add mapping for Loongson Technology
accel/kvm: move kvm_update_guest_debug to inline stub
gdbstub: move guest debug support check to ops
gdbstub: move breakpoint logic to accel ops
gdbstub: move sstep flags probing into AccelClass
gdbstub: move into its own sub directory
semihosting: update link to spec
docs/devel: document the test plugins
contrib/plugins: reset skip when matching in execlog
docs/devel: move API to end of tcg-plugins.rst
docs/devel: clean-up qemu invocations in tcg-plugins
plugins: Assert mmu_idx in range before use in qemu_plugin_get_hwaddr
plugins: extend execlog to filter matches
...
Alex Bennée [Thu, 29 Sep 2022 11:42:24 +0000 (12:42 +0100)]
gdbstub: move breakpoint logic to accel ops
As HW virtualization requires specific support to handle breakpoints
lets push out special casing out of the core gdbstub code and into
AccelOpsClass. This will make it easier to add other accelerator
support and reduces some of the stub shenanigans.
Alex Bennée [Thu, 29 Sep 2022 11:42:23 +0000 (12:42 +0100)]
gdbstub: move sstep flags probing into AccelClass
The support of single-stepping is very much dependent on support from
the accelerator we are using. To avoid special casing in gdbstub move
the probing out to an AccelClass function so future accelerators can
put their code there.
Alex Bennée [Thu, 29 Sep 2022 11:42:22 +0000 (12:42 +0100)]
gdbstub: move into its own sub directory
This is in preparation of future refactoring as well as cleaning up
the source tree. Aside from the minor tweaks to meson and trace.h this
is pure code motion.
Alex Bennée [Thu, 29 Sep 2022 11:42:19 +0000 (12:42 +0100)]
contrib/plugins: reset skip when matching in execlog
The purpose of the matches was to only track the execution of
instructions we care about. Without resetting skip to the value at the
start of the block we end up dumping all instructions after the match
with the consequent load on the instrumentation.
Alex Bennée [Thu, 29 Sep 2022 11:42:18 +0000 (12:42 +0100)]
docs/devel: move API to end of tcg-plugins.rst
The API documentation is quite dry and doesn't flow nicely with the
rest of the document. Move it to its own section at the bottom along
with a little leader text to remind people to update it.
Alex Bennée [Thu, 29 Sep 2022 11:42:17 +0000 (12:42 +0100)]
docs/devel: clean-up qemu invocations in tcg-plugins
We currently have the final binaries in the root of the build dir so
the build prefix is superfluous. Additionally add a shell prompt to be
more in line with the rest of the code.
Alex Bennée [Thu, 29 Sep 2022 11:42:14 +0000 (12:42 +0100)]
disas: use result of ->read_memory_func
This gets especially confusing if you start plugging in host addresses
from a trace and you wonder why the output keeps changing. Report when
read_memory_func fails instead of blindly disassembling the buffer
contents.
Alex Bennée [Thu, 29 Sep 2022 11:42:13 +0000 (12:42 +0100)]
disas: generalise plugin_printf and use for monitor_disas
Rather than assembling our output piecemeal lets use the same approach
as the plugin disas interface to build the disassembly string before
printing it.
Paolo Bonzini [Thu, 29 Sep 2022 11:42:08 +0000 (12:42 +0100)]
configure: build ROMs with container-based cross compilers
s390-ccw remains a bit more complex, because the -march=z900 test is done
only for the native cross compiler. Otherwise, all that is needed is
to pass the (now mandatory) target argument to write_target_makefile.
Paolo Bonzini [Thu, 29 Sep 2022 11:42:04 +0000 (12:42 +0100)]
tests/tcg: move compiler tests to Makefiles
Further decoupling of tests/tcg from the main QEMU Makefile, and making
the build more similar between the cross compiler case and the vetted
container images.
Paolo Bonzini [Thu, 29 Sep 2022 11:42:03 +0000 (12:42 +0100)]
tests/tcg: clean up calls to run-test
Almost all invocations of run-test have either "$* on $(TARGET_NAME)"
or "$< on $(TARGET_NAME)" as the last argument. So provide a default
test name, while allowing an escape hatch for custom names.
As an additional simplification, remove the need to do shell quoting.
Paolo Bonzini [Thu, 29 Sep 2022 11:42:02 +0000 (12:42 +0100)]
tests/tcg: unify ppc64 and ppc64le Makefiles
Make tests/tcg/ppc64le include tests/tcg/ppc64 instead of duplicating
the rules. Because the ppc64le vpath includes tests/tcg/ppc64 but
not vice versa, the tests have to be moved from tests/tcg/ppc64le/
to tests/tcg/ppc64.
Paolo Bonzini [Thu, 29 Sep 2022 11:42:00 +0000 (12:42 +0100)]
tests/tcg: remove -f from Makefile invocation
Instead of linking tests/tcg/Makefile.target into the build tree, name
the symbolic link "Makefile" and create it in every target subdirectory.
This makes it possible to just invoke "make" in tests/tcg subdirectories.
Paolo Bonzini [Thu, 29 Sep 2022 11:41:59 +0000 (12:41 +0100)]
tests: simplify Makefile invocation for tests/tcg
Remove the DOCKER_SCRIPT and TARGET variable from the Makefile invocation
for tests/tcg. For DOCKER_SCRIPT, resolve the path to docker.py in configure;
for TARGET, move it to config-$(TARGET).mak and use a symbolic link to break
the cycle.
The symbolic link is still needed because tests/tcg includes dummy config files
for targets that are not buildable. Once that is cleaned up, the symbolic link
will go away too.
Paolo Bonzini [Thu, 29 Sep 2022 11:41:58 +0000 (12:41 +0100)]
configure: store container engine in config-host.mak
In preparation for removing $(DOCKER_SCRIPT) from the tests/tcg configuration
files, have Make use the same container engine that had been probed at
configure time.
Paolo Bonzini [Thu, 29 Sep 2022 11:41:54 +0000 (12:41 +0100)]
pc-bios/s390-ccw: detect CC options just once
In preparation for adding Docker container support, detect compiler options
just once rather than once per Make run; container startup overhead is
substantial and doing the detection just once makes things faster.
Paolo Bonzini [Thu, 29 Sep 2022 11:41:53 +0000 (12:41 +0100)]
pc-bios/optionrom: detect CC options just once
In preparation for adding Docker container support, detect compiler options
just once rather than once per Make run; container startup overhead is
substantial and doing the detection just once makes things faster.
Alex Bennée [Thu, 29 Sep 2022 11:41:51 +0000 (12:41 +0100)]
tests/qtest: bump up QOS_PATH_MAX_ELEMENT_SIZE
It seems the depth of stack we need to support can vary depending on
the order of the init constructors getting called. It seems
--enable-lto shuffles things around just enough to push you over the
limit.
Alex Bennée [Thu, 29 Sep 2022 11:41:50 +0000 (12:41 +0100)]
tests/docker: move alpine from edge to tagged release
Tracking alpine-edge like debian-sid is a moving target. Usually such
rolling releases are marked as "allow_failure: true" in our CI.
However as alpine presents a musl based distro and provides useful
extra coverage lets track a release branch instead to avoid random
breakages.
Anton Johansson [Thu, 29 Sep 2022 11:41:46 +0000 (12:41 +0100)]
target/hexagon: add flex/bison/glib2 to qemu.yml
Note, the glib2-native mapping exists separately from the normal glib2
mapping. The latter uses a `foreign` cross-policy-default, and
libvirt-ci is not able to support package mappings for multiple
cross-compilation policies.
XEN hypervisor is only available in ARM and x86, but the yaml only
checked if the architecture is different from s390x, changed it to
a more accurate test.
Tested this change on a Ubuntu 20.04 ppc64le.
Stefan Hajnoczi [Wed, 5 Oct 2022 14:17:32 +0000 (10:17 -0400)]
Merge tag 'pull-hex-20221003' of https://github.com/quic/qemu into staging
Make store handling faster and more robust
Bug fix in gen_tcg_funcs.py
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# gpg: Signature made Mon 03 Oct 2022 14:08:46 EDT
# gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422
* tag 'pull-hex-20221003' of https://github.com/quic/qemu:
Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEW
Hexagon (target/hexagon) move store size tracking to translation
Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]
Hexagon (target/hexagon) add instruction attributes from archlib
Stefan Hajnoczi [Wed, 5 Oct 2022 14:17:02 +0000 (10:17 -0400)]
Merge tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu into staging
Cache CPUClass for use in hot code paths.
Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full.
Add generic support for TARGET_TB_PCREL.
tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07
target/sh4: Fix TB_FLAG_UNALIGN
* tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu:
target/sh4: Fix TB_FLAG_UNALIGN
tcg/ppc: Optimize 26-bit jumps
accel/tcg: Introduce TARGET_TB_PCREL
accel/tcg: Introduce tb_pc and log_pc
hw/core: Add CPUClass.get_pc
include/hw/core: Create struct CPUJumpCache
accel/tcg: Inline tb_flush_jmp_cache
accel/tcg: Do not align tb->page_addr[0]
accel/tcg: Use DisasContextBase in plugin_gen_tb_start
accel/tcg: Use bool for page_find_alloc
accel/tcg: Remove PageDesc code_bitmap
include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
accel/tcg: Introduce tlb_set_page_full
accel/tcg: Introduce probe_access_full
accel/tcg: Suppress auto-invalidate in probe_access_internal
accel/tcg: Drop addr member from SavedIOTLB
accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
cputlb: used cached CPUClass in our hot-paths
hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
cpu: cache CPUClass in CPUState for hot code paths
Rename all DELAY_SLOT_* and GUSA_* defines to emphasize
that they are included in TB_FLAGs. Add aliases for the
FPSCR and SR bits that are included in TB_FLAGS, so that
we don't accidentally reassign those bits.
Fixes: 4da06fb3062 ("target/sh4: Implement prctl_unalign_sigbus")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/856 Reviewed-by: Yoshinori Sato <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
PowerPC64 processors handle direct branches better than indirect
ones, resulting in less stalled cycles and branch misses.
However, PPC's tb_target_set_jmp_target() was only using direct
branches for 16-bit jumps, while PowerPC64's unconditional branch
instructions are able to handle displacements of up to 26 bits.
To take advantage of this, now jumps whose displacements fit in
between 17 and 26 bits are also converted to direct branches.
Populate this new method for all targets. Always match
the result that would be given by cpu_get_tb_cpu_state,
as we will want these values to correspond in the logs.
This function has two users, who use it incompatibly.
In tlb_flush_page_by_mmuidx_async_0, when flushing a
single page, we need to flush exactly two pages.
In tlb_flush_range_by_mmuidx_async_0, when flushing a
range of pages, we need to flush N+1 pages.
This avoids double-flushing of jmp cache pages in a range.
Let tb->page_addr[0] contain the address of the first byte of the
translated block, rather than the address of the page containing the
start of the translated block. We need to recover this value anyway
at various points, and it is easier to discard a page offset when it
is not needed, which happens naturally via the existing find_page shift.
* tag 'trivial-branch-for-7.2-pull-request' of https://gitlab.com/laurent_vivier/qemu:
docs: Update TPM documentation for usage of a TPM 2
Use g_new() & friends where that makes obvious sense
Drop superfluous conditionals around g_free()
block/qcow2-bitmap: Add missing cast to silent GCC error
checkpatch: ignore target/hexagon/imported/* files
mem/cxl_type3: fix GPF DVSEC
.gitignore: add .cache/ to .gitignore
hw/virtio/vhost-shadow-virtqueue: Silence GCC error "maybe-uninitialized"
Stefan Hajnoczi [Tue, 4 Oct 2022 18:03:21 +0000 (14:03 -0400)]
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* x86: re-enable rng seeding via SetupData
* x86: reinitialize RNG seed on system reboot and after kernel load
* qboot: rebuild based on latest commit
* watchdog: remove -watchdog option
* update Meson to 0.61.5, move more configure tests
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
x86: re-initialize RNG seed when selecting kernel
target/i386/kvm: fix kvmclock_current_nsec: Assertion `time.tsc_timestamp <= migration_tsc' failed
configure, meson: move linker flag detection to meson
configure, meson: move C++ compiler detection to meson.build
meson: multiple names can be passed to dependency()
meson: require 0.61.3
meson: -display dbus and CFI are incompatible
ui: fix path to dbus-display1.h
watchdog: remove -watchdog option
configure: do not invoke as/ld directly for pc-bios/optionrom
qboot: rebuild based on latest commit
x86: re-enable rng seeding via SetupData
x86: reinitialize RNG seed on system reboot
x86: use typedef for SetupData struct
x86: return modified setup_data only if read as memory, not as file
accel/tcg: Use DisasContextBase in plugin_gen_tb_start
Use the pc coming from db->pc_first rather than the TB.
Use the cached host_addr rather than re-computing for the
first page. We still need a separate lookup for the second
page because it won't be computed for DisasContextBase until
the translator actually performs a read from the page.
Now that we have collected all of the page data into
CPUTLBEntryFull, provide an interface to record that
all in one go, instead of using 4 arguments. This interface
allows CPUTLBEntryFull to be extended without having to
change the number of arguments.
Add an interface to return the CPUTLBEntryFull struct
that goes with the lookup. The result is not intended
to be valid across multiple lookups, so the user must
use the results immediately.
accel/tcg: Suppress auto-invalidate in probe_access_internal
When PAGE_WRITE_INV is set when calling tlb_set_page,
we immediately set TLB_INVALID_MASK in order to force
tlb_fill to be called on the next lookup. Here in
probe_access_internal, we have just called tlb_fill
and eliminated true misses, thus the lookup must be valid.
This allows us to remove a warning comment from s390x.
There doesn't seem to be a reason to change the code though.
accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
This structure will shortly contain more than just
data for accessing MMIO. Rename the 'addr' member
to 'xlat_section' to more clearly indicate its purpose.
Alex Bennée [Fri, 23 Sep 2022 08:47:59 +0000 (10:47 +0200)]
cpu: cache CPUClass in CPUState for hot code paths
The class cast checkers are quite expensive and always on (unlike the
dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To
avoid the overhead of repeatedly checking something which should never
change we cache the CPUClass reference for use in the hot code paths.
Stefan Berger [Tue, 27 Sep 2022 12:21:46 +0000 (08:21 -0400)]
docs: Update TPM documentation for usage of a TPM 2
Update the TPM documentation for usage of a TPM 2 rather than a TPM 1.2.
Adjust the command lines and expected outputs inside the VM accordingly.
Update the command line to start a TPM 2 with swtpm.
Use g_new() & friends where that makes obvious sense
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer,
for two reasons. One, it catches multiplication overflowing size_t.
Two, it returns T * rather than void *, which lets the compiler catch
more type errors.
This commit only touches allocations with size arguments of the form
sizeof(T).
block/qcow2-bitmap: Add missing cast to silent GCC error
Commit d1258dd0c8 ("qcow2: autoloading dirty bitmaps") added the
set_readonly_helper() GFunc handler, correctly casting the gpointer
user_data in both the g_slist_foreach() caller and the handler.
Few commits later (commit 1b6b0562db), the handler is reused in
qcow2_reopen_bitmaps_rw() but missing the gpointer cast, resulting
in the following error when using Homebrew GCC 12.2.0:
[2/658] Compiling C object libblock.fa.p/block_qcow2-bitmap.c.o
../../block/qcow2-bitmap.c: In function 'qcow2_reopen_bitmaps_rw':
../../block/qcow2-bitmap.c:1211:60: error: incompatible type for argument 3 of 'g_slist_foreach'
1211 | g_slist_foreach(ro_dirty_bitmaps, set_readonly_helper, false);
| ^~~~~
| |
| _Bool
In file included from /opt/homebrew/Cellar/glib/2.72.3_1/include/glib-2.0/glib/gmain.h:26,
from /opt/homebrew/Cellar/glib/2.72.3_1/include/glib-2.0/glib/giochannel.h:33,
from /opt/homebrew/Cellar/glib/2.72.3_1/include/glib-2.0/glib.h:54,
from /Users/philmd/source/qemu/include/glib-compat.h:32,
from /Users/philmd/source/qemu/include/qemu/osdep.h:144,
from ../../block/qcow2-bitmap.c:28:
/opt/homebrew/Cellar/glib/2.72.3_1/include/glib-2.0/glib/gslist.h:127:61: note: expected 'gpointer' {aka 'void *'} but argument is of type '_Bool'
127 | gpointer user_data);
| ~~~~~~~~~~~~~~~~~~^~~~~~~~~
At top level:
FAILED: libblock.fa.p/block_qcow2-bitmap.c.o
* tag 'for-upstream' of git://repo.or.cz/qemu/kevin:
hw/ide/core.c: Implement ATA INITIALIZE_DEVICE_PARAMETERS command
tests/qtest/ide-test: Verify that DIAGNOSTIC clears DEV to zero
hw/ide/core: Clear LBA and drive bits for EXECUTE DEVICE DIAGNOSTIC
tests/qtest/ide-test.c: Create disk image for use as a secondary
piix_ide_reset: Use pci_set_* functions instead of direct access
block: use the request length for iov alignment
block: move bdrv_qiov_is_aligned to file-posix
iotests/backing-file-invalidation: Add new test
block/qed: Keep auto_backing_file if possible
block/qcow2: Keep auto_backing_file if possible
gluster: stop using .bdrv_needs_filename
block: make serializing requests functions 'void'
block: use bdrv_is_sg() helper instead of raw bs->sg reading
block: add missed block_acct_setup with new block device init procedure
block: pass OnOffAuto instead of bool to block_acct_setup()
qemu-img: Wean documentation and help output off '?' for help
block/qcow2-bitmap: Add missing cast to silent GCC error
qcow2: fix memory leak in qcow2_read_extensions
Stefan Hajnoczi [Mon, 3 Oct 2022 19:00:36 +0000 (15:00 -0400)]
Merge tag 'pull-target-arm-20220930' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
PMCNTENSET_EL0 or PMCNTENCLR_EL0
* Make writes to MDCR_EL3 use PMU start/finish calls
* Let AArch32 write to SDCR.SCCD
* Rearrange cpu64.c so all the CPU initfns are together
* hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
* hw/arm/virt: fix some minor issues with generated device tree
* Fix regression where EL3 could not write to SP_EL1 if there is no EL2
* tag 'pull-target-arm-20220930' of https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
hw/arm/virt: Fix devicetree warning about the SMMU node
hw/arm/virt: Use "msi-map" devicetree property for PCI
hw/arm/virt: Fix devicetree warning about the GIC node
hw/arm/virt: Fix devicetree warning about the root node
hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
target/arm: Rearrange cpu64.c so all the CPU initfns are together
target/arm: Update SDCR_VALID_MASK to include SCCD
target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEW
Hexagon instructions with the A_CVI_NEW attribute produce a vector value
that can be used in the same packet. The python function responsible for
generating code for such instructions has a typo ("if" instead of
"elif"), which makes genptr_dst_write_ext() be executed twice, thus also
generating the same tcg code twice. Fortunately, this doesn't cause any
problems for correctness, but it is less efficient than it could be. Fix
it by using an "elif" and avoiding the unnecessary extra code gen.
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