Tom Musta [Tue, 22 Oct 2013 11:09:35 +0000 (22:09 +1100)]
Add xxpermdi
This patch adds the xxpermdi instruction. The instruction
uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
and BX). This results in overloading of the opcode table
with aliases, which can be seen in the GEN_XX3FORM_DM
macro.
Tom Musta [Tue, 22 Oct 2013 11:07:41 +0000 (22:07 +1100)]
Add VSR to Global Registers
This patch adds VSX VSRs to the the list of global register indices.
More specifically, it adds the lower halves of the first 32 VSRs to
the list of global register indices. The upper halves of the first
32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs
are already defined via the cpu_avrh[] and cpu_avrl[] arrays.
Tom Musta [Tue, 22 Oct 2013 11:06:46 +0000 (22:06 +1100)]
Add VSX Instruction Decoders
This patch adds decoders for the VSX fields XT, XS, XA, XB and
DM. The first four are split fields and a general helper for
these types of fields is also added.
Tom Musta [Tue, 22 Oct 2013 11:05:46 +0000 (22:05 +1100)]
Declare and Enable VSX
This patch adds the flag POWERPC_FLAG_VSX to the list of defined
flags and also adds this flag to the list of supported features of
the Power7 and Power8 CPUs. Additionally, the VSX instructions
are added to the list of TCG-enabled instruction.
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU list. Also, new CPU versions of already supported
CPU won't break the existing code.
This adds PVR value/mask support for KVM, i.e. for -cpu host option.
As CPU family class name for POWER7 is "POWER7-family", there is no need
to touch aliases.
Greg Kurz [Wed, 11 Dec 2013 13:15:34 +0000 (14:15 +0100)]
target-ppc: add stubs for KVM breakpoints
The latest update to v3.13-rc3 (bf63839f) breaks the
ppc build with KVM:
kvm-all.o: In function `kvm_update_guest_debug':
kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'
kvm-all.o: In function `kvm_insert_breakpoint':
kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint'
kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint'
kvm-all.o: In function `kvm_remove_breakpoint':
kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint'
kvm-all.o: In function `kvm_remove_all_breakpoints':
kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints'
Anthony Liguori [Thu, 19 Dec 2013 19:56:33 +0000 (11:56 -0800)]
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131217' into staging
target-arm queue:
* AES instruction support for 32 bit ARM
* pflash01: much better emulation of 2x16bit and similar configs
where multiple flash devices are banked together
* fixed CBAR handling on Zynq, Highbank
* initial AArch64 KVM control support
* first two chunks of patches for A64 instruction emulation
* new board: canon-a1100 (Canon DIGIC SoC)
* new board: cubieboard (Allwinner A10 SoC)
# gpg: Signature made Tue 17 Dec 2013 12:18:39 PM PST using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found
# By Alexander Graf (14) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-20131217: (62 commits)
MAINTAINERS: add myself to maintain allwinner-a10
hw/arm: add cubieboard support
hw/arm: add allwinner a10 SoC support
hw/intc: add allwinner A10 interrupt controller
hw/timer: add allwinner a10 timer
vmstate: Add support for an array of ptimer_state *
MAINTAINERS: Document 'Canon DIGIC' machine
hw/arm/digic: add NOR ROM support
hw/arm/digic: add UART support
hw/arm/digic: add timer support
hw/arm/digic: prepare DIGIC-based boards support
hw/arm: add very initial support for Canon DIGIC SoC
target-arm: A64: add support for logical (immediate) insns
target-arm: A64: add support for 1-src CLS insn
host-utils: add clrsb32/64 - count leading redundant sign bits
target-arm: A64: add support for bitfield insns
target-arm: A64: add support for 1-src REV insns
target-arm: A64: add support for 1-src RBIT insn
target-arm: A64: add support for 1-src data processing and CLZ
target-arm: A64: add support for 2-src shift reg insns
...
Thomas Huth [Tue, 17 Dec 2013 18:50:01 +0000 (19:50 +0100)]
s390x/ioinst: CHSC has to set a condition code
I missed to set the CC in the CHSC instruction when I refactored
the CC setting in the IO instructions with the following commit: 5d9bf1c07c1369ab3506fc82cc65a10f4415d867
s390/ioinst: Moved the CC setting to the IO instruction handlers
This patch now restores the correct behaviour of CHSC by setting the
condition code 0 at the end of the instruction.
Thomas Huth [Tue, 17 Dec 2013 13:22:08 +0000 (14:22 +0100)]
s390x/kvm: Simplified the calculation of the SIGP order code
We've already got a helper function for calculating the
base/displacement of RS formatted instructions, so we can
get rid of the manual calculation of the SIGP order code.
Cornelia Huck [Tue, 17 Dec 2013 17:27:33 +0000 (18:27 +0100)]
s390x/kvm: Fix diagnose handling.
The instruction intercept handler for diagnose used only the displacement
when trying to calculate the function code. This is only correct for base
0, however; we need to perform a complete base/displacement address
calculation and use bits 48-63 as the function code.
Peter Maydell [Tue, 17 Dec 2013 19:42:37 +0000 (19:42 +0000)]
vmstate: Add support for an array of ptimer_state *
Add support for defining a vmstate field which is an array
of pointers to structures, and use this to define a
VMSTATE_PTIMER_ARRAY() which allows an array of ptimer_state*
to be used by devices.
Antony Pavlov [Tue, 17 Dec 2013 19:42:36 +0000 (19:42 +0000)]
hw/arm: add very initial support for Canon DIGIC SoC
DIGIC is Canon Inc.'s name for a family of SoC
for digital cameras and camcorders.
There is no publicly available specification for
DIGIC chips. All information about DIGIC chip
internals is based on reverse engineering efforts
made by CHDK (http://chdk.wikia.com) and
Magic Lantern (http://www.magiclantern.fm) projects
contributors.
Alexander Graf [Tue, 17 Dec 2013 19:42:36 +0000 (19:42 +0000)]
target-arm: A64: add support for logical (immediate) insns
This patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted to new decoder, function renaming,
removed a TCG temp variable] Signed-off-by: Claudio Fontana <[email protected]>
[PMM: cleaned up some unnecessary code in logic_imm_decode_wmask
and added clarifying commentary on what it's actually doing.
Dropped an ext32u that's not needed if we've just done an AND.] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:35 +0000 (19:42 +0000)]
target-arm: A64: add support for 1-src RBIT insn
This adds support for the C5.6.147 RBIT instruction.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted to new decoder, use bswap64,
make RBIT part standalone from the rest of the patch,
splitting REV into a separate patch] Signed-off-by: Claudio Fontana <[email protected]> Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:34 +0000 (19:42 +0000)]
target-arm: A64: add support for 2-src data processing and DIV
This patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted to new decoder adding the 2-src decoding level,
always zero-extend result in 32bit mode] Signed-off-by: Claudio Fontana <[email protected]> Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:34 +0000 (19:42 +0000)]
target-arm: A64: add support for EXTR
This patch adds emulation support for the EXTR instruction.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted for new decoder, removed a few temporaries,
fixed the 32bit bug, added checks for more
unallocated cases]
Alexander Graf [Tue, 17 Dec 2013 19:42:34 +0000 (19:42 +0000)]
target-arm: A64: add support for logical (shifted register)
Add support for the instructions described in "C3.5.10 Logical
(shifted register)".
We store the flags in the same locations as the 32 bit decoder.
This is slightly awkward when calculating 64 bit results, but seems
a better tradeoff than having to rework the whole 32 bit decoder
and also make 32 bit result calculation in A64 awkward.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: some refactoring to avoid hidden allocation of temps,
rework flags, use enums for shift types,
renaming of functions] Signed-off-by: Claudio Fontana <[email protected]>
[PMM: Use TCG's andc/orc/eqv ops rather than manually inverting] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Claudio Fontana [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for conditional select
This patch adds support for the instruction group "C3.5.6
Conditional select": CSEL, CSINC, CSINV, CSNEG.
Signed-off-by: Claudio Fontana <[email protected]>
[PMM: Improved code generated in the nomatch case as per RTH suggestions] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for compare and branch imm
This patch adds emulation for the compare and branch insns,
CBZ and CBNZ.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted to new decoder,
compare with immediate 0,
introduce read_cpu_reg to get the 0 extension on (!sf)] Signed-off-by: Claudio Fontana <[email protected]> Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for 'test and branch' imm
This patch adds emulation for the test and branch insns,
TBZ and TBNZ.
Signed-off-by: Alexander Graf <[email protected]>
[claudio:
adapted for new decoder
always compare with 0
remove a TCG temporary
] Signed-off-by: Claudio Fontana <[email protected]> Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for conditional branches
This patch adds emulation for the conditional branch (b.cond) instruction.
Signed-off-by: Alexander Graf <[email protected]>
[claudio: adapted to new decoder structure,
reused arm infrastructure for checking the flags] Signed-off-by: Claudio Fontana <[email protected]> Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for BR, BLR and RET insns
Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
and DPRS (which are system mode only).
Alexander Graf [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: add support for B and BL insns
Implement the B and BL instructions (PC relative branches and calls).
For convenience in managing TCG temporaries which might be generated
if a source register is the zero-register XZR, we provide a simple
mechanism for creating a new temp which is automatically freed at the
end of decode of the instruction.
Claudio Fontana [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: expand decoding skeleton for system instructions
Decode the various kinds of system instructions:
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
sync instructions, which include CLREX, DSB, DMB, ISB
msr_i, which move immediate to processor state field
sys, which include all SYS and SYSL instructions
msr, which move from a gp register to a system register
mrs, which move from a system register to a gp register
Provide implementations where they are trivial nops.
Claudio Fontana [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: provide skeleton for a64 insn decoding
Provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) section C3.
Alexander Graf [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: add stubs for a64 specific helpers
We will need helpers that only make sense with AArch64. Add
helper-a64.{c,h} files as stubs that we can fill with these
helpers in the following patches.
Peter Maydell [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
target-arm: A64: provide functions for accessing FPCR and FPSR
The information which AArch32 holds in the FPSCR is split for
AArch64 into two logically distinct registers, FPSR and FPCR.
Since they are carefully arranged to use non-overlapping bits,
we leave the underlying state in the same place, and provide
accessor functions which just update the appropriate bits
via vfp_get_fpscr() and vfp_set_fpscr().
Alexander Graf [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
target-arm: A64: add set_pc cpu method
When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch64 CPUs.
This covers user-mode, but for system mode emulation we will
need to check if the CPU is in an AArch32 execution state.
Peter Maydell [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()
The A32/T32 gen_intermediate_code_internal() is complicated because it
has to deal with:
* conditionally executed instructions
* Thumb IT blocks
* kernel helper page
* M profile exception-exit special casing
None of these apply to A64, so putting the "this is A64 so
call the A64 decoder" check in the middle of the A32/T32
loop is confusing and means the A64 decoder's handling of
things like conditional jump and singlestepping has to take
account of the conditional-execution jumps the main loop
might emit.
Refactor the code to give A64 its own gen_intermediate_code_internal
function instead.
Peter Maydell [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
default-configs: Add config for aarch64-softmmu
Add a config for aarch64-softmmu; this enables building of this target.
The resulting executable doesn't know about any 64 bit CPUs, but all
the 32 bit CPUs and board models work.
Mian M. Hamayun [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
hw/arm/boot: Add boot support for AArch64 processor
This commit adds support for booting a single AArch64 CPU by setting
appropriate registers. The bootloader includes placeholders for Board-ID
that are used to implement uniform indexing across different bootloaders.
Signed-off-by: Mian M. Hamayun <[email protected]> Signed-off-by: Peter Maydell <[email protected]>
Message-id: 1385645602[email protected]
[PMM:
* updated to use ARMInsnFixup style bootloader fragments
* dropped virt.c additions
* use runtime checks for "is this an AArch64 core" rather than ifdefs
* drop some unnecessary setting of registers in reset hook
] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Christoffer Dall <[email protected]>
Peter Maydell [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
hw/arm/boot: Allow easier swapping in of different loader code
For AArch64 we will obviously require a different set of
primary and secondary boot loader code fragments. However currently
we hardcode the offsets into the loader code where we must write
the entrypoint and other data into arm_load_kernel(). This makes it
hard to substitute a different loader fragment, so switch to a more
flexible scheme where instead of a raw array of instructions we use
an array of (instruction, fixup-type) pairs that indicate which
words need special action or data written into them.
Peter Maydell [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
configure: Enable KVM for aarch64 host/target combination
Enable KVM if the host and target CPU are both aarch64. Note
that host aarch64 + target arm is not valid for KVM acceleration:
the 64 bit kernel does not support the ioctl interface for
32 bit CPUs. 32 bit VMs on 64 bit hosts need to be created
using the 64 bit ioctl interface; when QEMU supports this it
will be on the arch64-softmmu target with a -cpu parameter for
a 32 bit CPU, which is still an aarch64/aarch64 combination
as far as configure is concerned.
Mian M. Hamayun [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
target-arm: Add minimal KVM AArch64 support
Add the bare minimum set of functions needed for control of an
AArch64 KVM vcpu:
* CPU initialization
* minimal get/put register functions which only handle the
basic state of the CPU
Signed-off-by: Mian M. Hamayun <[email protected]> Signed-off-by: Peter Maydell <[email protected]>
Message-id: 1385645602[email protected]
[PMM: significantly overhauled; most notably:
* code lives in kvm64.c rather than using #ifdefs
* support '-cpu host' rather than implicitly using whatever the
host's CPU is regardless of what the user requests
* fix bug attempting to get/set nonexistent X[31]
* fix bug writing 64 bit kernel pstate into uint32_t env field
] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Christoffer Dall <[email protected]>
Peter Maydell [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
target-arm: Clean up handling of AArch64 PSTATE
The env->pstate field is a little odd since it doesn't strictly
speaking represent an architectural register. However it's convenient
for QEMU to use it to hold the various PSTATE architectural bits
in the same format the architecture specifies for SPSR registers
(since this is the same format the kernel uses for signal handlers
and the KVM register). Add some structure to how we deal with it:
* document what env->pstate is
* add some #defines for various bits in it
* add helpers for reading/writing it taking account of caching
of NZCV, and use them where appropriate
* reset it on startup
Peter Maydell [Tue, 17 Dec 2013 19:42:29 +0000 (19:42 +0000)]
target-arm/kvm: Split 32 bit only code into its own file
Split ARM KVM support code which is 32 bit specific out into its
own file, which we only compile on 32 bit hosts. This will give
us a place to add the 64 bit support code without adding lots of
ifdefs to kvm.c.
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.
Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the intended value is now
actually used.
So I have kind of tested this. I booted an ARM kernel on Highbank with
the stock Highbank DTB. It doesn't boot (and I will be doing something
wrong), but before this patch I got this:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at /workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 __arm_ioremap_pfn_caller+0x180/0x198()
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.13.0-rc1-next-20131126-dirty #2
[<c0015164>] (unwind_backtrace) from [<c00118c0>] (show_stack+0x10/0x14)
[<c00118c0>] (show_stack) from [<c02bd5fc>] (dump_stack+0x78/0x90)
[<c02bd5fc>] (dump_stack) from [<c001f110>] (warn_slowpath_common+0x68/0x84)
[<c001f110>] (warn_slowpath_common) from [<c001f1f4>] (warn_slowpath_null+0x1c/0x24)
[<c001f1f4>] (warn_slowpath_null) from [<c0017c6c>] (__arm_ioremap_pfn_caller+0x180/0x198)
[<c0017c6c>] (__arm_ioremap_pfn_caller) from [<c0017cd8>] (__arm_ioremap_caller+0x54/0x5c)
[<c0017cd8>] (__arm_ioremap_caller) from [<c0017d10>] (__arm_ioremap+0x18/0x1c)
[<c0017d10>] (__arm_ioremap) from [<c03913c0>] (highbank_init_irq+0x34/0x8c)
[<c03913c0>] (highbank_init_irq) from [<c038c228>] (init_IRQ+0x28/0x2c)
[<c038c228>] (init_IRQ) from [<c03899ec>] (start_kernel+0x234/0x398)
[<c03899ec>] (start_kernel) from [<00008074>] (0x8074)
---[ end trace 3406ff24bd97382f ]---
Some processors (notably A9 within Highbank) define and use the
CP15 configuration base address (CBAR). This is vendor specific
so its best implemented as a CPU property (otherwise we would need
vendor specific child classes for every ARM implementation).
This patch prepares support for converting CBAR reset value to
a CPU property by moving the CP registration out of the CPU
init fn, as registration will need to happen at realize time
to pick up any property updates. The easiest way to do this
is via definition of a new ARM_FEATURE to flag the existence
of the register.
The cp15.c15 space is implementation defined. Currently there is a
dummy placeholder register RAZing it. Allow overriding of this RAZ
so implementations of specific registers can take precedence.
Roy Franz [Tue, 17 Dec 2013 19:42:27 +0000 (19:42 +0000)]
Fix NOR flash device ID reading
Fix NOR flash manufacturer and device ID reading. This now
properly takes into account device widths and device max widths
as required. The reading of these IDs uses the same max_width
dependent addressing as CFI queries.
The old code remains for chips that don't specify a device width,
as the new code relies on a device width being set in order to
properly operate. The existing code seems very broken.
Only ident0 and ident1 are used in the new code, as other fields
relate to the lock state of blocks in flash.
The VExpress flash configuration has been updated to match
the new code, as the existing definition was 'wrong' in order
to return the expected results with the broken device ID code.
Roy Franz [Tue, 17 Dec 2013 19:42:27 +0000 (19:42 +0000)]
Fix CFI query responses for NOR flash
This change fixes the CFI query responses to handle NOR device
widths that are different from the bank width. Support is also
added for multi-width devices in a x8 configuration. This is
typically x8/x16 devices, but the CFI specification mentions
x8/x32 devices so those should be supported as well if they
exist.
The query response data is now replicated per-device in the bank,
and is adjusted for x16 or x32 parts configured in x8 mode.
The existing code is left in place for boards that have not
been updated to specify an explicit device_width. The VExpress
board has been updated in an earlier patch in this series so
this is the only board currently affected.
Roy Franz [Tue, 17 Dec 2013 19:42:27 +0000 (19:42 +0000)]
Add max device width parameter for NOR devices
For handling CFI and device ID reads, we need to not only know the
width that a NOR flash device is configured for, but also its maximum
width. The maximum width addressing mode is used for multi-width
parts no matter which width they are configured for. The most common
case is x16 parts that also support x8 mode. When configured for x8
operation these devices respond to CFI and device ID requests differently
than native x8 NOR parts.
Roy Franz [Tue, 17 Dec 2013 19:42:26 +0000 (19:42 +0000)]
Set proper device-width for vexpress flash
Create vexpress specific pflash registration
function which properly configures the device-width
of 16 bits (2 bytes) for the NOR flash on the
vexpress platform. This change is required for
buffered flash writes to work properly.
Roy Franz [Tue, 17 Dec 2013 19:42:26 +0000 (19:42 +0000)]
return status for each NOR flash device
Now that we know how wide each flash device that makes up the bank is,
return status for each device in the bank. Leave existing code
that treats 32 bit wide banks as composed of two 16 bit devices as otherwise
we may break configurations that do not set the device_width propery.
Roy Franz [Tue, 17 Dec 2013 19:42:26 +0000 (19:42 +0000)]
Add device-width property to pflash_cfi01
The width of the devices that make up the flash interface
is required to mask certain commands, in particular the
write length for buffered writes. This length will be presented
to each device on the interface by the program writing the flash,
and the flash emulation code needs to be able to determine
the length of the write as recieved by each flash device.
The device-width defaults to the bank width which should
maintain existing behavior for platforms that don't need
this change.
This change is required to support buffered writes on the
vexpress platform that has a 32 bit flash interface with 2
16 bit devices on it.
I checked all qemu_opts_parse() invocations (and all drive_def()
invocations too, because it blindly forwards the former's retval). Only
the two above examples look problematic.
Anthony Liguori [Mon, 16 Dec 2013 17:44:13 +0000 (09:44 -0800)]
Merge remote-tracking branch 'spice/tags/pull-spice-1' into staging
Collection of little cleanups anf bugfixes.
nbd patches in preparation of spice-nbd.
# gpg: Signature made Mon 16 Dec 2013 01:27:45 AM PST using RSA key ID D3E87138
# gpg: Can't check signature: public key not found
# By Marc-André Lureau (12) and Gerd Hoffmann (4)
# Via Gerd Hoffmann
* spice/tags/pull-spice-1:
spice: stop server for qxl hard reset
spice: move spice_server_vm_{start,stop} calls into qemu_spice_display_*()
spice: move qemu_spice_display_*() from spice-graphics to spice-core
nbd: avoid uninitialized warnings
nbd: finish any pending coroutine
nbd: make nbd_client_session_close() idempotent
nbd: pass export name as init argument
nbd: don't change socket block during negotiate
Split nbd block client code
spice-char: implement chardev port event
char: add qemu_chr_fe_event()
include: add missing config-host.h include
qmp_change_blockdev() remove unused has_format
spice-char: remove unused field
vscclient: do not add a socket watch if there is not data to send
spice: flip streaming video mode to off by default
Anthony Liguori [Mon, 16 Dec 2013 17:43:27 +0000 (09:43 -0800)]
Merge remote-tracking branch 'kwolf/tags/for-anthony' into staging
Block patches
# gpg: Signature made Fri 13 Dec 2013 09:47:03 AM PST using RSA key ID C88F2FD6
# gpg: Can't check signature: public key not found
# By Peter Lieven (2) and others
# Via Kevin Wolf
* kwolf/tags/for-anthony:
blkdebug: Use QLIST_FOREACH_SAFE to resume IO
qemu-img: make progress output more accurate during convert
block: expect get_block_status errors in bdrv_make_zero
block/vvfat: Fix compiler warnings for OpenBSD
qapi-schema.json: Change 1.8 reference to 2.0
sheepdog: check if '-o redundancy' is passed from user
Gerd Hoffmann [Mon, 9 Dec 2013 15:03:49 +0000 (16:03 +0100)]
spice: stop server for qxl hard reset
Hard reset can happen at any time. We should be able to put qxl into a
known-good state no matter what. Stop spice server thread for reset so
it can't be confused by fetching stale commands lingering around in the
rings while we reset is ongoing.
Gerd Hoffmann [Mon, 2 Dec 2013 10:17:04 +0000 (11:17 +0100)]
spice: flip streaming video mode to off by default
Video streaming detection heuristics in spice-server have problems
keeping modern desktop animations (as done by gnome shell) and real
video playback apart. This leads to jpeg compression artefacts on
your desktop, due to spice using mjpeg to send what it thinks is
a video stream.
Turn off video detection by default to avoid these artifacts.
projects / qemu.git / log