]>
Git Repo - qemu.git/log
Andrew Melnychenko [Fri, 14 May 2021 11:48:34 +0000 (14:48 +0300)]
docs: Added eBPF documentation.
Signed-off-by: Yuri Benditovich <[email protected] >
Signed-off-by: Andrew Melnychenko <[email protected] >
Signed-off-by: Jason Wang <[email protected] >
Andrew Melnychenko [Fri, 14 May 2021 11:48:33 +0000 (14:48 +0300)]
virtio-net: Added eBPF RSS to virtio-net.
When RSS is enabled the device tries to load the eBPF program
to select RX virtqueue in the TUN. If eBPF can be loaded
the RSS will function also with vhost (works with kernel 5.8 and later).
Software RSS is used as a fallback with vhost=off when eBPF can't be loaded
or when hash population requested by the guest.
Signed-off-by: Yuri Benditovich <[email protected] >
Signed-off-by: Andrew Melnychenko <[email protected] >
Signed-off-by: Jason Wang <[email protected] >
Andrew Melnychenko [Fri, 14 May 2021 11:48:32 +0000 (14:48 +0300)]
ebpf: Added eBPF RSS loader.
Added function that loads RSS eBPF program.
Added stub functions for RSS eBPF loader.
Added meson and configuration options.
By default, eBPF feature enabled if libbpf is present in the build system.
libbpf checked in configuration shell script and meson script.
Signed-off-by: Yuri Benditovich <[email protected] >
Signed-off-by: Andrew Melnychenko <[email protected] >
Signed-off-by: Jason Wang <[email protected] >
Andrew Melnychenko [Fri, 14 May 2021 11:48:31 +0000 (14:48 +0300)]
ebpf: Added eBPF RSS program.
RSS program and Makefile to build it.
The bpftool used to generate '.h' file.
The data in that file may be loaded by libbpf.
EBPF compilation is not required for building qemu.
You can use Makefile if you need to regenerate rss.bpf.skeleton.h.
Signed-off-by: Yuri Benditovich <[email protected] >
Signed-off-by: Andrew Melnychenko <[email protected] >
Signed-off-by: Jason Wang <[email protected] >
Andrew Melnychenko [Fri, 14 May 2021 11:48:30 +0000 (14:48 +0300)]
net: Added SetSteeringEBPF method for NetClientState.
For now, that method supported only by Linux TAP.
Linux TAP uses TUNSETSTEERINGEBPF ioctl.
Signed-off-by: Andrew Melnychenko <[email protected] >
Signed-off-by: Jason Wang <[email protected] >
Andrew Melnychenko [Fri, 14 May 2021 11:48:29 +0000 (14:48 +0300)]
net/tap: Added TUNSETSTEERINGEBPF code.
Additional code that will be used for eBPF setting steering routine.
Signed-off-by: Andrew Melnychenko <[email protected] >
Signed-off-by: Jason Wang <[email protected] >
Peter Maydell [Tue, 25 May 2021 15:17:06 +0000 (16:17 +0100)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-
20210525 ' into staging
target-arm queue:
* Implement SVE2 emulation
* Implement integer matrix multiply accumulate
* Implement FEAT_TLBIOS
* Implement FEAT_TLBRANGE
* disas/libvixl: Protect C system header for C++ compiler
* Use correct SP in M-profile exception return
* AN524, AN547: Correct modelling of internal SRAMs
* hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic
* hw/arm/smmuv3: Another range invalidation fix
# gpg: Signature made Tue 25 May 2021 16:02:25 BST
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "
[email protected] "
# gpg: Good signature from "Peter Maydell <
[email protected] >" [ultimate]
# gpg: aka "Peter Maydell <
[email protected] >" [ultimate]
# gpg: aka "Peter Maydell <
[email protected] >" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-
20210525 : (114 commits)
target/arm: Enable SVE2 and related extensions
linux-user/aarch64: Enable hwcap bits for sve2 and related extensions
target/arm: Implement integer matrix multiply accumulate
target/arm: Implement aarch32 VSUDOT, VUSDOT
target/arm: Split decode of VSDOT and VUDOT
target/arm: Split out do_neon_ddda
target/arm: Fix decode for VDOT (indexed)
target/arm: Remove unused fpst from VDOT_scalar
target/arm: Split out do_neon_ddda_fpst
target/arm: Implement aarch64 SUDOT, USDOT
target/arm: Implement SVE2 fp multiply-add long
target/arm: Move endian adjustment macros to vec_internal.h
target/arm: Implement SVE2 bitwise shift immediate
target/arm: Implement 128-bit ZIP, UZP, TRN
target/arm: Implement SVE2 LD1RO
target/arm: Tidy do_ldrq
target/arm: Share table of sve load functions
target/arm: Implement SVE2 FLOGB
target/arm: Implement SVE2 FCVTXNT, FCVTX
target/arm: Implement SVE2 FCVTLT
...
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:58 +0000 (18:03 -0700)]
target/arm: Enable SVE2 and related extensions
Disable I8MM again for !have_neon during realize.
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:57 +0000 (18:03 -0700)]
linux-user/aarch64: Enable hwcap bits for sve2 and related extensions
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:56 +0000 (18:03 -0700)]
target/arm: Implement integer matrix multiply accumulate
This is {S,U,US}MMLA for both AArch64 AdvSIMD and SVE,
and V{S,U,US}MMLA.S8 for AArch32 NEON.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:55 +0000 (18:03 -0700)]
target/arm: Implement aarch32 VSUDOT, VUSDOT
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:54 +0000 (18:03 -0700)]
target/arm: Split decode of VSDOT and VUDOT
Now that we have a common helper, sharing decode does not
save much. Also, this will solve an upcoming naming problem.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:53 +0000 (18:03 -0700)]
target/arm: Split out do_neon_ddda
Split out a helper that can handle the 4-register
format for helpers shared with SVE.
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:52 +0000 (18:03 -0700)]
target/arm: Fix decode for VDOT (indexed)
We were extracting the M register twice, once incorrectly
as M:vm and once correctly as rm. Remove the incorrect
name and remove the incorrect decode.
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:51 +0000 (18:03 -0700)]
target/arm: Remove unused fpst from VDOT_scalar
Cut and paste error from another pattern.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:50 +0000 (18:03 -0700)]
target/arm: Split out do_neon_ddda_fpst
Split out a helper that can handle the 4-register
format for helpers shared with SVE.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:49 +0000 (18:03 -0700)]
target/arm: Implement aarch64 SUDOT, USDOT
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:48 +0000 (18:03 -0700)]
target/arm: Implement SVE2 fp multiply-add long
Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200504171240 [email protected] >
[rth: Rearrange to use float16_to_float32_by_bits.]
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:47 +0000 (18:03 -0700)]
target/arm: Move endian adjustment macros to vec_internal.h
We have two copies of these, one set of which is not complete.
Move them to a common header.
Suggested-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:46 +0000 (18:03 -0700)]
target/arm: Implement SVE2 bitwise shift immediate
Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200430194159 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:45 +0000 (18:03 -0700)]
target/arm: Implement 128-bit ZIP, UZP, TRN
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:44 +0000 (18:03 -0700)]
target/arm: Implement SVE2 LD1RO
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:43 +0000 (18:03 -0700)]
target/arm: Tidy do_ldrq
Use tcg_constant_i32 for passing the simd descriptor,
as this hashed value does not need to be freed.
Rename dofs to doff to match poff.
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:42 +0000 (18:03 -0700)]
target/arm: Share table of sve load functions
The table used by do_ldrq is a subset of the table used by do_ld_zpa;
we can share them by passing dtype instead of msz to do_ldrq.
The lack of MTE handling in do_ldrq was a bug, fixed by this change.
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:41 +0000 (18:03 -0700)]
target/arm: Implement SVE2 FLOGB
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200430191405 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:40 +0000 (18:03 -0700)]
target/arm: Implement SVE2 FCVTXNT, FCVTX
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200428174332 [email protected] >
[rth: Use do_frint_mode, which avoids a specific runtime helper.]
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:39 +0000 (18:03 -0700)]
target/arm: Implement SVE2 FCVTLT
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200428174332 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:38 +0000 (18:03 -0700)]
target/arm: Implement SVE2 FCVTNT
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200428174332 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:37 +0000 (18:03 -0700)]
target/arm: Implement SVE2 TBL, TBX
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200428144352 [email protected] >
[rth: rearrange the macros a little and rebase]
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:36 +0000 (18:03 -0700)]
target/arm: Implement SVE2 crypto constructive binary operations
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:35 +0000 (18:03 -0700)]
target/arm: Implement SVE2 crypto destructive binary operations
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:34 +0000 (18:03 -0700)]
target/arm: Implement SVE2 crypto unary operations
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:33 +0000 (18:03 -0700)]
target/arm: Implement SVE mixed sign dot product
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:32 +0000 (18:03 -0700)]
target/arm: Implement SVE mixed sign dot product (indexed)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:31 +0000 (18:03 -0700)]
target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h}
We're about to add more variations on this theme.
Accept the inner loop for the _h variants, rather
than keep it unrolled.
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:30 +0000 (18:03 -0700)]
target/arm: Macroize helper_gvec_{s,u}dot_{b,h}
We're about to add more variations on this theme.
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:29 +0000 (18:03 -0700)]
target/arm: Implement SVE2 complex integer dot product
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:28 +0000 (18:03 -0700)]
target/arm: Implement SVE2 complex integer multiply-add (indexed)
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:27 +0000 (18:03 -0700)]
target/arm: Implement SVE2 integer multiply long (indexed)
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:26 +0000 (18:03 -0700)]
target/arm: Implement SVE2 multiply-add long (indexed)
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:25 +0000 (18:03 -0700)]
target/arm: Implement SVE2 saturating multiply high (indexed)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:24 +0000 (18:03 -0700)]
target/arm: Implement SVE2 signed saturating doubling multiply high
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:23 +0000 (18:03 -0700)]
target/arm: Implement SVE2 saturating multiply (indexed)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:22 +0000 (18:03 -0700)]
target/arm: Implement SVE2 saturating multiply-add (indexed)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:21 +0000 (18:03 -0700)]
target/arm: Implement SVE2 saturating multiply-add high (indexed)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:20 +0000 (18:03 -0700)]
target/arm: Implement SVE2 integer multiply-add (indexed)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:19 +0000 (18:03 -0700)]
target/arm: Implement SVE2 integer multiply (indexed)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:18 +0000 (18:03 -0700)]
target/arm: Split out formats for 3 vectors + 1 index
Used by FMLA and DOT, but will shortly be used more.
Split FMLA from FMLS to avoid an extra sub field;
similarly for SDOT from UDOT.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:17 +0000 (18:03 -0700)]
target/arm: Split out formats for 2 vectors + 1 index
Currently only used by FMUL, but will shortly be used more.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:16 +0000 (18:03 -0700)]
target/arm: Pass separate addend to FCMLA helpers
For SVE, we potentially have a 4th argument coming from the
movprfx instruction. Currently we do not optimize movprfx,
so the problem is not visible.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:15 +0000 (18:03 -0700)]
target/arm: Pass separate addend to {U, S}DOT helpers
For SVE, we potentially have a 4th argument coming from the
movprfx instruction. Currently we do not optimize movprfx,
so the problem is not visible.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:14 +0000 (18:03 -0700)]
target/arm: Use correct output type for gvec_sdot_*_b
The signed dot product routines produce a signed result.
Since we use -fwrapv, there is no functional change.
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:13 +0000 (18:03 -0700)]
target/arm: Implement SVE2 SPLICE, EXT
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200423180347 [email protected] >
[rth: Rename the trans_* functions to *_sve2.]
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:12 +0000 (18:03 -0700)]
target/arm: Implement SVE2 FMMLA
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200422165503 [email protected] >
[rth: Fix indexing in helpers, expand macro to straight functions.]
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:11 +0000 (18:03 -0700)]
target/arm: Implement SVE2 gather load insns
Add decoding logic for SVE2 64-bit/32-bit gather non-temporal
load insns.
64-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1SW
* LDNT1W (vector plus scalar)
* LDNT1D (vector plus scalar)
32-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1W (vector plus scalar)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200422152343 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:10 +0000 (18:03 -0700)]
target/arm: Implement SVE2 scatter store insns
Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal
store insns.
64-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
* STNT1D (vector plus scalar)
32-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200422141553 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:09 +0000 (18:03 -0700)]
target/arm: Implement SVE2 XAR
In addition, use the same vector generator interface for AdvSIMD.
This fixes a bug in which the AdvSIMD insn failed to clear the
high bits of the SVE register.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:08 +0000 (18:03 -0700)]
target/arm: Implement SVE2 HISTCNT, HISTSEG
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200416173109 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:07 +0000 (18:03 -0700)]
target/arm: Implement SVE2 RSUBHNB, RSUBHNT
This completes the section 'SVE2 integer add/subtract narrow high part'
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200417162231 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:06 +0000 (18:03 -0700)]
target/arm: Implement SVE2 SUBHNB, SUBHNT
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200417162231 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:05 +0000 (18:03 -0700)]
target/arm: Implement SVE2 RADDHNB, RADDHNT
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200417162231 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:03:04 +0000 (18:03 -0700)]
target/arm: Implement SVE2 ADDHNB, ADDHNT
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200417162231 [email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:03 +0000 (18:03 -0700)]
target/arm: Implement SVE2 complex integer multiply-add
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:02 +0000 (18:03 -0700)]
target/arm: Implement SVE2 integer multiply-add long
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:01 +0000 (18:03 -0700)]
target/arm: Implement SVE2 saturating multiply-add high
SVE2 has two additional sizes of the operation and unlike NEON,
there is no saturation flag. Create new entry points for SVE2
that do not set QC.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:03:00 +0000 (18:03 -0700)]
target/arm: Implement SVE2 saturating multiply-add long
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:02:59 +0000 (18:02 -0700)]
target/arm: Implement SVE2 MATCH, NMATCH
Reviewed-by: Richard Henderson <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Message-Id: <
20200415145915 [email protected] >
[rth: Expanded comment for do_match2]
Signed-off-by: Richard Henderson <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:58 +0000 (18:02 -0700)]
target/arm: Implement SVE2 bitwise ternary operations
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:57 +0000 (18:02 -0700)]
target/arm: Implement SVE2 WHILERW, WHILEWR
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:56 +0000 (18:02 -0700)]
target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS
Rename the existing sve_while (less-than) helper to sve_whilel
to make room for a new sve_whileg helper for greater-than.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:55 +0000 (18:02 -0700)]
target/arm: Implement SVE2 SQSHRN, SQRSHRN
This completes the section "SVE2 bitwise shift right narrow".
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:54 +0000 (18:02 -0700)]
target/arm: Implement SVE2 UQSHRN, UQRSHRN
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:53 +0000 (18:02 -0700)]
target/arm: Implement SVE2 SQSHRUN, SQRSHRUN
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:52 +0000 (18:02 -0700)]
target/arm: Implement SVE2 SHRN, RSHRN
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Stephen Long [Tue, 25 May 2021 01:02:51 +0000 (18:02 -0700)]
target/arm: Implement SVE2 floating-point pairwise
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Stephen Long <[email protected] >
Reviewed-by: Richard Henderson <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:50 +0000 (18:02 -0700)]
target/arm: Implement SVE2 saturating extract narrow
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:49 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer absolute difference and accumulate
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:48 +0000 (18:02 -0700)]
target/arm: Implement SVE2 bitwise shift and insert
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:47 +0000 (18:02 -0700)]
target/arm: Implement SVE2 bitwise shift right and accumulate
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:46 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer add/subtract long with carry
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:45 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer absolute difference and accumulate long
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:44 +0000 (18:02 -0700)]
target/arm: Implement SVE2 complex integer add
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:43 +0000 (18:02 -0700)]
target/arm: Implement SVE2 bitwise permute
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:42 +0000 (18:02 -0700)]
target/arm: Implement SVE2 bitwise exclusive-or interleaved
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:41 +0000 (18:02 -0700)]
target/arm: Implement SVE2 bitwise shift left long
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:40 +0000 (18:02 -0700)]
target/arm: Implement SVE2 PMULLB, PMULLT
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:39 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer multiply long
Exclude PMULL from this category for the moment.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:38 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer add/subtract wide
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:37 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer add/subtract interleaved long
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:36 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer add/subtract long
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:35 +0000 (18:02 -0700)]
target/arm: Implement SVE2 saturating add/subtract (predicated)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:34 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer pairwise arithmetic
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:33 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer halving add/subtract (predicated)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:32 +0000 (18:02 -0700)]
target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated)
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:31 +0000 (18:02 -0700)]
target/arm: Split out saturating/rounding shifts from neon
Split these operations out into a header that can be shared
between neon and sve. The "sat" pointer acts both as a boolean
for control of saturating behavior and controls the difference
in behavior between neon and sve -- QC bit or no QC bit.
Widen the shift operand in the new helpers, as the SVE2 insns treat
the whole input element as significant. For the neon uses, truncate
the shift to int8_t while passing the parameter.
Implement right-shift rounding as
tmp = src >> (shift - 1);
dst = (tmp >> 1) + (tmp & 1);
This is the same number of instructions as the current
tmp = 1 << (shift - 1);
dst = (src + tmp) >> shift;
without any possibility of intermediate overflow.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:30 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer unary operations (predicated)
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:29 +0000 (18:02 -0700)]
target/arm: Implement SVE2 integer pairwise add and accumulate long
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:28 +0000 (18:02 -0700)]
target/arm: Implement SVE2 Integer Multiply - Unpredicated
For MUL, we can rely on generic support. For SMULH and UMULH,
create some trivial helpers. For PMUL, back in
a21bb78e5817 ,
we organized helper_gvec_pmul_b in preparation for this use.
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
Richard Henderson [Tue, 25 May 2021 01:02:27 +0000 (18:02 -0700)]
target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
Will be used for SVE2 isa subset enablement.
Reviewed-by: Alex Bennée <[email protected] >
Signed-off-by: Richard Henderson <[email protected] >
Message-id:
20210525010358 [email protected]
Reviewed-by: Peter Maydell <[email protected] >
Signed-off-by: Peter Maydell <[email protected] >
Philippe Mathieu-Daudé [Sun, 16 May 2021 17:10:23 +0000 (19:10 +0200)]
disas/libvixl: Protect C system header for C++ compiler
When selecting an ARM target on Debian unstable, we get:
Compiling C++ object libcommon.fa.p/disas_libvixl_vixl_utils.cc.o
FAILED: libcommon.fa.p/disas_libvixl_vixl_utils.cc.o
c++ -Ilibcommon.fa.p -I. -I.. [...] -o libcommon.fa.p/disas_libvixl_vixl_utils.cc.o -c ../disas/libvixl/vixl/utils.cc
In file included from /home/philmd/qemu/disas/libvixl/vixl/utils.h:30,
from ../disas/libvixl/vixl/utils.cc:27:
/usr/include/string.h:36:43: error: missing binary operator before token "("
36 | #if defined __cplusplus && (__GNUC_PREREQ (4, 4) \
| ^
/usr/include/string.h:53:62: error: missing binary operator before token "("
53 | #if defined __USE_MISC || defined __USE_XOPEN || __GLIBC_USE (ISOC2X)
| ^
/usr/include/string.h:165:21: error: missing binary operator before token "("
165 | || __GLIBC_USE (LIB_EXT2) || __GLIBC_USE (ISOC2X))
| ^
/usr/include/string.h:174:43: error: missing binary operator before token "("
174 | #if defined __USE_XOPEN2K8 || __GLIBC_USE (LIB_EXT2) || __GLIBC_USE (ISOC2X)
| ^
/usr/include/string.h:492:19: error: missing binary operator before token "("
492 | #if __GNUC_PREREQ (3,4)
| ^
Relevant information from the host:
$ lsb_release -d
Description: Debian GNU/Linux 11 (bullseye)
$ gcc --version
gcc (Debian 10.2.1-6) 10.2.1
20210110
$ dpkg -S /usr/include/string.h
libc6-dev: /usr/include/string.h
$ apt-cache show libc6-dev
Package: libc6-dev
Version: 2.31-11
Partially cherry-pick vixl commit
78973f258039f6e96 [*]:
Refactor VIXL to use `extern` block when including C header
that do not have a C++ counterpart.
which is similar to commit
875df03b221 ('osdep: protect qemu/osdep.h
with extern "C"').
[*] https://git.linaro.org/arm/vixl.git/commit/?id=
78973f258039f6e96
Buglink: https://bugs.launchpad.net/qemu/+bug/1914870
Suggested-by: Thomas Huth <[email protected] >
Signed-off-by: Philippe Mathieu-Daudé <[email protected] >
Reviewed-by: Thomas Huth <[email protected] >
Message-id:
20210516171023 [email protected]
Signed-off-by: Peter Maydell <[email protected] >
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