Peter Maydell [Fri, 5 Feb 2021 17:14:56 +0000 (17:14 +0000)]
arm: Update infocenter.arm.com URLs
Update infocenter.arm.com URLs for various pieces of Arm
documentation to the new developer.arm.com equivalents. (There is a
redirection in place from the old URLs, but we might as well update
our comments in case the redirect ever disappears in future.)
This patch covers all the URLs which are not MPS2/SSE-200/IoTKit
related (those are dealt with in a different patch).
Rebecca Cran [Mon, 8 Feb 2021 06:56:57 +0000 (23:56 -0700)]
target/arm: Add support for FEAT_DIT, Data Independent Timing
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic and TCG is outside of the security domain, it's
implemented as a NOP.
Aaron Lindsay [Wed, 3 Feb 2021 16:13:40 +0000 (11:13 -0500)]
target/arm: Don't migrate CPUARMState.features
As feature flags are added or removed, the meanings of bits in the
`features` field can change between QEMU versions, causing migration
failures. Additionally, migrating the field is not useful because it is
a constant function of the CPU being used.
Peter Maydell [Wed, 10 Feb 2021 15:42:19 +0000 (15:42 +0000)]
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging
Pull request
v4:
* Add PCI_EXPRESS Kconfig dependency to fix s390x in "multi-process: setup PCI
host bridge for remote device" [Philippe and Thomas]
# gpg: Signature made Wed 10 Feb 2021 09:26:14 GMT
# gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <[email protected]>" [full]
# gpg: aka "Stefan Hajnoczi <[email protected]>" [full]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha-gitlab/tags/block-pull-request: (27 commits)
docs: fix Parallels Image "dirty bitmap" section
multi-process: perform device reset in the remote process
multi-process: Retrieve PCI info from remote process
multi-process: create IOHUB object to handle irq
multi-process: Synchronize remote memory
multi-process: PCI BAR read/write handling for proxy & remote endpoints
multi-process: Forward PCI config space acceses to the remote process
multi-process: add proxy communication functions
multi-process: introduce proxy object
multi-process: setup memory manager for remote device
multi-process: Associate fd of a PCIDevice with its object
multi-process: Initialize message handler in remote device
multi-process: define MPQemuMsg format and transmission functions
io: add qio_channel_readv_full_all_eof & qio_channel_readv_full_all helpers
io: add qio_channel_writev_full_all helper
multi-process: setup a machine object for remote device process
multi-process: setup PCI host bridge for remote device
multi-process: Add config option for multi-process QEMU
memory: alloc RAM from file at offset
multi-process: add configure and usage information
...
Peter Maydell [Wed, 10 Feb 2021 13:38:27 +0000 (13:38 +0000)]
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210210' into staging
ppc patch queue for 20201-02-10
Here's the latest batch of patches for the ppc target and machine
types. Highlights are:
* Several fixes for E500 from Bin Meng
* Fixes and cleanups for PowerNV from Cédric Le Goater
* Assorted other fixes and cleanups
* remotes/dg-gitlab/tags/ppc-for-6.0-20210210:
target/ppc: Add E500 L2CSR0 write helper
hw/net: fsl_etsec: Reverse the RCTRL.RSF logic
hw/ppc: e500: Fill in correct <clock-frequency> for the serial nodes
hw/ppc: e500: Use a macro for the platform clock frequency
ppc/pnv: Set default RAM size to 1 GB
spapr_numa.c: fix ibm,max-associativity-domains calculation
spapr_numa.c: create spapr_numa_initial_nvgpu_numa_id() helper
spapr: move spapr_machine_using_legacy_numa() to spapr_numa.c
ppc/pnv: Introduce a LPC FW memory region attribute to map the PNOR
ppc/pnv: Remove default disablement of the PNOR contents
ppc/pnv: Discard internal BMC initialization when BMC is external
ppc/pnv: Simplify pnv_bmc_create()
ppc/pnv: Use skiboot addresses to load kernel and ramfs
ppc/xive: Add firmware bit when dumping the ENDs
ppc/pnv: Add trace events for PCI event notification
target/ppc: Remove unused MMU definitions
spapr: Adjust firmware path of PCI devices
spapr.c: add 'name' property for hotplugged CPUs nodes
spapr.c: use g_auto* with 'nodename' in CPU DT functions
Denis V. Lunev [Thu, 28 Jan 2021 17:13:13 +0000 (20:13 +0300)]
docs: fix Parallels Image "dirty bitmap" section
Original specification says that l1 table size if 64 * l1_size, which
is obviously wrong. The size of the l1 entry is 64 _bits_, not bytes.
Thus 64 is to be replaces with 8 as specification says about bytes.
There is also minor tweak, field name is renamed from l1 to l1_table,
which matches with the later text.
Elena Ufimtseva [Fri, 29 Jan 2021 16:46:21 +0000 (11:46 -0500)]
multi-process: perform device reset in the remote process
Perform device reset in the remote process when QEMU performs
device reset. This is required to reset the internal state
(like registers, etc...) of emulated devices
IOHUB object is added to manage PCI IRQs. It uses KVM_IRQFD
ioctl to create irqfd to injecting PCI interrupts to the guest.
IOHUB object forwards the irqfd to the remote process. Remote process
uses this fd to directly send interrupts to the guest, bypassing QEMU.
Add ProxyMemoryListener object which is used to keep the view of the RAM
in sync between QEMU and remote process.
A MemoryListener is registered for system-memory AddressSpace. The
listener sends SYNC_SYSMEM message to the remote process when memory
listener commits the changes to memory, the remote process receives
the message and processes it in the handler for SYNC_SYSMEM message.
multi-process: PCI BAR read/write handling for proxy & remote endpoints
Proxy device object implements handler for PCI BAR writes and reads.
The handler uses BAR_WRITE/BAR_READ message to communicate to the
remote process with the BAR address and value to be written/read.
The remote process implements handler for BAR_WRITE/BAR_READ
message.
multi-process: setup memory manager for remote device
SyncSysMemMsg message format is defined. It is used to send
file descriptors of the RAM regions to remote device.
RAM on the remote device is configured with a set of file descriptors.
Old RAM regions are deleted and new regions, each with an fd, is
added to the RAM.
multi-process: Initialize message handler in remote device
Initializes the message handler function in the remote process. It is
called whenever there's an event pending on QIOChannel that registers
this function.
Elena Ufimtseva [Fri, 29 Jan 2021 16:46:10 +0000 (11:46 -0500)]
multi-process: define MPQemuMsg format and transmission functions
Defines MPQemuMsg, which is the message that is sent to the remote
process. This message is sent over QIOChannel and is used to
command the remote process to perform various tasks.
Define transmission functions used by proxy and by remote.
multi-process: setup a machine object for remote device process
x-remote-machine object sets up various subsystems of the remote
device process. Instantiate PCI host bridge object and initialize RAM, IO &
PCI memory regions.
multi-process: setup PCI host bridge for remote device
PCI host bridge is setup for the remote device process. It is
implemented using remote-pcihost object. It is an extension of the PCI
host bridge setup by QEMU.
Remote-pcihost configures a PCI bus which could be used by the remote
PCI device to latch on to.
[Added PCI_EXPRESS condition in hw/remote/Kconfig since remote-pcihost
needs PCIe. This solves "make check" failure on s390x. Fix suggested by
Philippe Mathieu-Daudé <[email protected]> and Thomas Huth
<[email protected]>.
--Stefan]
Bin Meng [Wed, 10 Feb 2021 02:10:21 +0000 (10:10 +0800)]
hw/net: fsl_etsec: Reverse the RCTRL.RSF logic
Per MPC8548ERM [1] chapter 14.5.3.4.1:
When RCTRL.RSF is 1, frames less than 64 bytes are accepted upon
a DA match. But currently QEMU does the opposite. This commit
reverses the RCTRL.RSF testing logic to match the manual.
Due to the reverse of the logic, certain guests may potentially
break if they don't program eTSEC to have RCTRL.RSF bit set.
When RCTRL.RSF is 0, short frames are silently dropped, however
as of today both slirp and tap networking do not pad short frames
(e.g.: an ARP packet) to the minimum frame size of 60 bytes. So
ARP requests will be dropped, preventing the guest from becoming
visible on the network.
The same issue was reported on e1000 and vmxenet3 before, see:
commit 78aeb23eded2 ("e1000: Pad short frames to minimum size (60 bytes)")
commit 40a87c6c9b11 ("vmxnet3: Pad short frames to minimum size (60 bytes)")
Bin Meng [Wed, 3 Feb 2021 14:24:48 +0000 (22:24 +0800)]
hw/ppc: e500: Fill in correct <clock-frequency> for the serial nodes
At present the <clock-frequency> property of the serial node is
populated with value zero. U-Boot's ns16550 driver is not happy
about this, so let's fill in a meaningful value.
The current logic for calculating 'maxdomain' making it a sum of
numa_state->num_nodes with spapr->gpu_numa_id. spapr->gpu_numa_id is
used as a index to determine the next available NUMA id that a
given NVGPU can use.
The problem is that the initial value of gpu_numa_id, for any topology
that has more than one NUMA node, is equal to numa_state->num_nodes.
This means that our maxdomain will always be, at least, twice the
amount of existing NUMA nodes. This means that a guest with 4 NUMA
nodes will end up with the following max-associativity-domains:
SLUB is detecting 8 total nodes, with 4 nodes being online.
This patch fixes ibm,max-associativity-domains by considering the amount
of NVGPUs NUMA nodes presented in the guest, instead of just
spapr->gpu_numa_id.
We'll need to check the initial value given to spapr->gpu_numa_id when
building the rtas DT, so put it in a helper for easier access and to
avoid repetition.
Cédric Le Goater [Tue, 26 Jan 2021 17:10:58 +0000 (18:10 +0100)]
ppc/pnv: Remove default disablement of the PNOR contents
On PowerNV systems, the BMC is in charge of mapping the PNOR contents
on the LPC FW address space using the HIOMAP protocol. Under QEMU, we
emulate this behavior and we also add an extra control on the flash
accesses by letting the HIOMAP command handler decide whether the
memory region is accessible or not depending on the firmware requests.
However, this behavior is not compatible with hostboot like firmwares
which need this mapping to be always available. For this reason, the
PNOR memory region is initially disabled for skiboot mode only.
This is badly placed under the LPC model and requires the use of the
machine. Since it doesn't add much, simply remove the initial setting.
The extra control in the HIOMAP command handler will still be performed.
Cédric Le Goater [Tue, 26 Jan 2021 17:10:55 +0000 (18:10 +0100)]
ppc/pnv: Use skiboot addresses to load kernel and ramfs
The current settings are useful to load large kernels (with debug) but
it moves the initrd image in a memory region not protected by
skiboot. If skiboot is compiled with DEBUG=1, memory poisoning will
corrupt the initrd.
Cédric Le Goater [Tue, 26 Jan 2021 17:10:53 +0000 (18:10 +0100)]
ppc/pnv: Add trace events for PCI event notification
On POWER9 systems, PHB controllers signal the XIVE interrupt controller
of a source interrupt notification using a store on a MMIO region. Add
traces for such events.
SLOF **********************************************************************
QEMU Starting
Build Date = Jul 17 2020 11:15:24
FW Version = git-e18ddad8516ff2cf
Press "s" to enter Open Firmware.
Populating /vdevice methods
Populating /vdevice/vty@71000000
Populating /vdevice/nvram@71000001
Populating /pci@800000020000000
00 0000 (D) : 1b36 000d serial bus [ usb-xhci ]
No NVRAM common partition, re-initializing...
Scanning USB
XHCI: Initializing
USB Storage
SCSI: Looking for devices 101000000000000 DISK : "QEMU QEMU HARDDISK 2.5+"
Using default console: /vdevice/vty@71000000
Welcome to Open Firmware
Copyright (c) 2004, 2017 IBM Corporation All rights reserved.
This program and the accompanying materials are made available
under the terms of the BSD License available at
http://www.opensource.org/licenses/bsd-license.php
but the device node is named usb-xhci@0, not usb@0.
This happens because the firmware names of PCI devices returned
by get_boot_devices_list() come from pcibus_get_fw_dev_path(),
while the sPAPR PHB code uses a different naming scheme for
device nodes. This inconsistency has always been there but it was
hidden for a long time because SLOF used to rename USB device
nodes, until this commit, merged in QEMU 4.2.0 :
This fixes USB host bus adapter name in the device tree to match QEMU's
one.
Signed-off-by: Alexey Kardashevskiy <[email protected]> Signed-off-by: David Gibson <[email protected]>
Fortunately, sPAPR implements the firmware path provider interface.
This provides a way to override the default firmware paths.
Just factor out the sPAPR PHB naming logic from spapr_dt_pci_device()
to a helper, and use it in the sPAPR firmware path provider hook.
spapr.c: add 'name' property for hotplugged CPUs nodes
In the CPU hotunplug bug [1] the guest kernel throws a scary
message in dmesg:
pseries-hotplug-cpu: Failed to offline CPU <NULL>, rc: -16
The reason isn't related to the bug though. This happens because the
kernel file arch/powerpc/platform/pseries/hotplug-cpu.c, function
dlpar_cpu_remove(), is not finding the device_node.name of the offending
CPU.
We're not populating the 'name' property for hotplugged CPUs. Since the
kernel relies on device_node.name for identifying CPU nodes, and the
CPUs that are coldplugged has the 'name' property filled by SLOF, this
is creating an unneeded inconsistency between hotplug and coldplug CPUs
in the kernel.
Let's fill the 'name' property for hotplugged CPUs as well. This will
make the guest dmesg throws a less intimidating message when we try to
unplug the last online CPU:
pseries-hotplug-cpu: Failed to offline CPU PowerPC,POWER9@1, rc: -16
spapr.c: use g_auto* with 'nodename' in CPU DT functions
Next patch will use the 'nodename' string in spapr_core_dt_populate()
after the point it's being freed today.
Instead of moving 'g_free(nodename)' around, let's do a QoL change in
both CPU DT functions where 'nodename' is being freed, and use
g_autofree to avoid the 'g_free()' call altogether.
Allow RAM MemoryRegion to be created from an offset in a file, instead
of allocating at offset of 0 by default. This is needed to synchronize
RAM between QEMU & remote process.
[Move orphan docs/multi-process.rst document into docs/system/ and add
it to index.rst to prevent Sphinx "document isn't included in any
toctree" error.
--Stefan]
Stefan Hajnoczi [Mon, 11 Jan 2021 11:50:17 +0000 (11:50 +0000)]
get_maintainer: update repo URL to GitLab
qemu.org is running out of bandwidth and the QEMU project is moving
towards a gating CI on GitLab. Use the GitLab repos instead of qemu.org
(they will become mirrors).
Stefan Hajnoczi [Mon, 11 Jan 2021 11:50:16 +0000 (11:50 +0000)]
pc-bios: update mirror URLs to GitLab
qemu.org is running out of bandwidth and the QEMU project is moving
towards a gating CI on GitLab. Use the GitLab repos instead of qemu.org
(they will become mirrors).
Stefan Hajnoczi [Mon, 11 Jan 2021 11:50:15 +0000 (11:50 +0000)]
docs: update README to use GitLab repo URLs
qemu.org is running out of bandwidth and the QEMU project is moving
towards a gating CI on GitLab. Use the GitLab repos instead of qemu.org
(they will become mirrors).
Stefan Hajnoczi [Mon, 11 Jan 2021 11:50:13 +0000 (11:50 +0000)]
gitmodules: use GitLab repos instead of qemu.org
qemu.org is running out of bandwidth and the QEMU project is moving
towards a gating CI on GitLab. Use the GitLab repos instead of qemu.org
(they will become mirrors).
And a lot of smaller fixes from Gollu Appalanaidu and Minwoo Im.
# gpg: Signature made Tue 09 Feb 2021 07:25:18 GMT
# gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9
# gpg: Good signature from "Klaus Jensen <[email protected]>" [unknown]
# gpg: aka "Klaus Jensen <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838
# Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9
* remotes/nvme/tags/nvme-next-pull-request: (56 commits)
hw/block/nvme: refactor the logic for zone write checks
hw/block/nvme: fix zone boundary check for append
hw/block/nvme: fix wrong parameter name 'cross_read'
hw/block/nvme: align with existing style
hw/block/nvme: fix set feature save field check
hw/block/nvme: fix set feature for error recovery
hw/block/nvme: error if drive less than a zone size
hw/block/nvme: lift cmb restrictions
hw/block/nvme: bump to v1.4
hw/block/nvme: move cmb logic to v1.4
hw/block/nvme: add PMR RDS/WDS support
hw/block/nvme: disable PMR at boot up
hw/block/nvme: remove redundant zeroing of PMR registers
hw/block/nvme: rename PMR/CMB shift/mask fields
hw/block/nvme: allow cmb and pmr to coexist
hw/block/nvme: move msix table and pba to BAR 0
hw/block/nvme: indicate CMB support through controller capabilities register
hw/block/nvme: fix 64 bit register hi/lo split writes
hw/block/nvme: add size to mmio read/write trace events
hw/block/nvme: trigger async event during injecting smart warning
...
Peter Maydell [Mon, 8 Feb 2021 20:22:54 +0000 (20:22 +0000)]
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/integration-testing-20210208' into staging
Integration testing patches
Tests added:
- Armbian 20.08 on Orange Pi PC (Philippe)
- MPC8544ds machine (Thomas)
- Virtex-ml507 ppc machine (Thomas)
- Re-enable the microblaze test (Thomas)
Various fixes and documentation improvements from Cleber.
# gpg: Signature made Mon 08 Feb 2021 20:19:12 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <[email protected]>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/integration-testing-20210208:
Acceptance Tests: remove unnecessary tag from documentation example
Acceptance tests: clarify ssh connection failure reason
tests/acceptance/virtiofs_submounts: required space between IP and port
tests/acceptance/virtiofs_submounts: standardize port as integer
tests/acceptance/virtiofs_submounts: use a virtio-net device instead
tests/acceptance/virtiofs_submounts: do not ask for ssh key password
tests/acceptance/virtiofs_submounts: use workdir property
tests/acceptance/boot_linux: rename misleading cloudinit method
tests/acceptance/boot_linux: fix typo on cloudinit error message
tests/acceptance: Re-enable the microblaze test
tests/acceptance: Add a test for the virtex-ml507 ppc machine
tests/acceptance: Test the mpc8544ds machine
tests/acceptance: Move the pseries test to a separate file
tests/acceptance: Test U-Boot/Linux from Armbian 20.08 on Orange Pi PC
tests/acceptance: Extract do_test_arm_orangepi_armbian_uboot() method
tests/acceptance: Introduce tesseract_ocr() helper
tests/acceptance: Extract tesseract_available() helper in new namespace
Klaus Jensen [Tue, 19 Jan 2021 13:21:50 +0000 (14:21 +0100)]
hw/block/nvme: refactor the logic for zone write checks
Refactor the zone write check logic such that the most "meaningful"
error is returned first. That is, first, if the zone is not writable,
return an appropriate status code for that. Then, make sure we are
actually writing at the write pointer and finally check that we do not
cross the zone write boundary. This aligns with the "priority" of status
codes for zone read checks.
Also add a couple of additional descriptive trace events and remove an
always true assert.
Klaus Jensen [Tue, 19 Jan 2021 11:42:58 +0000 (12:42 +0100)]
hw/block/nvme: fix zone boundary check for append
When a zone append is processed the controller checks that validity of
the write before assigning the LBA to the append command. This causes
the boundary check to be wrong.
Fix this by checking the write *after* assigning the LBA. Remove the
append special case from the nvme_check_zone_write and open code it in
nvme_do_write, assigning the slba when basic sanity checks have been
performed. Then check the validity of the resulting write like any other
write command.
In the process, also fix a missing endianness conversion for the zone
append ALBA.
Currently, no features are saveable, so the current check is not wrong,
but add a check against the feature capabilities to make sure this will
not regress if saveable features are added later.
Minwoo Im [Fri, 15 Jan 2021 12:19:20 +0000 (21:19 +0900)]
hw/block/nvme: error if drive less than a zone size
If a user assigns a backing device with less capacity than the size of a
single zone, the namespace capacity will be reported as zero and the
kernel will silently fail to allocate the namespace.
This patch errors out in case that the backing device cannot accomodate
at least a single zone.
Signed-off-by: Minwoo Im <[email protected]>
[k.jensen: small fixup in the error and commit message] Signed-off-by: Klaus Jensen <[email protected]>
Klaus Jensen [Thu, 17 Dec 2020 23:32:57 +0000 (00:32 +0100)]
hw/block/nvme: lift cmb restrictions
The controller now implements v1.4 and we can lift the restrictions on
CMB Data Pointer and Command Independent Locations Support (CDPCILS) and
CMB Data Pointer Mixed Locations Support (CDPMLS) since the device
really does not care about mixed host/cmb pointers in those cases.
Implement v1.4 logic for configuring the Controller Memory Buffer. By
default, the v1.4 scheme will be used (CMB must be explicitly enabled by
the host), so drivers that only support v1.3 will not be able to use the
CMB anymore.
To retain the v1.3 behavior, set the boolean 'legacy-cmb' nvme device
parameter.
Klaus Jensen [Fri, 18 Dec 2020 12:04:19 +0000 (13:04 +0100)]
hw/block/nvme: disable PMR at boot up
The PMR should not be enabled at boot up. Disable the PMR MemoryRegion
initially and implement MMIO for PMRCTL, allowing the host to enable the
PMR explicitly.
Klaus Jensen [Fri, 13 Nov 2020 08:50:33 +0000 (09:50 +0100)]
hw/block/nvme: move msix table and pba to BAR 0
In the interest of supporting both CMB and PMR to be enabled on the same
device, move the MSI-X table and pending bit array out of BAR 4 and into
BAR 0.
This is a simplified version of the patch contributed by Andrzej
Jakowski (see [1]). Leaving the CMB at offset 0 removes the need for
changes to CMB address mapping code.
Andrzej Jakowski [Fri, 13 Nov 2020 07:00:47 +0000 (08:00 +0100)]
hw/block/nvme: indicate CMB support through controller capabilities register
This patch sets CMBS bit in controller capabilities register when user
configures NVMe driver with CMB support, so capabilites are correctly
reported to guest OS.
Klaus Jensen [Mon, 18 Jan 2021 06:31:45 +0000 (07:31 +0100)]
hw/block/nvme: fix 64 bit register hi/lo split writes
64 bit registers like ASQ and ACQ should be writable by both a hi/lo 32
bit write combination as well as a plain 64 bit write. The spec does not
define ordering on the hi/lo split, but the code currently assumes that
the low order bits are written first. Additionally, the code does not
consider that another address might already have been written into the
register, causing the OR'ing to result in a bad address.
Fix this by explicitly overwriting only the low or high order bits for
32 bit writes.
There is a very low probability that hitting physical NVMe disk
hardware critical warning case, it's hard to write & test a monitor
agent service.
For debugging purposes, add a new 'smart_critical_warning' property
to emulate this situation.
The orignal version of this change is implemented by adding a fixed
property which could be initialized by QEMU command line. Suggested
by Philippe & Klaus, rework like current version.
Test with this patch:
1, change smart_critical_warning property for a running VM:
#virsh qemu-monitor-command nvme-upstream '{ "execute": "qom-set",
"arguments": { "path": "/machine/peripheral-anon/device[0]",
"property": "smart_critical_warning", "value":16 } }'
2, run smartctl in guest
#smartctl -H -l error /dev/nvme0n1
=== START OF SMART DATA SECTION ===
SMART overall-health self-assessment test result: FAILED!
- volatile memory backup device has failed
zhenwei pi [Fri, 15 Jan 2021 03:27:00 +0000 (11:27 +0800)]
nvme: introduce bit 5 for critical warning
According to NVM Express v1.4, Section 5.14.1.2 ("SMART / Health
Information"), introduce bit 5 for "Persistent Memory Region has become
read-only or unreliable".
Signed-off-by: zhenwei pi <[email protected]>
[k.jensen: minor brush ups in commit message] Signed-off-by: Klaus Jensen <[email protected]>
Klaus Jensen [Tue, 12 Jan 2021 09:32:37 +0000 (10:32 +0100)]
hw/block/nvme: fix zone write finalize
The zone write pointer is unconditionally advanced, even for write
faults. Make sure that the zone is always transitioned to Full if the
write pointer reaches zone capacity.
Minwoo Im [Sun, 17 Jan 2021 14:53:34 +0000 (23:53 +0900)]
hw/block/nvme: split setup and register for namespace
In NVMe, namespace is being attached to process I/O. We register NVMe
namespace to a controller via nvme_register_namespace() during
nvme_ns_setup(). This is main reason of receiving NvmeCtrl object
instance to this function to map the namespace to a controller.
To make namespace instance more independent, it should be split into two
parts: setup and register. This patch split them into two differnt
parts, and finally nvme_ns_setup() does not have nothing to do with
NvmeCtrl instance at all.
This patch is a former patch to introduce NVMe subsystem scheme to the
existing design especially for multi-path. In that case, it should be
split into two to make namespace independent from a controller.
Minwoo Im [Sun, 17 Jan 2021 14:53:32 +0000 (23:53 +0900)]
hw/block/nvme: open code for volatile write cache
Volatile Write Cache(VWC) feature is set in nvme_ns_setup() in the
initial time. This feature is related to block device backed, but this
feature is controlled in controller level via Set/Get Features command.
This patch removed dependency between nvme and nvme-ns to manage the VWC
flag value. Also, it open coded the Get Features for VWC to check all
namespaces attached to the controller, and if false detected, return
directly false.
Signed-off-by: Minwoo Im <[email protected]>
[k.jensen: report write cache preset if present on ANY namespace] Signed-off-by: Klaus Jensen <[email protected]>
Dmitry Fomichev [Mon, 18 Jan 2021 03:39:17 +0000 (12:39 +0900)]
hw/block/nvme: Correct error status for unaligned ZA
TP 4053 says (in section 2.3.1.1) -
... if a Zone Append command specifies a ZSLBA that is not the lowest
logical block address in that zone, then the controller shall abort
that command with a status code of Invalid Field In Command.
In the code, Zone Invalid Write is returned instead, fix this.
Klaus Jensen [Wed, 9 Dec 2020 22:43:15 +0000 (23:43 +0100)]
hw/block/nvme: zero out zones on reset
The zoned command set specification states that "All logical blocks in a
zone *shall* be marked as deallocated when [the zone is reset]". Since
the device guarantees 0x00 to be read from deallocated blocks we have to
issue a pwrite_zeroes since we cannot be sure that a discard will do
anything. But typically, this will be achieved with an efficient
unmap/discard operation.
Klaus Jensen [Mon, 11 Jan 2021 12:52:40 +0000 (13:52 +0100)]
hw/block/nvme: conditionally enable DULBE for zoned namespaces
The device uses the BDRV_BLOCK_ZERO flag to determine the "deallocated"
status of logical blocks. Since the zoned namespaces command set
specification defines that logical blocks SHALL be marked as deallocated
when the zone is in the Empty or Offline states, DULBE can only be
supported if the zone size is a multiple of the calculated deallocation
granularity (reported in NPDG) which depends on the underlying block
device cluster size (if applicable) or the configured
discard_granularity.
Klaus Jensen [Tue, 12 Jan 2021 12:30:26 +0000 (13:30 +0100)]
hw/block/nvme: fix for non-msix machines
Commit 1c0c2163aa08 ("hw/block/nvme: verify msix_init_exclusive_bar()
return value") had the unintended effect of breaking support on
several platforms not supporting MSI-X.
Still check for errors, but only report that MSI-X is unsupported
instead of bailing out.
Fixes: 1c0c2163aa08 ("hw/block/nvme: verify msix_init_exclusive_bar() return value") Fixes: fbf2e5375e33 ("hw/block/nvme: Verify msix_vector_use() returned value") Reported-by: Guenter Roeck <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Klaus Jensen <[email protected]>
Dmitry Fomichev [Tue, 8 Dec 2020 20:04:10 +0000 (05:04 +0900)]
hw/block/nvme: Document zoned parameters in usage text
Added brief descriptions of the new device properties that are
now available to users to configure features of Zoned Namespace
Command Set in the emulator.
This patch is for documentation only, no functionality change.
Dmitry Fomichev [Tue, 8 Dec 2020 20:04:08 +0000 (05:04 +0900)]
hw/block/nvme: Support Zone Descriptor Extensions
Zone Descriptor Extension is a label that can be assigned to a zone.
It can be set to an Empty zone and it stays assigned until the zone
is reset.
This commit adds a new optional module property,
"zoned.descr_ext_size". Its value must be a multiple of 64 bytes.
If this value is non-zero, it becomes possible to assign extensions
of that size to any Empty zones. The default value for this property
is 0, therefore setting extensions is disabled by default.
Dmitry Fomichev [Tue, 8 Dec 2020 20:04:07 +0000 (05:04 +0900)]
hw/block/nvme: Introduce max active and open zone limits
Add two module properties, "zoned.max_active" and "zoned.max_open"
to control the maximum number of zones that can be active or open.
Once these variables are set to non-default values, these limits are
checked during I/O and Too Many Active or Too Many Open command status
is returned if they are exceeded.
Dmitry Fomichev [Tue, 8 Dec 2020 20:04:06 +0000 (05:04 +0900)]
hw/block/nvme: Support Zoned Namespace Command Set
The emulation code has been changed to advertise NVM Command Set when
"zoned" device property is not set (default) and Zoned Namespace
Command Set otherwise.
Define values and structures that are needed to support Zoned
Namespace Command Set (NVMe TP 4053) in PCI NVMe controller emulator.
Define trace events where needed in newly introduced code.
In order to improve scalability, all open, closed and full zones
are organized in separate linked lists. Consequently, almost all
zone operations don't require scanning of the entire zone array
(which potentially can be quite large) - it is only necessary to
enumerate one or more zone lists.
Handlers for three new NVMe commands introduced in Zoned Namespace
Command Set specification are added, namely for Zone Management
Receive, Zone Management Send and Zone Append.
Device initialization code has been extended to create a proper
configuration for zoned operation using device properties.
Read/Write command handler is modified to only allow writes at the
write pointer if the namespace is zoned. For Zone Append command,
writes implicitly happen at the write pointer and the starting write
pointer value is returned as the result of the command. Write Zeroes
handler is modified to add zoned checks that are identical to those
done as a part of Write flow.
Subsequent commits in this series add ZDE support and checks for
active and open zone limits.
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