Peter Maydell [Tue, 15 Mar 2011 16:26:51 +0000 (16:26 +0000)]
target-arm: Fix VLD of single element to all lanes
Fix several bugs in VLD of single element to all lanes:
The "single element to all lanes" form of VLD1 differs from those for
VLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded element
should be written to one or two Dregs (rather than being a register
stride). Handle this by special-casing VLD1 rather than trying to
have one loop which deals with both VLD1 and 2/3/4.
Handle VLD4.32 with 16 byte alignment specified, rather than UNDEFfing.
UNDEF for the invalid size and alignment combinations.
Wen Congyang [Mon, 28 Feb 2011 02:22:33 +0000 (10:22 +0800)]
fix build errors when we enable acpi_piix4 debug
I enable acpi_piix4 debug, and got the following build errors:
# make
CC libhw64/acpi_piix4.o
cc1: warnings being treated as errors
/home/wency/source/qemu/hw/acpi_piix4.c: In function ‘pm_ioport_write’:
/home/wency/source/qemu/hw/acpi_piix4.c:193: error: format ‘%04x’ expects type ‘unsigned int’, but argument 2 has type ‘uint64_t’
/home/wency/source/qemu/hw/acpi_piix4.c:193: error: format ‘%04x’ expects type ‘unsigned int’, but argument 3 has type ‘uint64_t’
/home/wency/source/qemu/hw/acpi_piix4.c: In function ‘pm_ioport_read’:
/home/wency/source/qemu/hw/acpi_piix4.c:219: error: format ‘%04x’ expects type ‘unsigned int’, but argument 2 has type ‘uint64_t’
make[1]: *** [acpi_piix4.o] Error 1
make: *** [subdir-libhw64] Error 2
Stefan Weil [Wed, 16 Feb 2011 20:15:40 +0000 (21:15 +0100)]
ui/sdl: Load optional QEMU icon
Load an optional QEMU icon file. If there is no icon file named
qemu.bmp in QEMU's default search path, QEMU will run with
the usual system default icon.
A matching icon file will be loaded and used by X Windows managers
or MS Windows while a QEMU instance is running.
David Gibson [Fri, 1 Apr 2011 04:15:34 +0000 (15:15 +1100)]
Add SLOF-based partition firmware for pSeries machine, allowing more boot options
Currently, the emulated pSeries machine requires the use of the
-kernel parameter in order to explicitly load a guest kernel. This
means booting from the virtual disk, cdrom or network is not possible.
This patch addresses this limitation by inserting a within-partition
firmware image (derived from the "SLOF" free Open Firmware project).
If -kernel is not specified, qemu will now load the SLOF image, which
has access to the qemu boot device list through the device tree, and
can boot from any of the usual virtual devices.
In order to support the new firmware, an extension to the emulated
machine/hypervisor is necessary. Unlike Linux, which expects
multi-CPU entry to be handled kexec() style, the SLOF firmware expects
only one CPU to be active at entry, and to use a hypervisor RTAS
method to enable the other CPUs one by one.
This patch also implements this 'start-cpu' method, so that SLOF can
start the secondary CPUs and marshal them into the kexec() holding
pattern ready for entry into the guest OS. Linux should, and in the
future might directly use the start-cpu method to enable initially
disabled CPUs, but for now it does require kexec() entry.
David Gibson [Fri, 1 Apr 2011 04:15:33 +0000 (15:15 +1100)]
Implement PAPR VPA functions for pSeries shared processor partitions
Shared-processor partitions are those where a CPU is time-sliced between
partitions, rather than being permanently dedicated to a single
partition. qemu emulated partitions, since they are just scheduled with
the qemu user process, behave mostly like shared processor partitions.
In order to better support shared processor partitions (splpar), PAPR
defines the "VPA" (Virtual Processor Area), a shared memory communication
channel between the hypervisor and partitions. There are also two
additional shared memory communication areas for specialized purposes
associated with the VPA.
A VPA is not essential for operating an splpar, though it can be necessary
for obtaining accurate performance measurements in the presence of
runtime partition switching.
Most importantly, however, the VPA is a prerequisite for PAPR's H_CEDE,
hypercall, which allows a partition OS to give up it's shared processor
timeslices to other partitions when idle.
This patch implements the VPA and H_CEDE hypercalls in qemu. We don't
implement any of the more advanced statistics which can be communicated
through the VPA. However, this is enough to make normal pSeries kernels
do an effective power-save idle on an emulated pSeries, significantly
reducing the host load of a qemu emulated pSeries running an idle guest OS.
Add a PAPR TCE-bypass mechanism for the pSeries machine
Usually, PAPR virtual IO devices use a virtual IOMMU mechanism, TCEs,
to mediate all DMA transfers. While this is necessary for some sorts of
operation, it can be complex to program and slow for others.
This patch implements a mechanism for bypassing TCE translation, treating
"IO" addresses as plain (guest) physical memory addresses. This has two
main uses:
* Simple, but 64-bit aware programs like firmwares can use the VIO devices
without the complexity of TCE setup.
* The guest OS can optionally use the TCE bypass to improve performance in
suitable situations.
The mechanism used is a per-device flag which disables TCE translation.
The flag is toggled with some (hypervisor-implemented) RTAS methods.
This patch implements the infrastructure and hypercalls necessary for
the PAPR specified Virtual SCSI interface. This is the normal method
for providing (virtual) disks to PAPR partitions.
This patch implements the infrastructure and hypercalls necessary for the
PAPR specified CRQ (Command Request Queue) mechanism. This general
request queueing system is used by many of the PAPR virtual IO devices,
including the virtual scsi adapter.
David Gibson [Fri, 1 Apr 2011 04:15:28 +0000 (15:15 +1100)]
Implement TCE translation for sPAPR VIO
This patch implements the necessary infrastructure and hypercalls for
sPAPR's TCE (Translation Control Entry) IOMMU mechanism. This is necessary
for all virtual IO devices which do DMA (i.e. nearly all of them).
David Gibson [Fri, 1 Apr 2011 04:15:27 +0000 (15:15 +1100)]
Add (virtual) interrupt to PAPR virtual tty device
Now that we have implemented the PAPR "xics" virtualized interrupt
controller, we can add interrupts in PAPR VIO devices. This patch adds
interrupt support to the PAPR virtual tty/console device.
David Gibson [Fri, 1 Apr 2011 04:15:26 +0000 (15:15 +1100)]
Add PAPR H_VIO_SIGNAL hypercall and infrastructure for VIO interrupts
This patch adds infrastructure to support interrupts from PAPR virtual IO
devices. This includes correctly advertising those interrupts in the
device tree, and implementing the H_VIO_SIGNAL hypercall, used to
enable and disable individual device interrupts.
David Gibson [Fri, 1 Apr 2011 04:15:25 +0000 (15:15 +1100)]
Implement the PAPR (pSeries) virtualized interrupt controller (xics)
PAPR defines an interrupt control architecture which is logically divided
into ICS (Interrupt Control Presentation, each unit is responsible for
presenting interrupts to a particular "interrupt server", i.e. CPU) and
ICS (Interrupt Control Source, each unit responsible for one or more
hardware interrupts as numbered globally across the system). All PAPR
virtual IO devices expect to deliver interrupts via this mechanism. In
Linux, this interrupt controller system is handled by the "xics" driver.
On pSeries systems, access to the interrupt controller is virtualized via
hypercalls and RTAS methods. However, the virtualized interface is very
similar to the underlying interrupt controller hardware, and similar PICs
exist un-virtualized in some other systems.
This patch implements both the ICP and ICS sides of the PAPR interrupt
controller. For now, only the hypercall virtualized interface is provided,
however it would be relatively straightforward to graft an emulated
register interface onto the underlying interrupt logic if we want to add
a machine with a hardware ICS/ICP system in the future.
There are some limitations in this implementation: it is assumed for now
that only one instance of the ICS exists, although a full xics system can
have several, each responsible for a different group of hardware irqs.
ICP/ICS can handle both level-sensitve (LSI) and message signalled (MSI)
interrupt inputs. For now, this implementation supports only MSI
interrupts, since that is used by PAPR virtual IO devices.
David Gibson [Fri, 1 Apr 2011 04:15:24 +0000 (15:15 +1100)]
Implement assorted pSeries hcalls and RTAS methods
This patch adds several small utility hypercalls and RTAS methods to
the pSeries platform emulation. Specifically:
* 'display-character' rtas call
This just prints a character to the console, it's occasionally used
for early debug of the OS. The support includes a hack to make this
RTAS call respond on the normal token value present on real hardware,
since some early debugging tools just assume this value without
checking the device tree.
* 'get-time-of-day' rtas call
This one just takes the host real time, converts to the PAPR described
format and returns it to the guest.
* 'power-off' rtas call
This one shuts down the emulated system.
* H_DABR hypercall
On pSeries, the DABR debug register is usually a hypervisor resource
and virtualized through this hypercall. If the hypercall is not
present, Linux will under some circumstances attempt to manipulate the
DABR directly which will fail on this emulated machine.
This stub implementation is enough to stop that behaviour, although it
doesn't actually implement the requested DABR operations as yet.
David Gibson [Fri, 1 Apr 2011 04:15:23 +0000 (15:15 +1100)]
Implement hcall based RTAS for pSeries machines
On pSeries machines, operating systems can instantiate "RTAS" (Run-Time
Abstraction Services), a runtime component of the firmware which implements
a number of low-level, infrequently used operations. On logical partitions
under a hypervisor, many of the RTAS functions require hypervisor
privilege. For simplicity, therefore, hypervisor systems typically
implement the in-partition RTAS as just a tiny wrapper around a hypercall
which actually implements the various RTAS functions.
This patch implements such a hypercall based RTAS for our emulated pSeries
machine. A tiny in-partition "firmware" calls a new hypercall, which
looks up available RTAS services in a table.
David Gibson [Fri, 1 Apr 2011 04:15:22 +0000 (15:15 +1100)]
Virtual hash page table handling on pSeries machine
On pSeries logical partitions, excepting the old POWER4-style full system
partitions, the guest does not have direct access to the hardware page
table. Instead, the pagetable exists in hypervisor memory, and the guest
must manipulate it with hypercalls.
However, our current pSeries emulation more closely resembles the old
style where the guest must set up and handle the pagetables itself. This
patch converts it to act like a modern partition.
This involves two things: first, the hash translation path is modified to
permit the has table to be stored externally to the emulated machine's
RAM. The pSeries machine init code configures the CPUs to use this mode.
Secondly, we emulate the PAPR hypercalls for manipulating the external
hashed page table.
This patch adds a "pseries" machine to qemu. This aims to emulate a
logical partition on an IBM pSeries machine, compliant to the
"PowerPC Architecture Platform Requirements" (PAPR) document.
This initial version is quite limited, it implements a basic machine
and PAPR hypercall emulation. So far only one hypercall is present -
H_PUT_TERM_CHAR - so that a (write-only) console is available.
Multiple CPUs are permitted, with SMP entry handled kexec() style.
The machine so far more resembles an old POWER4 style "full system
partition" rather than a modern LPAR, in that the guest manages the
page tables directly, rather than via hypercalls.
The machine requires qemu to be configured with --enable-fdt. The
machine can (so far) only be booted with -kernel - i.e. no partition
firmware is provided.
David Gibson [Fri, 1 Apr 2011 04:15:19 +0000 (15:15 +1100)]
Add POWER7 support for ppc
This adds emulation support for the recent POWER7 cpu to qemu. It's far
from perfect - it's missing a number of POWER7 features so far, including
any support for VSX or decimal floating point instructions. However, it's
close enough to boot a kernel with the POWER7 PVR.
David Gibson [Fri, 1 Apr 2011 04:15:18 +0000 (15:15 +1100)]
Support 1T segments on ppc
Traditionally, the "segments" used for the two-stage translation used on
powerpc MMUs were 256MB in size. This was the only option on all hash
page table based 32-bit powerpc cpus, and on the earlier 64-bit hash page
table based cpus. However, newer 64-bit cpus also permit 1TB segments
This patch adds support for 1TB segment translation to the qemu code.
David Gibson [Fri, 1 Apr 2011 04:15:17 +0000 (15:15 +1100)]
Better factor the ppc hash translation path
Currently the path handling hash page table translation in get_segment()
has a mix of common and 32 or 64 bit specific code. However the
division is not done terribly well which results in a lot of messy code
flipping between common and divided paths.
This patch improves the organization, consolidating several divided paths
into one. This in turn allows simplification of some code in
get_segment(), removing a number of ugly interim variables.
This new factorization will also make it easier to add support for the 1T
segments added in newer CPUs.
David Gibson [Fri, 1 Apr 2011 04:15:16 +0000 (15:15 +1100)]
Use "hash" more consistently in ppc mmu code
Currently, get_segment() has a variable called hash. However it doesn't
(quite) get the hash value for the ppc hashed page table. Instead it
gets the hash shifted - effectively the offset of the hash bucket within
the hash page table.
As well, as being different to the normal use of plain "hash" in the
architecture documentation, this usage necessitates some awkward 32/64
dependent masks and shifts which clutter up the path in get_segment().
This patch alters the code to use raw hash values through get_segment()
including storing raw hashes instead of pte group offsets in the ctx
structure. This cleans up the path noticeably.
This does necessitate 32/64 dependent shifts when the hash values are
taken out of the ctx structure and used, but those paths already have
32/64 bit variants so this is less awkward than it was in get_segment().
David Gibson [Fri, 1 Apr 2011 04:15:15 +0000 (15:15 +1100)]
Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1
contains both the base address of the encoded size (hashed) page tables.
At present, we interpret the SDR1 value within the address translation
path. But because the encodings of the size for 32-bit and 64-bit are
different this makes for a confusing branch on the MMU type with a bunch
of curly shifts and masks in the middle of the translate path.
This patch cleans things up by moving the interpretation on SDR1 into the
helper function handling the write to the register. This leaves a simple
pre-sanitized base address and mask for the hash table in the CPUState
structure which is easier to work with in the translation path.
This makes the translation path more readable. It addresses the FIXME
comment currently in the mtsdr1 helper, by validating the SDR1 value during
interpretation. Finally it opens the way for emulating a pSeries-style
partition where the hash table used for translation is not mapped into
the guests's RAM.
David Gibson [Fri, 1 Apr 2011 04:15:14 +0000 (15:15 +1100)]
Clean up slb_lookup() function
The slb_lookup() function, used in the ppc translation path returns a
number of slb entry fields in reference parameters. However, only one
of the two callers of slb_lookup() actually wants this information.
This patch, therefore, makes slb_lookup() return a simple pointer to the
located SLB entry (or NULL), and the caller which needs the fields can
extract them itself.
David Gibson [Fri, 1 Apr 2011 04:15:13 +0000 (15:15 +1100)]
Correct ppc popcntb logic, implement popcntw and popcntd
qemu already includes support for the popcntb instruction introduced
in POWER5 (although it doesn't actually allow you to choose POWER5).
However, the logic is slightly incorrect: it will generate results
truncated to 32-bits when the CPU is in 32-bit mode. This is not
normal for powerpc - generally arithmetic instructions on a 64-bit
powerpc cpu will generate full 64 bit results, it's just that only the
low 32 bits will be significant for condition codes.
This patch corrects this nit, which actually simplifies the code slightly.
In addition, this patch implements the popcntw and popcntd
instructions added in POWER7, in preparation for allowing POWER7 as an
emulated CPU.
David Gibson [Fri, 1 Apr 2011 04:15:12 +0000 (15:15 +1100)]
Implement missing parts of the logic for the POWER PURR
The PURR (Processor Utilization Resource Register) is a register found
on recent POWER CPUs. The guts of implementing it at least enough to
get by are already present in qemu, however some of the helper
functions needed to actually wire it up are missing.
This patch adds the necessary glue, so that the PURR can be wired up
when we implement newer POWER CPU targets which include it.
David Gibson [Fri, 1 Apr 2011 04:15:11 +0000 (15:15 +1100)]
Implement PowerPC slbmfee and slbmfev instructions
For a 64-bit PowerPC target, qemu correctly implements translation
through the segment lookaside buffer. Likewise it supports the
slbmte instruction which is used to load entries into the SLB.
However, it does not emulate the slbmfee and slbmfev instructions
which read SLB entries back into registers. Because these are
only occasionally used in guests (mostly for debugging) we get
away with it.
However, given the recent SLB cleanups, it becomes quite easy to
implement these, and thereby allow, amongst other things, a guest
Linux to use xmon's command to dump the SLB.
David Gibson [Fri, 1 Apr 2011 04:15:10 +0000 (15:15 +1100)]
Add a hook to allow hypercalls to be emulated on PowerPC
PowerPC and POWER chips since the POWER4 and 970 have a special
hypervisor mode, and a corresponding form of the system call
instruction which traps to the hypervisor.
qemu currently has stub implementations of hypervisor mode. That
is, the outline is there to allow qemu to run a PowerPC hypervisor
under emulation. There are a number of details missing so this
won't actually work at present, but the idea is there.
What there is no provision at all, is for qemu to instead emulate
the hypervisor itself. That is to have hypercalls trap into qemu
and their result be emulated from qemu, rather than running
hypervisor code within the emulated system.
Hypervisor hardware aware KVM implementations are in the works and
it would be useful for debugging and development to also allow
full emulation of the same para-virtualized guests as such a KVM.
Therefore, this patch adds a hook which will allow a machine to
set up emulation of hypervisor calls.
David Gibson [Fri, 1 Apr 2011 04:15:09 +0000 (15:15 +1100)]
Allow qemu_devtree_setprop() to take arbitrary values
Currently qemu_devtree_setprop() expects the new property value to be
given as a uint32_t *. While property values consisting of u32s are
common, in general they can have any bytestring value.
Therefore, this patch alters the function to take a void * instead,
allowing callers to easily give anything as the property value.
David Gibson [Fri, 1 Apr 2011 04:15:08 +0000 (15:15 +1100)]
Clean up PowerPC SLB handling code
Currently the SLB information when emulating a PowerPC 970 is
storeed in a structure with the unhelpfully named fields 'tmp'
and 'tmp64'. While the layout in these fields does match the
description of the SLB in the architecture document, it is not
convenient either for looking up the SLB, or for emulating the
slbmte instruction.
This patch, therefore, reorganizes the SLB entry structure to be
divided in the the "ESID related" and "VSID related" fields as
they are divided in instructions accessing the SLB.
In addition to making the code smaller and more readable, this will
make it easier to implement for the 1TB segments used in more
recent PowerPC chips.
Paolo Bonzini [Wed, 9 Mar 2011 17:21:10 +0000 (18:21 +0100)]
add a service to reap zombies, use it in SLIRP
SLIRP -smb support wants to fork a process and forget about reaping it.
To please it, add a generic service to register a process id and let
QEMU reap it. In the future it could be enhanced to pass a status,
but this would be unused.
With this in place, the SIGCHLD signal handler would not stomp on pclose
anymore.
Commit c81131db15dd1844d0db1d51f3cd7a105cfd2cf3
detects old guests by comparing virtio and
PCI status. It attempts to do this on load,
as well, but load_config callback in a binding
is invoked too early and so the virtio status
isn't set yet.
We could add yet another callback to the
binding, to invoke after load, but it
seems easier to reuse the existing vmstate
callback.
Gleb Natapov [Tue, 15 Mar 2011 11:56:04 +0000 (13:56 +0200)]
report that QEMU process was killed by a signal
Currently when rogue script kills QEMU process (using TERM/INT/HUP
signal) it looks indistinguishable from system shutdown. Lets report
that QEMU was killed and leave some clues about the killer identity.
AFAIK, extraction is optional to get vlans working. The driver
requests rx detagging but should not assume that it was done. Under
Linux, the mac layer will catch the vlan ethertype. I only added this
part for completeness (to emulate the hardware more truthfully...) Signed-off-by: Blue Swirl <[email protected]>
Peter Maydell [Wed, 16 Mar 2011 15:21:31 +0000 (15:21 +0000)]
tcg/arm: Support host code being compiled for Thumb
Although the TCG generated code is always in ARM mode, it is possible
that the host code was compiled by gcc in Thumb mode (this is often the
default for Linux distributions targeting ARM v7 only). Handle this
by using BLX imm when doing a call from ARM into Thumb mode.
Since BLX imm is not a conditionalisable instruction, we make
tcg_out_call() no longer take a condition code; we were only ever
using it with COND_AL anyway.
Jes Sorensen [Wed, 9 Mar 2011 13:31:06 +0000 (14:31 +0100)]
qmp-commands.hx: Clean up mess of client_migrate_info
client_migrate_info was put into qmp-commands.hx in the middle of
migrate_set_speed, between the command and it's description. In
addition client_migrate_info put the description before the command
itself, which is the wrong order.
Jes Sorensen [Wed, 16 Mar 2011 12:33:32 +0000 (13:33 +0100)]
Introduce -display none
New option -display none. This option differs from -nographic by not
trying to take control of stdio etc. but instead behaves as if a
graphics display is enabled, except that it doesn't show one.
Peter Maydell [Mon, 14 Mar 2011 15:37:13 +0000 (15:37 +0000)]
target-arm: use make_float32() to make constant floats for VRSQRTS
The preferred way to create a constant floating point value is to use
make_float32() rather than doing a runtime int32_to_float32().
Convert the code in the VRSQRTS helper to work this way.
Peter Maydell [Mon, 14 Mar 2011 15:37:12 +0000 (15:37 +0000)]
target-arm: Fix VRECPS edge cases handling
Correct the handling of edge cases for the VRECPS instruction:
* this is a Neon instruction so uses the "standard FPSCR value"
* (zero, inf) is a special case which returns 2.0
Peter Maydell [Fri, 11 Mar 2011 10:09:58 +0000 (10:09 +0000)]
target-arm: Set Q bit for overflow in SMUAD and SMLAD
SMUAD and SMLAD are supposed to set the Q bit if the addition of
the two 16x16 multiply products and optional accumulator overflows
considered as a signed value. However we were only doing this check
for the addition of the accumulator, not when adding the products,
with the effect that we were mishandling the edge case where
both inputs are 0x80008000.
Peter Maydell [Thu, 10 Mar 2011 18:51:49 +0000 (18:51 +0000)]
target-arm: Fix GE bits for v6media signed modulo arithmetic
Fix the signed modulo arithmetic helpers for the v6media
instructions (SADD8, SSUB8, SADD16, SSUB16, SASX, SSAX) to set
the GE bits correctly (based on the result of the add or subtract
before it is truncated to 16 bits, not after).
Peter Maydell [Thu, 10 Mar 2011 16:48:49 +0000 (16:48 +0000)]
target-arm: Fix UNDEF cases in Thumb load/store
Decode of Thumb load/store was merging together the cases of 'bit 11==0'
(reg+reg LSL imm) and 'bit 11==1' (reg+imm). This happens to work for
valid instruction patterns but meant that we would not UNDEF for the
cases the architecture mandates that we must. Make the decode actually
look at bit 11 as well as [10..8] so that we UNDEF in the right places.
This change also removes what was a spurious unreachable 'case 8',
and correctly frees TCG temporaries on the illegal-insn codepaths.
Peter Maydell [Fri, 25 Feb 2011 10:27:40 +0000 (10:27 +0000)]
linux-user: Fix unlock_user() call in return from poll()
Correct the broken attempt to calculate the third argument
to unlock_user() in the code path which unlocked the pollfd
array on return from poll() and ppoll() emulation. (This
only caused a problem if unlock_user() wasn't a no-op, eg
if DEBUG_REMAP is defined.)
Gleb Natapov [Mon, 31 Jan 2011 13:11:01 +0000 (15:11 +0200)]
fix linuxboot.bin and multiboot.bin to not hijack int19
Currently linuxboot.bin and multiboot.bin option roms override int19
vector to intercept boot process. No sane option rom should do that.
Provide bev entry instead that will be called by BIOS if option rom
is selected for booting.
Anthony Liguori [Tue, 15 Mar 2011 16:22:12 +0000 (11:22 -0500)]
seabios: update to latest git
- cc97564 Add config option to permit running option roms with bad checksums.
- 424f217 Add config option to disable MTRR initialization.
- fb2f10d Prep version for next release.
- f18b09b Update version to 0.6.2
- 20fcf9b lets pretend that RTC can be used to wakeup from S4
- 1efb10b Expand user configurable parameters in Kconfig.
- 3dba4c2 Support non-local build directory - allow "make OUT=abc/" to work.
- 42d9771 The vgabios build must depend on autoconf.h.
- 32aa9f3 fix parallel compilation of SeaBIOS
- 713be89 Start using Kconfig to configure SeaBIOS settings.
- b623e7c Change kconfig to emit disabled symbols in autoconf.h.
- 0da7bfd Build changes for Linux kconfig code to work in seabios dir structure.
- a4c5daf Initial commit of Kconfig build tool.
- 4d0c592 Minor boot fixes.
- 812478e Minor comment / code layout improvement to romlayout.S.
- 6fc7cf1 Fix to prevent infinite loop in build_pci_path().
- f5154e2 support T13 EDD3.0 spec
- d08eb9c Add ability to track PCI paths and add to build_pci_path().
- 89a1efd Move the CBFS payload setup to later in the boot.
- 9e881a3 Extract space trimming code from ATA and use in USB and bootorder code.
- 3c241ed seabios: acpi: add _RMV control method for PCI devices
- c2002a1 Add support for finding the boot priority of USB drives.
- a5f2b91 Extend 'usb_pipe' to track the controller and ports of each device.
- 8bf5503 Add functions for boot device path parsing.
- c4bd3b9 Use bootprio_find_named_rom() for ramdisk and cbfs payload priorities.
- ca2bc1c Remove drive->desc field.
- f13a180 Minor reorganization of some of the boot_xxx code in boot.c.
- 3da2c1c Move IPL.fw_bootorder to static variables in boot.c.
- 7bb1584 Move IPL.bev to static variables in boot.c
- baaadb6 Move IPL.checkfloppysig to a global (CheckFloppySig) in boot.c.
- a0842f8 Remove Drives global struct in favor of independent global variables.
- ecbcf77 Don't access drive_g->desc from boot_cdrom().
- 551caa2 Simplify keyboard reading code in the interactive boot menu.
- 697e63c Call setup_translation() from map_hd_drive().
- 3c5e0e1 Rename add_ordered_drive() to add_drive() and use in map_hd_drive().
- 031ef55 Add stubs to permit devices to specify their boot priority.
- 72eee3e Simplify boot ordering by building an inclusive boot list.
- ce24be5 Populate drive_g->desc prior to calling add_bcv_internal().
- 74fd942 pciinit: fix off-by-one
- 311f887 Minor build fixes.
- bca3a87 Track the source of each optionrom deployed.
- c6629e0 Support qemu based romfile wrappers called out of order.
- d1a1746 Breakup boot_setup() bootorder code into its own function.
- f9b0930 Add romfile_loadfile() helper function.
- b9a7591 Read bootorder file into memory.
- 2e109a6 Add strchr() function.
- 1703ea2 Add romfile_name() function.
- b674152 Add BAID for ahci cdrom.
- f77e179 Provide full EDD 3.0 info for virtio disk
- 67863be Enhance layoutrom.py to work around a binutils quirk.
- 4c90a20 Create separate IPL entry for each CD/DVD
- 0e6f636 ahci: set controller id
- 1e924bb ahci: fix off-by-one in port count
- 7eb0222 ahci: enable io/mem/dma
- c19fc71 ahci: set dma feature flag
- 80c2b6e Check if capability enabled in XXX_cmd_data functions.
- f3fe3aa Require a "_cfuncXX_" symbol prefix for inter-mode c function references.
- d52fdf6 add ahci support
- 54fa8ec ata: make helpers available
- 0a80608 util: add memset_fl()
- f1f18eb pci: add helper functions for mmio bar access from real mode.
- af9629b Enhance call32() to pass a parameter to called function.
- 4057f98 Don't pass return address to transition(32,16,16big) on stack.
- e2623fc pciinit: use pci_region functions.
- 58a38e8 pci: introduce pci_region to manage pci io/memory/prefmemory regions.
- 6d5a217 mark irq9 active high in DSDT
- 9433098 Report meaningful error if pyserial not present in tools/readserial.py
- 94dc9c4 Show size of non-relocatable runtime code during build.
- 4d96edc Cleanup - it's no longer necessary to manually reset global variables.
- a899945 Allow rom to grow to 256K.
- 4a446d7 Fix typo preventing relocated space from being used for option roms.
- 0f67397 fix virtio-blk failure after reboot
- d4bded4 Add a debug method to AML code.
- 2f96800 Warn that ohci bulk is not supported.
- e826465 Enable optionroms to use freed space due to CONFIG_RELOCATE_INIT.
- 7f55fd3 Move the 32bit init code to high memory at runtime.
- 025cabd Move init code from _start() to post().
- 12fa24a Add memalign_tmp() helper function.
- 244caf8 Try to hard-reboot on rerun of post even on emulators.
- 5bd01de Don't do shadow copying of optionroms when CONFIG_OPTIONROMS_DEPLOYED.
- adaf373 Try to hard-reboot processor on rerun of post under coreboot.
- 402fd9c Enhance build to emit relocation information.
- d1b4f96 Separate out init code from the rest of the 32bit flat code.
- 1a4885e Modify tools/layoutrom.py to use classes instead of tuples.
- 6c2e781 Use str.startswith() in python scripts.
- d9c916e Prep version for next release.
Andreas Färber [Mon, 7 Mar 2011 00:34:05 +0000 (01:34 +0100)]
softfloat: Resolve type mismatches between declaration and implementation
The original SoftFloat 2.0b library avoided the use of custom integer types
in its public headers. This requires the definitions of int{8,16,32,64} to
match the assumptions in the declarations. This breaks on BeOS R5 and Haiku/x86,
where int32 is defined in {be,os}/support/SupportDefs.h in terms of a long
rather than an int. Spotted by Michael Lotz.
Since QEMU already breaks this distinction by defining those types just above,
do use them for consistency and to allow #ifndef'ing them out as done for
[u]int16 on AIX.
Andreas Färber [Mon, 7 Mar 2011 00:34:04 +0000 (01:34 +0100)]
softfloat: Prepend QEMU-style header with derivation notice
The SoftFloat license requires "prominent notice that the work
is derivative". Having added features like improved 16-bit support
for arm already, add such a notice to the sources.
softfloat-native.[ch] are not under the SoftFloat license
and thus are not changed.
The PCI/PCI-X Family of Gigabit Ethernet Controllers Software
Developer’s Manual states the following about the POPTS field:
Provides a number of options which control the handling of this
packet. This field is ignored except on the first data descriptor of
a packet.
The current implementation always loads the field and its checksum
offload flags. This patch uses only the first descriptor's POPTS field
in order to comply with the specification.
When Solaris sends multi-descriptor packets it fills in POPTS for the
first descriptor only. Therefore this patch is necessary in order to
perform checksum offload correctly for multi-descriptor packets.
Aurelien Jarno [Mon, 21 Mar 2011 20:28:38 +0000 (21:28 +0100)]
Merge branch 'for-anthony' of git://github.com/bonzini/qemu
* 'for-anthony' of git://github.com/bonzini/qemu:
remove qemu_get_clock
add a generic scaling mechanism for timers
change all other clock references to use nanosecond resolution accessors
change all rt_clock references to use millisecond resolution accessors
add more helper functions with explicit milli/nanosecond resolution
Aurelien Jarno [Mon, 21 Mar 2011 20:28:19 +0000 (21:28 +0100)]
Merge branch 'for-anthony' of git://repo.or.cz/qemu/kevin
* 'for-anthony' of git://repo.or.cz/qemu/kevin:
Add qcow2 documentation
hw/xen_disk: aio_inflight not released in handling ioreq when nr_segments==0
Improve error handling in do_snapshot_blkdev()
Fix ATA SMART and CHECK POWER MODE
Don't allow multiwrites against a block device without underlying medium
tools: Use real async.c instead of stubs
Add error message for loading snapshot without VM state
block/qcow: Don't ignore immediate read/write and other failures
block/vdi: Don't ignore immediate read/write failures
Aurelien Jarno [Mon, 7 Mar 2011 06:17:49 +0000 (07:17 +0100)]
rbd: don't link with -lcrypto
rbd support tries to both link with -lrados and -lcrypto. While the
first one is of course necessary, the second is not necessary (only
librados ifself needs to link with libcrypto).
This fixes a licensing issue: qemu as a whole is GPL v2, and thus can't
be linked with OpenSSL without an exception in the license, which seems
difficult to get given the number of persons involved.
Peter Maydell [Mon, 7 Mar 2011 11:10:31 +0000 (11:10 +0000)]
hw/arm_sysctl.c: Add the Versatile Express system registers
Add support for the Versatile Express SYS_CFG registers, which provide
a generic means of reading or writing configuration information from
various parts of the board. We only implement shutdown and reset.
Also make the RESETCTL register RAZ/WI on Versatile Express rather
than reset the board. Other system registers are generally the same
as Versatile and Realview.
This includes a VMState version number bump for arm_sysctl,
since we have new register state to preserve. It also adds
sys_mci to the VMState while we're bumping the version number
(an accidental omission from commit b50ff6f5).
Amit Shah [Tue, 15 Mar 2011 08:43:09 +0000 (14:13 +0530)]
virtio-console: Keep chardev open for other users after hot-unplug
After a hot-unplug operation, the previous behaviour was to close the
chardev. That meant the chardev couldn't be re-used. Also, since
chardev hot-plug isn't possible so far, this means virtio-console
hot-plug isn't feasible as well.
With this change, the chardev is kept around. A new virtio-console
channel can then be hot-plugged with the same chardev and things will
continue to work.
Amit Shah [Thu, 3 Mar 2011 07:59:45 +0000 (13:29 +0530)]
virtio-serial: Don't clear ->have_data() pointer after unplug
After a port unplug operation, the port->info->have_data() pointer was
set to NULL. The problem is, the ->info struct is shared by all ports,
effectively disabling writes to other ports.
Amit Shah [Thu, 3 Feb 2011 07:35:07 +0000 (13:05 +0530)]
virtio-serial: Disallow generic ports at id 0
Port 0 is reserved for virtconsole devices for backward compatibility
with the old -virtioconsole (from qemu 0.12) device type.
libvirt prior to commit 8e28c5d40200b4c5d483bd585d237b9d870372e5 used
port 0 for generic ports. libvirt will no longer do that, but disallow
instantiating generic ports at id 0 from qemu as well.
Amit Shah [Thu, 3 Feb 2011 05:52:32 +0000 (11:22 +0530)]
virtio-serial: Use a struct to pass config information from proxy
Instead of using a single variable to pass to the virtio_serial_init
function, use a struct so that expanding the number of variables to be
passed on later is easier.
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