target/mips: Declare gen_msa/_branch() in 'translate.h'

Make gen_msa() and gen_msa_branch() public declarations
so we can keep calling them once extracted from the big
translate.c in the next commit.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201215225757[email protected]>
Tested-by: Jiaxun Yang <[email protected]>

target/mips: Extract MSA helper definitions

Keep all MSA-related code altogether.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20201120210844.2625602[email protected]>
Tested-by: Jiaxun Yang <[email protected]>

target/mips: Extract MSA helpers from op_helper.c

We have ~400 lines of MSA helpers in the generic op_helper.c,
move them with the other helpers in 'msa_helper.c'.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201123204448.3260804[email protected]>
Tested-by: Jiaxun Yang <[email protected]>

target/mips: Move msa_reset() to msa_helper.c

translate_init.c.inc mostly contains CPU definitions.
msa_reset() doesn't belong here, move it with the MSA
helpers.

One comment style is updated to avoid checkpatch.pl warning.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201215225757[email protected]>
Tested-by: Jiaxun Yang <[email protected]>

target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()

In preparation of using the decodetree script, explode
gen_msa_branch() as following:

- OPC_BZ_V              -> BxZ_V(EQ)
- OPC_BNZ_V             -> BxZ_V(NE)
- OPC_BZ_[BHWD]         -> BxZ(false)
- OPC_BNZ_[BHWD]        -> BxZ(true)

Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Jiaxun Yang <[email protected]>
Message-Id: <20201208003702.4088927[email protected]>

target/mips: Remove CPUMIPSState* argument from gen_msa*() methods

The gen_msa*() methods don't use the "CPUMIPSState *env"
argument. Remove it to simplify.

Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Jiaxun Yang <[email protected]>
Message-Id: <20201208003702.4088927[email protected]>

target/mips: Extract msa_translate_init() from mips_tcg_init()

The msa_wr_d[] registers are only initialized/used by MSA.

They are declared static. We want to move them to the new
'msa_translate.c' unit in few commits, without having to
declare them global (with extern).

Extract first the logic initialization of the MSA registers
from the generic initialization. We will later move this
function along with the MSA registers to the new C unit.

Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Jiaxun Yang <[email protected]>
Message-Id: <20201208003702.4088927[email protected]>

target/mips: Alias MSA vector registers on FPU scalar registers

Commits 863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.

It is not very clear to have FPU registers displayed with MSA
register names, even if MSA ASE is not present.

Instead of aliasing FPU registers to the MSA ones (even when MSA
is absent), we now alias the MSA ones to the FPU ones (only when
MSA is present).

Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Jiaxun Yang <[email protected]>
Message-Id: <20201208003702.4088927[email protected]>

target/mips: Remove now unused ASE_MSA definition

We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.

Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Jiaxun Yang <[email protected]>
Message-Id: <20201208003702.4088927[email protected]>

target/mips: Simplify MSA TCG logic

Only decode MSA opcodes if MSA is present (implemented).

Now than check_msa_access() will only be called if MSA is
present, the only way to have MIPS_HFLAG_MSA unset is if
MSA is disabled (bit CP0C5_MSAEn cleared, see previous
commit). Therefore we can remove the 'reserved instruction'
exception.

Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Jiaxun Yang <[email protected]>
Message-Id: <20201208003702.4088927[email protected]>

target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA

MSA presence is expressed by the MSAP bit of CP0_Config3.
We don't need to check anything else.

Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Jiaxun Yang <[email protected]>
Message-Id: <20201208003702.4088927[email protected]>

target/mips: Simplify msa_reset()

Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.

Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Jiaxun Yang <[email protected]>
Message-Id: <20201208003702.4088927[email protected]>

target/mips: Introduce ase_msa_available() helper

Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.

Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Jiaxun Yang <[email protected]>
Message-Id: <20201208003702.4088927[email protected]>

target/mips/translate: Expose check_mips_64() to 32-bit mode

To allow compiling 64-bit specific translation code more
generically (and removing #ifdef'ry), allow compiling
check_mips_64() on 32-bit targets.
If ever called on 32-bit, we obviously emit a reserved
instruction exception.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Jiaxun Yang <[email protected]>
Message-Id: <20201215225757[email protected]>

target/mips/translate: Extract decode_opc_legacy() from decode_opc()

As we will slowly move to decodetree generated decoders,
extract the legacy decoding from decode_opc(), so new
decoders are added in decode_opc() while old code is
removed from decode_opc_legacy().

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201215225757[email protected]>

target/mips: Only build TCG code when CONFIG_TCG is set

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201206233949.3783184[email protected]>

target/mips: Extract FPU specific definitions to translate.h

Extract FPU specific definitions that can be used by
ISA / ASE / extensions to translate.h header.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201214183739[email protected]>

target/mips: Declare generic FPU / Coprocessor functions in translate.h

Some FPU / Coprocessor translation functions / registers can be
used by ISA / ASE / extensions out of the big translate.c file.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201214183739[email protected]>

target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction

gen_reserved_instruction() is easier to read than
generate_exception_end(ctx, EXCP_RI), replace it.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201214183739[email protected]>

target/mips: Replace gen_exception_err(err=0) by gen_exception_end()

generate_exception_err(err=0) is simply generate_exception_end().

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201214183739[email protected]>

target/mips/translate: Add declarations for generic code

Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201207235539.4070364[email protected]>

target/mips/translate: Extract DisasContext structure

Extract DisasContext to a new 'translate.h' header so
different translation files (ISA, ASE, extensions)
can use it.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201207235539.4070364[email protected]>

target/mips: Rename translate_init.c as cpu-defs.c

This file is not TCG specific, contains CPU definitions
and is consumed by cpu.c. Rename it as such.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201214183739[email protected]>

target/mips: Move mmu_init() functions to tlb_helper.c

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201206233949.3783184[email protected]>

target/mips: Fix code style for checkpatch.pl

We are going to move this code, fix its style first.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201206233949.3783184[email protected]>

target/mips: Rename helper.c as tlb_helper.c

This file contains functions related to TLB management,
rename it as 'tlb_helper.c'.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201206233949.3783184[email protected]>

target/mips: Move common helpers from helper.c to cpu.c

The rest of helper.c is TLB related. Extract the non TLB
specific functions to cpu.c, so we can rename helper.c as
tlb_helper.c in the next commit.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201214183739[email protected]>

target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201214183739[email protected]>

target/mips: Add !CONFIG_USER_ONLY comment after #endif

To help understand ifdef'ry, add comment after #endif.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201214183739[email protected]>

target/mips: Extract FPU helpers to 'fpu_helper.h'

Extract FPU specific helpers from "internal.h" to "fpu_helper.h".

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20201120210844.2625602[email protected]>

target/mips: Inline cpu_state_reset() in mips_cpu_reset()

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201214183739[email protected]>

target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6

The MIPS ISA release 6 is common to 32/64-bit CPUs.

To avoid holes in the insn_flags type, update the
definition with the next available bit.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5

The MIPS ISA release 5 is common to 32/64-bit CPUs.

To avoid holes in the insn_flags type, update the
definition with the next available bit.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3

The MIPS ISA release 3 is common to 32/64-bit CPUs.

To avoid holes in the insn_flags type, update the
definition with the next available bit.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2

The MIPS ISA release 2 is common to 32/64-bit CPUs.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1

The MIPS ISA release '1' is common to 32/64-bit CPUs.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6

Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.

For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5

Use the single ISA_MIPS32R5 definition to check if the Release 5
ISA is supported, whether the CPU support 32/64-bit.

For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R5 in few commits.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3

Use the single ISA_MIPS32R3 definition to check if the Release 3
ISA is supported, whether the CPU support 32/64-bit.

For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R3 in few commits.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2

Use the single ISA_MIPS32R2 definition to check if the Release 2
ISA is supported, whether the CPU support 32/64-bit.

For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R2 in few commits.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1

Use the single ISA_MIPS32 definition to check if the Release 1
ISA is supported, whether the CPU support 32/64-bit.

For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R1 in few commits.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()

Directly check if the CPU supports 64-bit with the recently
added cpu_type_is_64bit() helper (inlined).

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()

MIPS 64-bit ISA is introduced with MIPS3.

Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
and the cpu_type_is_64bit() method to check if a CPU supports
this ISA (thus is 64-bit).

Suggested-by: Jiaxun Yang <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1

'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Reorder CPU_MIPS5 definition

Move CPU_MIPS5 after CPU_MIPS4 :)

Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment

Remove a comment added 12 years ago but never used (commit
b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20210104221154.3127610[email protected]>

target/mips/addr: Add translation helpers for KSEG1

It's useful for bootloader to do I/O operations.

Signed-off-by: Jiaxun Yang <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Huacai Chen <[email protected]>
Message-Id: <20201215064507[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>

target/mips: Replace CP0_Config0 magic values by proper definitions

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201201132817.2863301[email protected]>

target/mips: Add CP0 Config0 register definitions for MIPS3 ISA

The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20201201132817.2863301[email protected]>

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210113' into staging

Improvements to tcg constant handling.
Force utf8 for decodetree.

# gpg: Signature made Thu 14 Jan 2021 02:15:42 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210113: (24 commits)
  decodetree: Open files with encoding='utf-8'
  tcg/aarch64: Use tcg_constant_vec with tcg vec expanders
  tcg/ppc: Use tcg_constant_vec with tcg vec expanders
  tcg: Remove tcg_gen_dup{8,16,32,64}i_vec
  tcg/i386: Use tcg_constant_vec with tcg vec expanders
  tcg: Add tcg_reg_alloc_dup2
  tcg: Remove movi and dupi opcodes
  tcg/tci: Add special tci_movi_{i32,i64} opcodes
  tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders
  tcg: Use tcg_constant_{i32,i64} with tcg plugins
  tcg: Use tcg_constant_{i32,i64} with tcg int expanders
  tcg: Use tcg_constant_i32 with icount expander
  tcg: Convert tcg_gen_dupi_vec to TCG_CONST
  tcg/optimize: Use tcg_constant_internal with constant folding
  tcg/optimize: Adjust TempOptInfo allocation
  tcg/optimize: Improve find_better_copy
  tcg: Introduce TYPE_CONST temporaries
  tcg: Expand TempOptInfo to 64-bits
  tcg: Rename struct tcg_temp_info to TempOptInfo
  tcg: Expand TCGTemp.val to 64-bits
  ...

Signed-off-by: Peter Maydell <[email protected]>

Merge remote-tracking branch 'remotes/mcayland/tags/qemu-macppc-20210113' into staging

qemu-macppc updates

# gpg: Signature made Wed 13 Jan 2021 13:02:20 GMT
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Mark Cave-Ayland <[email protected]>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-macppc-20210113:
  macio: don't set user_creatable to false
  macio: wire macio GPIOs to OpenPIC using sysbus IRQs
  macio: move OpenPIC inside macio-newworld device
  mac_newworld: delay wiring of PCI IRQs in New World machine
  macio: move heathrow PIC inside macio-oldworld device
  mac_oldworld: move initialisation of grackle before heathrow
  mac_oldworld: remove duplicate bus check for PPC_INPUT(env)

Signed-off-by: Peter Maydell <[email protected]>

decodetree: Open files with encoding='utf-8'

When decodetree.py was added in commit 568ae7efae7, QEMU was
using Python 2 which happily reads UTF-8 files in text mode.
Python 3 requires either UTF-8 locale or an explicit encoding
passed to open(). Now that Python 3 is required, explicit
UTF-8 encoding for decodetree source files.

To avoid further problems with the user locale, also explicit
UTF-8 encoding for the generated C files.

Explicit both input/output are plain text by using the 't' mode.

This fixes:

  $ /usr/bin/python3 scripts/decodetree.py test.decode
  Traceback (most recent call last):
    File "scripts/decodetree.py", line 1397, in <module>
      main()
    File "scripts/decodetree.py", line 1308, in main
      parse_file(f, toppat)
    File "scripts/decodetree.py", line 994, in parse_file
      for line in f:
    File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode
      return codecs.ascii_decode(input, self.errors)[0]
  UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position 80:
  ordinal not in range(128)

Reported-by: Peter Maydell <[email protected]>
Suggested-by: Yonggang Luo <[email protected]>
Reviewed-by: Eduardo Habkost <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210110000240[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/aarch64: Use tcg_constant_vec with tcg vec expanders

Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to
"t1 = -v2, t2 = c - v2".  This avoids a serial dependency
between t1 and t2.

Signed-off-by: Richard Henderson <[email protected]>

tcg/ppc: Use tcg_constant_vec with tcg vec expanders

Improve expand_vec_shi to use sign-extraction for MO_32.
This allows a single VSPLTISB instruction to load all of
the valid shift constants.

Signed-off-by: Richard Henderson <[email protected]>

tcg: Remove tcg_gen_dup{8,16,32,64}i_vec

These interfaces have been replaced by tcg_gen_dupi_vec
and tcg_constant_vec.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/i386: Use tcg_constant_vec with tcg vec expanders

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Add tcg_reg_alloc_dup2

There are several ways we can expand a vector dup of a 64-bit
element on a 32-bit host.

Signed-off-by: Richard Henderson <[email protected]>

tcg: Remove movi and dupi opcodes

These are now completely covered by mov from a
TYPE_CONST temporary.

Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Aleksandar Markovic <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/tci: Add special tci_movi_{i32,i64} opcodes

The normal movi opcodes are going away.  We need something
for TCI to use internally.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders

Signed-off-by: Richard Henderson <[email protected]>

tcg: Use tcg_constant_{i32,i64} with tcg plugins

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Use tcg_constant_{i32,i64} with tcg int expanders

Signed-off-by: Richard Henderson <[email protected]>

tcg: Use tcg_constant_i32 with icount expander

We must do this before we adjust tcg_out_movi_i32, lest the
under-the-hood poking that we do for icount be broken.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Convert tcg_gen_dupi_vec to TCG_CONST

Because we now store uint64_t in TCGTemp, we can now always
store the full 64-bit duplicate immediate.  So remove the
difference between 32- and 64-bit hosts.

Signed-off-by: Richard Henderson <[email protected]>

tcg/optimize: Use tcg_constant_internal with constant folding

Signed-off-by: Richard Henderson <[email protected]>

tcg/optimize: Adjust TempOptInfo allocation

Do not allocate a large block for indexing.  Instead, allocate
for each temporary as they are seen.

In general, this will use less memory, if we consider that most
TBs do not touch every target register.  This also allows us to
allocate TempOptInfo for new temps created during optimization.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/optimize: Improve find_better_copy

Prefer TEMP_CONST over anything else.

Signed-off-by: Richard Henderson <[email protected]>

tcg: Introduce TYPE_CONST temporaries

These will hold a single constant for the duration of the TB.
They are hashed, so that each value has one temp across the TB.

Not used yet, this is all infrastructure.

Signed-off-by: Richard Henderson <[email protected]>

tcg: Expand TempOptInfo to 64-bits

This propagates the extended value of TCGTemp.val that we did before.
In addition, it will be required for vector constants.

Signed-off-by: Richard Henderson <[email protected]>

tcg: Rename struct tcg_temp_info to TempOptInfo

Fix this name vs our coding style.

Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Expand TCGTemp.val to 64-bits

This will reduce the differences between 32-bit and 64-bit hosts,
allowing full 64-bit constants to be created with the same interface.

Signed-off-by: Richard Henderson <[email protected]>

tcg: Add temp_readonly

In most, but not all, places that we check for TEMP_FIXED,
we are really testing that we do not modify the temporary.

Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Consolidate 3 bits into enum TCGTempKind

The temp_fixed, temp_global, temp_local bits are all related.
Combine them into a single enumeration.

Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Increase tcg_out_dupi_vec immediate to int64_t

While we don't store more than tcg_target_long in TCGTemp,
we shouldn't be limited to that for code generation.  We will
be able to use this for INDEX_op_dup2_vec with 2 constants.

Also pass along the minimal vece that may be said to apply
to the constant.  This allows some simplification in the
various backends.

Signed-off-by: Richard Henderson <[email protected]>

tcg: Use tcg_out_dupi_vec from temp_load

Having dupi pass though movi is confusing and arguably wrong.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

Merge remote-tracking branch 'remotes/armbru/tags/pull-yank-2021-01-13' into staging

Yank patches patches for 2021-01-13

# gpg: Signature made Wed 13 Jan 2021 09:25:46 GMT
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Markus Armbruster <[email protected]>" [full]
# gpg:                 aka "Markus Armbruster <[email protected]>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-yank-2021-01-13:
  tests/test-char.c: Wait for the chardev to connect in char_socket_client_dupid_test
  io: Document qmp oob suitability of qio_channel_shutdown and io_shutdown
  io/channel-tls.c: make qio_channel_tls_shutdown thread-safe
  migration: Add yank feature
  chardev/char-socket.c: Add yank feature
  block/nbd.c: Add yank feature
  Introduce yank feature

Signed-off-by: Peter Maydell <[email protected]>

macio: don't set user_creatable to false

Now that all of the object property links to the heathrow PIC and OpenPIC have
been removed from the macio devices, it is safe to allow the macio-oldworld
and macio-neworld devices to be marked as user_creatable.

Signed-off-by: Mark Cave-Ayland <[email protected]>
Message-Id: <20201229175619[email protected]>
Signed-off-by: Mark Cave-Ayland <[email protected]>

macio: wire macio GPIOs to OpenPIC using sysbus IRQs

This both allows the wiring to be done as Ben suggested in his original comment in
gpio.c and also enables the OpenPIC object property link to be removed.

Signed-off-by: Mark Cave-Ayland <[email protected]>
Message-Id: <20201229175619[email protected]>
Signed-off-by: Mark Cave-Ayland <[email protected]>

macio: move OpenPIC inside macio-newworld device

The OpenPIC device is located within the macio device on real hardware so make it
a child of the macio-newworld device. This also removes the need for setting and
checking a separate PIC object property link on the macio-newworld device which
currently causes the automated QOM introspection tests to fail.

Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: David Gibson <[email protected]>
Message-Id: <20201229175619[email protected]>
Signed-off-by: Mark Cave-Ayland <[email protected]>

mac_newworld: delay wiring of PCI IRQs in New World machine

In order to move the OpenPIC device to the macio device, the PCI bus needs to be
initialised before the macio device and also before wiring the OpenPIC IRQs.

Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: David Gibson <[email protected]>
Message-Id: <20201229175619[email protected]>
Signed-off-by: Mark Cave-Ayland <[email protected]>

macio: move heathrow PIC inside macio-oldworld device

The heathrow PIC is located within the macio device on real hardware so make it
a child of the macio-oldworld device. This also removes the need for setting and
checking a separate PIC object property link on the macio-oldworld device which
currently causes the automated QOM introspection tests to fail.

Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: David Gibson <[email protected]>
Message-Id: <20201229175619[email protected]>
Signed-off-by: Mark Cave-Ayland <[email protected]>

mac_oldworld: move initialisation of grackle before heathrow

In order to move the heathrow PIC to the macio device, the PCI bus needs to be
initialised before the macio device and also before wiring the PIC IRQs.

Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: David Gibson <[email protected]>
Message-Id: <20201229175619[email protected]>
Signed-off-by: Mark Cave-Ayland <[email protected]>

mac_oldworld: remove duplicate bus check for PPC_INPUT(env)

This condition will have already been caught when wiring the heathrow PIC
IRQs to the CPU.

Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: David Gibson <[email protected]>
Message-Id: <20201229175619[email protected]>
Signed-off-by: Mark Cave-Ayland <[email protected]>

tests/test-char.c: Wait for the chardev to connect in char_socket_client_dupid_test

A connecting chardev object has an additional reference by the connecting
thread, so if the chardev is still connecting by the end of the test,
then the chardev object won't be freed. This in turn means that the yank
instance won't be unregistered and when running the next test-case
yank_register_instance will abort, because the yank instance is
already/still registered.

Signed-off-by: Lukas Straub <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Message-Id: <1445e97a5800e3f2ba024ad52b500a0315701632.1609167865[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

io: Document qmp oob suitability of qio_channel_shutdown and io_shutdown

Migration and yank code assume that qio_channel_shutdown is thread
-safe and can be called from qmp oob handler. Document this after
checking the code.

Signed-off-by: Lukas Straub <[email protected]>
Acked-by: Stefan Hajnoczi <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Message-Id: <32b8c27e256da043f0f00db05bd7ab8fbc506070.1609167865[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

io/channel-tls.c: make qio_channel_tls_shutdown thread-safe

Make qio_channel_tls_shutdown thread-safe by using atomics when
accessing tioc->shutdown.

Signed-off-by: Lukas Straub <[email protected]>
Acked-by: Stefan Hajnoczi <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Message-Id: <5bd8733f583f3558b32250fd0eb576b7aa756485.1609167865[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

migration: Add yank feature

Register yank functions on sockets to shut them down.

Signed-off-by: Lukas Straub <[email protected]>
Acked-by: Stefan Hajnoczi <[email protected]>
Acked-by: Dr. David Alan Gilbert <[email protected]>
Message-Id: <484c6a14cc2506bebedd5a237259b91363ff8f88.1609167865[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

chardev/char-socket.c: Add yank feature

Register a yank function to shutdown the socket on yank.

Signed-off-by: Lukas Straub <[email protected]>
Acked-by: Stefan Hajnoczi <[email protected]>
Message-Id: <1f4eeed1d066c6cbb8d05ffa9585f6e87b34aac6.1609167865[email protected]>
Acked-by: Marc-André Lureau <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

block/nbd.c: Add yank feature

Register a yank function which shuts down the socket and sets
s->state = NBD_CLIENT_QUIT. This is the same behaviour as if an
error occured.

Signed-off-by: Lukas Straub <[email protected]>
Acked-by: Stefan Hajnoczi <[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Message-Id: <b73eb07db6d1fcd00667beb13ae6117260f002c3.1609167865[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

Introduce yank feature

The yank feature allows to recover from hanging qemu by "yanking"
at various parts. Other qemu systems can register themselves and
multiple yank functions. Then all yank functions for selected
instances can be called by the 'yank' out-of-band qmp command.
Available instances can be queried by a 'query-yank' oob command.

Signed-off-by: Lukas Straub <[email protected]>
Acked-by: Stefan Hajnoczi <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Message-Id: <69934ceacfd33a7dfe53db145ecc630ad39ee47c.1609167865[email protected]>
Acked-by: Marc-André Lureau <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

* UI configury cleanups and Meson conversion
* scripts/gdb improvements
* WHPX cleanups and fixes
* cirrus win32 CI improvements
* meson gnutls workaround

# gpg: Signature made Tue 12 Jan 2021 16:05:19 GMT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Paolo Bonzini <[email protected]>" [full]
# gpg:                 aka "Paolo Bonzini <[email protected]>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini-gitlab/tags/for-upstream:
  target/i386: Use X86Seg enum for segment registers
  configure: quote command line arguments in config.status
  configure: move Cocoa incompatibility checks to Meson
  configure: move GTK+ detection to Meson
  configure: move X11 detection to Meson
  gtk: remove CONFIG_GTK_GL
  cocoa: do not enable coreaudio automatically
  virtio-scsi: trace events
  meson: Propagate gnutls dependency
  Docs/RCU: Correct sample code of qatomic_rcu_set
  scripts/gdb: implement 'qemu bt'
  scripts/gdb: fix 'qemu coroutine' when users selects a non topmost stack frame
  meson: fix Cocoa option in summary
  whpx: move whpx_lapic_state from header to c file
  maintainers: Add me as Windows Hosted Continuous Integration maintainer
  cirrus/msys2: Cache msys2 mingw in a better way.
  cirrus/msys2: Exit powershell with $LastExitCode
  whpx: move internal definitions to whpx-internal.h
  whpx: rename whp-dispatch to whpx-internal.h
  meson: do not use CONFIG_VIRTFS

Signed-off-by: Peter Maydell <[email protected]>

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210112-1' into staging

target-arm queue:
 * arm: Support emulation of ARMv8.4-TTST extension
 * arm: Update cpu.h ID register field definitions
 * arm: Fix breakage of XScale instruction emulation
 * hw/net/lan9118: Fix RX Status FIFO PEEK value
 * npcm7xx: Add ADC and PWM emulation
 * ui/cocoa: Make "open docs" help menu entry work again when binary
   is run from the build tree
 * ui/cocoa: Fix openFile: deprecation on Big Sur
 * docs: Add qemu-storage-daemon(1) manpage to meson.build

# gpg: Signature made Tue 12 Jan 2021 21:22:15 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [ultimate]
# gpg:                 aka "Peter Maydell <[email protected]>" [ultimate]
# gpg:                 aka "Peter Maydell <[email protected]>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210112-1:
  ui/cocoa: Fix openFile: deprecation on Big Sur
  hw/*: Use type casting for SysBusDevice in NPCM7XX
  hw/misc: Add QTest for NPCM7XX PWM Module
  hw/misc: Add a PWM module for NPCM7XX
  hw/adc: Add an ADC module for NPCM7XX
  hw/timer: Refactor NPCM7XX Timer to use CLK clock
  hw/misc: Add clock converter in NPCM7XX CLK module
  hw/net/lan9118: Add symbolic constants for register offsets
  hw/net/lan9118: Fix RX Status FIFO PEEK value
  target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
  docs: Add qemu-storage-daemon(1) manpage to meson.build
  ui/cocoa: Update path to docs in build tree
  target/arm: add aarch32 ID register fields to cpu.h
  target/arm: add aarch64 ID register fields to cpu.h
  target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
  target/arm: make ARMCPU.ctr 64-bit
  target/arm: make ARMCPU.clidr 64-bit
  target/arm: fix typo in cpu.h ID_AA64PFR1 field name
  target/arm: enable Small Translation tables in max CPU
  target/arm: ARMv8.4-TTST extension

Signed-off-by: Peter Maydell <[email protected]>

ui/cocoa: Fix openFile: deprecation on Big Sur

ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
      [-Wdeprecated-declarations]
        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
                                           ^
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
      'openFile:' has been explicitly marked deprecated here
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
^

Signed-off-by: Roman Bolshakov <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: 20210102150718[email protected]
Signed-off-by: Peter Maydell <[email protected]>

hw/*: Use type casting for SysBusDevice in NPCM7XX

A device shouldn't access its parent object which is QOM internal.
Instead it should use type cast for this purporse. This patch fixes this
issue for all NPCM7XX Devices.

Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: 20210108190945[email protected]
Signed-off-by: Peter Maydell <[email protected]>

hw/misc: Add QTest for NPCM7XX PWM Module

We add a qtest for the PWM in the previous patch. It proves it works as
expected.

Reviewed-by: Havard Skinnemoen <[email protected]>
Reviewed-by: Tyrone Ting <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: 20210108190945[email protected]
Signed-off-by: Peter Maydell <[email protected]>

hw/misc: Add a PWM module for NPCM7XX

The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
two outputs: frequency and duty_cycle. Both are computed using inputs
from software side.

This module does not model detail pulse signals since it is expensive.
It also does not model interrupts and watchdogs that are dependant on
the detail models. The interfaces for these are left in the module so
that anyone in need for these functionalities can implement on their
own.

The user can read the duty cycle and frequency using qom-get command.

Reviewed-by: Havard Skinnemoen <[email protected]>
Reviewed-by: Tyrone Ting <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: 20210108190945[email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>

hw/adc: Add an ADC module for NPCM7XX

The ADC is part of NPCM7XX Module. Its behavior is controled by the
ADC_CON register. It converts one of the eight analog inputs into a
digital input and stores it in the ADC_DATA register when enabled.

Users can alter input value by using qom-set QMP command.

Reviewed-by: Havard Skinnemoen <[email protected]>
Reviewed-by: Tyrone Ting <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: 20210108190945[email protected]
[PMM: Added missing hw/adc/trace.h file]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>

hw/timer: Refactor NPCM7XX Timer to use CLK clock

This patch makes NPCM7XX Timer to use a the timer clock generated by the
CLK module instead of the magic number TIMER_REF_HZ.

Reviewed-by: Havard Skinnemoen <[email protected]>
Reviewed-by: Tyrone Ting <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: 20210108190945[email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>

hw/misc: Add clock converter in NPCM7XX CLK module

This patch allows NPCM7XX CLK module to compute clocks that are used by
other NPCM7XX modules.

Add a new struct NPCM7xxClockConverterState which represents a
single converter.  Each clock converter in CLK module represents one
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
takes one or more input clocks and converts them into one output clock.
They form a clock hierarchy in the CLK module and are responsible for
outputing clocks for various other modules in an NPCM7XX SoC.

Each converter has a function pointer called "convert" which represents
the unique logic for that converter.

The clock contains two initialization information: ConverterInitInfo and
ConverterConnectionInfo. They represent the vertices and edges in the
clock diagram respectively.

Reviewed-by: Havard Skinnemoen <[email protected]>
Reviewed-by: Tyrone Ting <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: 20210108190945[email protected]
Signed-off-by: Peter Maydell <[email protected]>

hw/net/lan9118: Add symbolic constants for register offsets

The lan9118 code mostly uses symbolic constants for register offsets;
the exceptions are those which the datasheet doesn't give an official
symbolic name to.

Add some names for the registers which don't already have them, based
on the longer names they are given in the memory map.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: 20210108180401[email protected]