]> Git Repo - qemu.git/log
qemu.git
5 years agoaudio: paaudio: fix connection and stream name
Kővágó, Zoltán [Tue, 10 Sep 2019 23:26:19 +0000 (01:26 +0200)]
audio: paaudio: fix connection and stream name

Connection name was previously erroneously set to the server socket
path, while connection names were simply "qemu".  After this patch, the
connection name will be the vm name (falling back to "qemu" if not
specified), while stream names will be the audiodev's id.

Signed-off-by: Kővágó, Zoltán <[email protected]>
Message-id: 3d139426031a400a68d440608ba5e43f0e116cd8.1568157545[email protected]
Signed-off-by: Gerd Hoffmann <[email protected]>
5 years agoaudio: fix parameter dereference before NULL check
Kővágó, Zoltán [Tue, 10 Sep 2019 23:26:18 +0000 (01:26 +0200)]
audio: fix parameter dereference before NULL check

This should fix Coverity issues CID 1405305 and 1405301.

Signed-off-by: Kővágó, Zoltán <[email protected]>
Message-id: 0eadcc88b8421bb86ce2d68ac70517f920c3ad6c.1568157545[email protected]
Signed-off-by: Gerd Hoffmann <[email protected]>
5 years agodirty-bitmaps: remove deprecated autoload parameter
John Snow [Wed, 2 Oct 2019 23:24:11 +0000 (19:24 -0400)]
dirty-bitmaps: remove deprecated autoload parameter

This parameter has been deprecated since 2.12.0 and is eligible for
removal. Remove this parameter as it is actually completely ignored;
let's not give false hope.

Signed-off-by: John Snow <[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Message-id: 20191002232411[email protected]

5 years agoMAINTAINERS: Add Vladimir as a reviewer for bitmaps
John Snow [Sat, 5 Oct 2019 19:44:48 +0000 (15:44 -0400)]
MAINTAINERS: Add Vladimir as a reviewer for bitmaps

I already try to make sure all bitmaps patches have been reviewed by both
Red Hat and Virtuozzo anyway, so this formalizes the arrangement.

Fam meanwhile is no longer as active, so I am removing him as a co-maintainer
simply to reflect the current practice.

Signed-off-by: John Snow <[email protected]>
Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Message-id: 20191005194448[email protected]

5 years agoqcow2-bitmap: move bitmap reopen-rw code to qcow2_reopen_commit
Vladimir Sementsov-Ogievskiy [Fri, 27 Sep 2019 12:23:55 +0000 (15:23 +0300)]
qcow2-bitmap: move bitmap reopen-rw code to qcow2_reopen_commit

The only reason I can imagine for this strange code at the very-end of
bdrv_reopen_commit is the fact that bs->read_only updated after
calling drv->bdrv_reopen_commit in bdrv_reopen_commit. And in the same
time, prior to previous commit, qcow2_reopen_bitmaps_rw did a wrong
check for being writable, when actually it only need writable file
child not self.

So, as it's fixed, let's move things to correct place.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Acked-by: Max Reitz <[email protected]>
Message-id: 20190927122355[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock/qcow2-bitmap: fix and improve qcow2_reopen_bitmaps_rw
Vladimir Sementsov-Ogievskiy [Fri, 27 Sep 2019 12:23:54 +0000 (15:23 +0300)]
block/qcow2-bitmap: fix and improve qcow2_reopen_bitmaps_rw

- Correct check for write access to file child, and in correct place
  (only if we want to write).
- Support reopen rw -> rw (which will be used in following commit),
  for example, !bdrv_dirty_bitmap_readonly() is not a corruption if
  bitmap is marked IN_USE in the image.
- Consider unexpected bitmap as a corruption and check other
  combinations of in-image and in-RAM bitmaps.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Message-id: 20190927122355[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoiotests: add test 260 to check bitmap life after snapshot + commit
Vladimir Sementsov-Ogievskiy [Fri, 27 Sep 2019 12:23:53 +0000 (15:23 +0300)]
iotests: add test 260 to check bitmap life after snapshot + commit

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Message-id: 20190927122355[email protected]
[Maintainer edit: removed 260 from auto group per Peter Maydell. --js]
Signed-off-by: John Snow <[email protected]>
5 years agoblock/qcow2-bitmap: do not remove bitmaps on reopen-ro
Vladimir Sementsov-Ogievskiy [Fri, 27 Sep 2019 12:23:52 +0000 (15:23 +0300)]
block/qcow2-bitmap: do not remove bitmaps on reopen-ro

qcow2_reopen_bitmaps_ro wants to store bitmaps and then mark them all
readonly. But the latter don't work, as
qcow2_store_persistent_dirty_bitmaps removes bitmaps after storing.
It's OK for inactivation but bad idea for reopen-ro. And this leads to
the following bug:

Assume we have persistent bitmap 'bitmap0'.
Create external snapshot
  bitmap0 is stored and therefore removed
Commit snapshot
  now we have no bitmaps
Do some writes from guest (*)
  they are not marked in bitmap
Shutdown
Start
  bitmap0 is loaded as valid, but it is actually broken! It misses
  writes (*)
Incremental backup
  it will be inconsistent

So, let's stop removing bitmaps on reopen-ro. But don't rejoice:
reopening bitmaps to rw is broken too, so the whole scenario will not
work after this patch and we can't enable corresponding test cases in
260 iotests still. Reopening bitmaps rw will be fixed in the following
patches.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20190927122355[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock/qcow2-bitmap: drop qcow2_reopen_bitmaps_rw_hint()
Vladimir Sementsov-Ogievskiy [Fri, 27 Sep 2019 12:23:51 +0000 (15:23 +0300)]
block/qcow2-bitmap: drop qcow2_reopen_bitmaps_rw_hint()

The function is unused, drop it.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20190927122355[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock/qcow2-bitmap: get rid of bdrv_has_changed_persistent_bitmaps
Vladimir Sementsov-Ogievskiy [Fri, 27 Sep 2019 12:23:50 +0000 (15:23 +0300)]
block/qcow2-bitmap: get rid of bdrv_has_changed_persistent_bitmaps

Firstly, no reason to optimize failure path. Then, function name is
ambiguous: it checks for readonly and similar things, but someone may
think that it will ignore normal bitmaps which was just unchanged, and
this is in bad relation with the fact that we should drop IN_USE flag
for unchanged bitmaps in the image.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20190927122355[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoiotests: add test-case to 165 to test reopening qcow2 bitmaps to RW
Vladimir Sementsov-Ogievskiy [Fri, 27 Sep 2019 12:23:49 +0000 (15:23 +0300)]
iotests: add test-case to 165 to test reopening qcow2 bitmaps to RW

Reopening bitmaps to RW was broken prior to previous commit. Check that
it works now.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Message-id: 20190927122355[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock: reverse order for reopen commits
Vladimir Sementsov-Ogievskiy [Fri, 27 Sep 2019 12:23:48 +0000 (15:23 +0300)]
block: reverse order for reopen commits

It's needed to fix reopening qcow2 with bitmaps to RW. Currently it
can't work, as qcow2 needs write access to file child, to mark bitmaps
in-image with IN_USE flag. But usually children goes after parents in
reopen queue and file child is still RO on qcow2 reopen commit. Reverse
reopen order to fix it.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Acked-by: Max Reitz <[email protected]>
Acked-by: John Snow <[email protected]>
Message-id: 20190927122355[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock: switch reopen queue from QSIMPLEQ to QTAILQ
Vladimir Sementsov-Ogievskiy [Fri, 27 Sep 2019 12:23:47 +0000 (15:23 +0300)]
block: switch reopen queue from QSIMPLEQ to QTAILQ

We'll need reverse-foreach in the following commit, QTAILQ support it,
so move to QTAILQ.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Max Reitz <[email protected]>
Message-id: 20190927122355[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock/dirty-bitmap: refactor bdrv_dirty_bitmap_next
Vladimir Sementsov-Ogievskiy [Mon, 16 Sep 2019 14:19:11 +0000 (17:19 +0300)]
block/dirty-bitmap: refactor bdrv_dirty_bitmap_next

bdrv_dirty_bitmap_next is always used in same pattern. So, split it
into _next and _first, instead of combining two functions into one and
add FOR_EACH_DIRTY_BITMAP macro.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20190916141911[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock/dirty-bitmap: drop BdrvDirtyBitmap.mutex
Vladimir Sementsov-Ogievskiy [Mon, 16 Sep 2019 14:19:10 +0000 (17:19 +0300)]
block/dirty-bitmap: drop BdrvDirtyBitmap.mutex

mutex field is just a pointer to bs->dirty_bitmap_mutex, so no needs
to store it in BdrvDirtyBitmap when we have bs pointer in it (since
previous patch).

Drop mutex field. Constantly use bdrv_dirty_bitmaps_lock/unlock in
block/dirty-bitmap.c to make it more obvious that it's not per-bitmap
lock. Still, for simplicity, leave bdrv_dirty_bitmap_lock/unlock
functions as an external API.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20190916141911[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock/dirty-bitmap: add bs link
Vladimir Sementsov-Ogievskiy [Mon, 16 Sep 2019 14:19:09 +0000 (17:19 +0300)]
block/dirty-bitmap: add bs link

Add bs field to BdrvDirtyBitmap structure. Drop BlockDriverState
parameter from bitmap APIs where possible.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20190916141911[email protected]
[Rebased on top of block-copy. --js]
Signed-off-by: John Snow <[email protected]>
5 years agoblock/dirty-bitmap: drop meta
Vladimir Sementsov-Ogievskiy [Mon, 16 Sep 2019 14:19:08 +0000 (17:19 +0300)]
block/dirty-bitmap: drop meta

Drop meta bitmaps, as they are unused.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20190916141911[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock/qcow2: proper locking on bitmap add/remove paths
Vladimir Sementsov-Ogievskiy [Fri, 20 Sep 2019 08:25:43 +0000 (11:25 +0300)]
block/qcow2: proper locking on bitmap add/remove paths

qmp_block_dirty_bitmap_add and do_block_dirty_bitmap_remove do acquire
aio context since 0a6c86d024c52b. But this is not enough: we also must
lock qcow2 mutex when access in-image metadata. Especially it concerns
freeing qcow2 clusters.

To achieve this, move qcow2_can_store_new_dirty_bitmap and
qcow2_remove_persistent_dirty_bitmap to coroutine context.

Since we work in coroutines in correct aio context, we don't need
context acquiring in blockdev.c anymore, drop it.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20190920082543[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock/dirty-bitmap: return int from bdrv_remove_persistent_dirty_bitmap
Vladimir Sementsov-Ogievskiy [Fri, 20 Sep 2019 08:25:42 +0000 (11:25 +0300)]
block/dirty-bitmap: return int from bdrv_remove_persistent_dirty_bitmap

It's more comfortable to not deal with local_err.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20190920082543[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoblock: move bdrv_can_store_new_dirty_bitmap to block/dirty-bitmap.c
Vladimir Sementsov-Ogievskiy [Fri, 20 Sep 2019 08:25:41 +0000 (11:25 +0300)]
block: move bdrv_can_store_new_dirty_bitmap to block/dirty-bitmap.c

block/dirty-bitmap.c seems to be more appropriate for it and
bdrv_remove_persistent_dirty_bitmap already in it.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20190920082543[email protected]
Signed-off-by: John Snow <[email protected]>
5 years agoutil/hbitmap: strict hbitmap_reset
Vladimir Sementsov-Ogievskiy [Tue, 6 Aug 2019 15:26:11 +0000 (18:26 +0300)]
util/hbitmap: strict hbitmap_reset

hbitmap_reset has an unobvious property: it rounds requested region up.
It may provoke bugs, like in recently fixed write-blocking mode of
mirror: user calls reset on unaligned region, not keeping in mind that
there are possible unrelated dirty bytes, covered by rounded-up region
and information of this unrelated "dirtiness" will be lost.

Make hbitmap_reset strict: assert that arguments are aligned, allowing
only one exception when @start + @count == hb->orig_size. It's needed
to comfort users of hbitmap_next_dirty_area, which cares about
hb->orig_size.

Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Max Reitz <[email protected]>
Message-Id: <20190806152611[email protected]>
[Maintainer edit: Max's suggestions from on-list. --js]
[Maintainer edit: Eric's suggestion for aligned macro. --js]
Signed-off-by: John Snow <[email protected]>
5 years agoMerge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into...
Peter Maydell [Thu, 17 Oct 2019 17:16:55 +0000 (18:16 +0100)]
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

x86 and machine queue, 2019-10-15

Features:
* Snowridge-v2 (no MPX) CPU model (Xiaoyao Li)

Bug fixes:
* cpu-plug-test: fix device_add for pc/q35 machines (Igor Mammedov)
* Fix legacy guest with xsave panic on older Linux kernel (Bingsong Si)
* Omit all-zeroes entries from KVM CPUID table (Eduardo Habkost)

Cleanups:
* Convert reset handlers to DeviceReset (Philippe Mathieu-Daudé)
* MachineClass::auto_enable_numa field (Tao Xu)
* target/i386/cpu.h cleanups (Tao Xu)
* memory_device_get_free_addr() cleanups (Wei Yang)

# gpg: Signature made Tue 15 Oct 2019 22:35:43 BST
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Eduardo Habkost <[email protected]>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request:
  target/i386: Add Snowridge-v2 (no MPX) CPU model
  i386: Omit all-zeroes entries from KVM CPUID table
  i386: Fix legacy guest with xsave panic on host kvm without update cpuid.
  target/i386: drop the duplicated definition of cpuid AVX512_VBMI macro
  target/i386: clean up comments over 80 chars per line
  memory-device: break the loop if tmp exceed the hinted range
  memory-device: not necessary to use goto for the last check
  hw/misc/vmcoreinfo: Add comment about reset handler
  hw/input/lm832x: Convert reset handler to DeviceReset
  hw/isa/vt82c686: Convert reset handler to DeviceReset
  hw/ide/via82c: Convert reset handler to DeviceReset
  hw/ide/sii3112: Convert reset handler to DeviceReset
  hw/ide/piix: Convert reset handler to DeviceReset
  hw/isa/piix4: Convert reset handler to DeviceReset
  hw/acpi/piix4: Convert reset handler to DeviceReset
  numa: Introduce MachineClass::auto_enable_numa for implicit NUMA node
  tests: cpu-plug-test: fix device_add for pc/q35 machines
  tests: add qtest_qmp_device_add_qdict() helper

Signed-off-by: Peter Maydell <[email protected]>
5 years agoMerge remote-tracking branch 'remotes/rth/tags/pull-tcg-20191013' into staging
Peter Maydell [Thu, 17 Oct 2019 15:48:56 +0000 (16:48 +0100)]
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20191013' into staging

Host vector support for tcg/ppc.
Fix thread=single cpu kicking.

# gpg: Signature made Mon 14 Oct 2019 15:11:55 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20191013: (23 commits)
  cpus: kick all vCPUs when running thread=single
  tcg/ppc: Update vector support for v3.00 dup/dupi
  tcg/ppc: Update vector support for v3.00 load/store
  tcg/ppc: Update vector support for v3.00 Altivec
  tcg/ppc: Update vector support for v2.07 FP
  tcg/ppc: Update vector support for v2.07 VSX
  tcg/ppc: Update vector support for v2.07 Altivec
  tcg/ppc: Update vector support for VSX
  tcg/ppc: Enable Altivec detection
  tcg/ppc: Support vector dup2
  tcg/ppc: Support vector multiply
  tcg/ppc: Support vector shift by immediate
  tcg/ppc: Add support for vector saturated add/subtract
  tcg/ppc: Add support for vector add/subtract
  tcg/ppc: Add support for vector maximum/minimum
  tcg/ppc: Add support for load/store/logic/comparison
  tcg/ppc: Enable tcg backend vector compilation
  tcg/ppc: Replace HAVE_ISEL macro with a variable
  tcg/ppc: Replace HAVE_ISA_2_06
  tcg/ppc: Create TCGPowerISA and have_isa
  ...

Signed-off-by: Peter Maydell <[email protected]>
5 years agoMerge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
Peter Maydell [Thu, 17 Oct 2019 14:30:44 +0000 (15:30 +0100)]
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging

virtio, vhost, acpi: features, fixes, tests

ARM ACPI memory hotplug support +
tests for new arm/virt ACPI tables.

Virtio fs support (no migration).
A vhost-user reconnect bugfix.

Signed-off-by: Michael S. Tsirkin <[email protected]>
# gpg: Signature made Tue 15 Oct 2019 22:02:19 BST
# gpg:                using RSA key 281F0DB8D28D5469
# gpg: Good signature from "Michael S. Tsirkin <[email protected]>" [full]
# gpg:                 aka "Michael S. Tsirkin <[email protected]>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream:
  virtio: add vhost-user-fs-pci device
  virtio: add vhost-user-fs base device
  virtio: Add virtio_fs linux headers
  tests/acpi: add expected tables for arm/virt
  tests: document how to update acpi tables
  tests: Add bios tests to arm/virt
  tests: allow empty expected files
  tests/acpi: add empty files
  tests: Update ACPI tables list for upcoming arm/virt tests
  docs/specs: Add ACPI GED documentation
  hw/arm: Use GED for system_powerdown event
  hw/arm: Factor out powerdown notifier from GPIO
  hw/arm/virt-acpi-build: Add PC-DIMM in SRAT
  hw/arm/virt: Enable device memory cold/hot plug with ACPI boot
  hw/arm/virt: Add memory hotplug framework
  hw/acpi: Add ACPI Generic Event Device Support
  hw/acpi: Do not create memory hotplug method when handler is not defined
  hw/acpi: Make ACPI IO address space configurable
  vhost-user: save features if the char dev is closed

Signed-off-by: Peter Maydell <[email protected]>
5 years agosphinx: Use separate doctree directories for different builders
Eduardo Habkost [Mon, 14 Oct 2019 15:01:33 +0000 (12:01 -0300)]
sphinx: Use separate doctree directories for different builders

sphinx-build is buggy when multiple processes are using the same
doctree directory in parallel.  See the 3-year-old Sphinx bug
report at: https://github.com/sphinx-doc/sphinx/issues/2946

Instead of avoiding parallel builds or adding some kind of
locking, I'm using the simplest solution: just using a different
doctree cache for each builder.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 20191014150133[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agotarget/i386: Add Snowridge-v2 (no MPX) CPU model
Xiaoyao Li [Sat, 12 Oct 2019 02:47:48 +0000 (10:47 +0800)]
target/i386: Add Snowridge-v2 (no MPX) CPU model

Add new version of Snowridge CPU model that removes MPX feature.

MPX support is being phased out by Intel. GCC has dropped it, Linux kernel
and KVM are also going to do that in the future.

Signed-off-by: Xiaoyao Li <[email protected]>
Message-Id: <20191012024748[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agoi386: Omit all-zeroes entries from KVM CPUID table
Eduardo Habkost [Thu, 22 Aug 2019 22:52:10 +0000 (19:52 -0300)]
i386: Omit all-zeroes entries from KVM CPUID table

KVM has a 80-entry limit at KVM_SET_CPUID2.  With the
introduction of CPUID[0x1F], it is now possible to hit this limit
with unusual CPU configurations, e.g.:

  $ ./x86_64-softmmu/qemu-system-x86_64 \
    -smp 1,dies=2,maxcpus=2 \
    -cpu EPYC,check=off,enforce=off \
    -machine accel=kvm
  qemu-system-x86_64: kvm_init_vcpu failed: Argument list too long

This happens because QEMU adds a lot of all-zeroes CPUID entries
for unused CPUID leaves.  In the example above, we end up
creating 48 all-zeroes CPUID entries.

KVM already returns all-zeroes when emulating the CPUID
instruction if an entry is missing, so the all-zeroes entries are
redundant.  Skip those entries.  This reduces the CPUID table
size by half while keeping CPUID output unchanged.

Reported-by: Yumei Huang <[email protected]>
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1741508
Signed-off-by: Eduardo Habkost <[email protected]>
Message-Id: <20190822225210[email protected]>
Acked-by: Paolo Bonzini <[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agoi386: Fix legacy guest with xsave panic on host kvm without update cpuid.
Bingsong Si [Thu, 22 Aug 2019 04:29:01 +0000 (12:29 +0800)]
i386: Fix legacy guest with xsave panic on host kvm without update cpuid.

without kvm commit 412a3c41, CPUID(EAX=0xd,ECX=0).EBX always equal to 0 even
through guest update xcr0, this will crash legacy guest(e.g., CentOS 6).
Below is the call trace on the guest.

[    0.000000] kernel BUG at mm/bootmem.c:469!
[    0.000000] invalid opcode: 0000 [#1] SMP
[    0.000000] last sysfs file:
[    0.000000] CPU 0
[    0.000000] Modules linked in:
[    0.000000]
[    0.000000] Pid: 0, comm: swapper Tainted: G           --------------- H  2.6.32-279#2 Red Hat KVM
[    0.000000] RIP: 0010:[<ffffffff81c4edc4>]  [<ffffffff81c4edc4>] alloc_bootmem_core+0x7b/0x29e
[    0.000000] RSP: 0018:ffffffff81a01cd8  EFLAGS: 00010046
[    0.000000] RAX: ffffffff81cb1748 RBX: ffffffff81cb1720 RCX: 0000000001000000
[    0.000000] RDX: 0000000000000040 RSI: 0000000000000000 RDI: ffffffff81cb1720
[    0.000000] RBP: ffffffff81a01d38 R08: 0000000000000000 R09: 0000000000001000
[    0.000000] R10: 02008921da802087 R11: 00000000ffff8800 R12: 0000000000000000
[    0.000000] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000001000000
[    0.000000] FS:  0000000000000000(0000) GS:ffff880002200000(0000) knlGS:0000000000000000
[    0.000000] CS:  0010 DS: 0018 ES: 0018 CR0: 0000000080050033
[    0.000000] CR2: 0000000000000000 CR3: 0000000001a85000 CR4: 00000000001406b0
[    0.000000] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[    0.000000] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
[    0.000000] Process swapper (pid: 0, threadinfo ffffffff81a00000, task ffffffff81a8d020)
[    0.000000] Stack:
[    0.000000]  0000000000000002 81a01dd881eaf060 000000007e5fe227 0000000000001001
[    0.000000] <d> 0000000000000040 0000000000000001 0000006cffffffff 0000000001000000
[    0.000000] <d> ffffffff81cb1720 0000000000000000 0000000000000000 0000000000000000
[    0.000000] Call Trace:
[    0.000000]  [<ffffffff81c4f074>] ___alloc_bootmem_nopanic+0x8d/0xca
[    0.000000]  [<ffffffff81c4f0cf>] ___alloc_bootmem+0x11/0x39
[    0.000000]  [<ffffffff81c4f172>] __alloc_bootmem+0xb/0xd
[    0.000000]  [<ffffffff814d42d9>] xsave_cntxt_init+0x249/0x2c0
[    0.000000]  [<ffffffff814e0689>] init_thread_xstate+0x17/0x25
[    0.000000]  [<ffffffff814e0710>] fpu_init+0x79/0xaa
[    0.000000]  [<ffffffff814e27e3>] cpu_init+0x301/0x344
[    0.000000]  [<ffffffff81276395>] ? sort+0x155/0x230
[    0.000000]  [<ffffffff81c30cf2>] trap_init+0x24e/0x25f
[    0.000000]  [<ffffffff81c2bd73>] start_kernel+0x21c/0x430
[    0.000000]  [<ffffffff81c2b33a>] x86_64_start_reservations+0x125/0x129
[    0.000000]  [<ffffffff81c2b438>] x86_64_start_kernel+0xfa/0x109
[    0.000000] Code: 03 48 89 f1 49 c1 e8 0c 48 0f af d0 48 c7 c6 00 a6 61 81 48 c7 c7 00 e5 79 81 31 c0 4c 89 74 24 08 e8 f2 d7 89 ff 4d 85 e4 75 04 <0f> 0b eb fe 48 8b 45 c0 48 83 e8 01 48 85 45
c0 74 04 0f 0b eb

Signed-off-by: Bingsong Si <[email protected]>
Message-Id: <20190822042901[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agotarget/i386: drop the duplicated definition of cpuid AVX512_VBMI macro
Tao Xu [Thu, 26 Sep 2019 02:10:55 +0000 (10:10 +0800)]
target/i386: drop the duplicated definition of cpuid AVX512_VBMI macro

Drop the duplicated definition of cpuid AVX512_VBMI macro and rename
it as CPUID_7_0_ECX_AVX512_VBMI. Rename CPUID_7_0_ECX_VBMI2 as
CPUID_7_0_ECX_AVX512_VBMI2.

Acked-by: Stefano Garzarella <[email protected]>
Signed-off-by: Tao Xu <[email protected]>
Message-Id: <20190926021055[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agotarget/i386: clean up comments over 80 chars per line
Tao Xu [Thu, 26 Sep 2019 02:10:54 +0000 (10:10 +0800)]
target/i386: clean up comments over 80 chars per line

Add some comments, clean up comments over 80 chars per line. And there
is an extra line in comment of CPUID_8000_0008_EBX_WBNOINVD, remove
the extra enter and spaces.

Acked-by: Stefano Garzarella <[email protected]>
Signed-off-by: Tao Xu <[email protected]>
Message-Id: <20190926021055[email protected]>
[ehabkost: rebase to latest git master]
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agomemory-device: break the loop if tmp exceed the hinted range
Wei Yang [Tue, 30 Jul 2019 00:37:40 +0000 (08:37 +0800)]
memory-device: break the loop if tmp exceed the hinted range

The memory-device list built by memory_device_build_list is ordered by
its address, this means if the tmp range exceed the hinted range, all
the following range will not overlap with it.

And this won't change default pc-dimm mapping and address assignment stay
the same as before this change.

Signed-off-by: Wei Yang <[email protected]>
Message-Id: <20190730003740[email protected]>
Reviewed-by: David Hildenbrand <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agomemory-device: not necessary to use goto for the last check
Wei Yang [Tue, 30 Jul 2019 00:37:39 +0000 (08:37 +0800)]
memory-device: not necessary to use goto for the last check

We are already at the last condition check.

Signed-off-by: Wei Yang <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Reviewed-by: David Hildenbrand <[email protected]>
Message-Id: <20190730003740[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agohw/misc/vmcoreinfo: Add comment about reset handler
Philippe Mathieu-Daudé [Thu, 10 Oct 2019 13:15:27 +0000 (15:15 +0200)]
hw/misc/vmcoreinfo: Add comment about reset handler

The VM coreinfo device does not sit on a bus, so it won't be
reset automatically. This is why it calls qemu_register_reset().

Add a comment about it, so we don't convert its reset handler
to a DeviceReset method.

Reviewed-by: Marc-André Lureau <[email protected]>
Reviewed-by: Li Qiang <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20191010131527[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agohw/input/lm832x: Convert reset handler to DeviceReset
Philippe Mathieu-Daudé [Thu, 10 Oct 2019 13:15:26 +0000 (15:15 +0200)]
hw/input/lm832x: Convert reset handler to DeviceReset

The LM8323 key-scan controller is a I2C device, it will be reset
when the I2C bus it stands on is reset.

Convert its reset handler into a proper Device reset method.

Reviewed-by: Li Qiang <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20191010131527[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agohw/isa/vt82c686: Convert reset handler to DeviceReset
Philippe Mathieu-Daudé [Thu, 10 Oct 2019 13:15:25 +0000 (15:15 +0200)]
hw/isa/vt82c686: Convert reset handler to DeviceReset

The VIA VT82C686 Southbridge is a PCI device, it will be reset
when the PCI bus it stands on is reset.

Convert its reset handler into a proper Device reset method.

Reviewed-by: Li Qiang <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20191010131527[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agohw/ide/via82c: Convert reset handler to DeviceReset
Philippe Mathieu-Daudé [Thu, 10 Oct 2019 13:15:24 +0000 (15:15 +0200)]
hw/ide/via82c: Convert reset handler to DeviceReset

The VIA82C686B IDE controller is a PCI device, it will be reset
when the PCI bus it stands on is reset.

Convert its reset handler into a proper Device reset method.

Reviewed-by: Li Qiang <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20191010131527[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agohw/ide/sii3112: Convert reset handler to DeviceReset
Philippe Mathieu-Daudé [Thu, 10 Oct 2019 13:15:23 +0000 (15:15 +0200)]
hw/ide/sii3112: Convert reset handler to DeviceReset

The SiI3112A SATA controller is a PCI device, it will be reset
when the PCI bus it stands on is reset.

Convert its reset handler into a proper Device reset method.

Reviewed-by: Li Qiang <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20191010131527[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agohw/ide/piix: Convert reset handler to DeviceReset
Philippe Mathieu-Daudé [Thu, 10 Oct 2019 13:15:22 +0000 (15:15 +0200)]
hw/ide/piix: Convert reset handler to DeviceReset

The PIIX/IDE is a PCI device within a PIIX chipset, it will be reset
when the PCI bus it stands on is reset.

Convert its reset handler into a proper Device reset method.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20191010131527[email protected]>
Reviewed-by: Li Qiang <[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agohw/isa/piix4: Convert reset handler to DeviceReset
Philippe Mathieu-Daudé [Thu, 10 Oct 2019 13:15:21 +0000 (15:15 +0200)]
hw/isa/piix4: Convert reset handler to DeviceReset

The PIIX4/ISA is a PCI device within the PIIX4 chipset, it will be reset
when the PCI bus it stands on is reset.

Convert its reset handler into a proper Device reset method.

Reviewed-by: Li Qiang <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20191010131527[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agohw/acpi/piix4: Convert reset handler to DeviceReset
Philippe Mathieu-Daudé [Thu, 10 Oct 2019 13:15:20 +0000 (15:15 +0200)]
hw/acpi/piix4: Convert reset handler to DeviceReset

The PIIX4/PM is a PCI device within the PIIX4 chipset, it will be reset
when the PCI bus it stands on is reset.

Convert its reset handler into a proper Device reset method.

Reviewed-by: Igor Mammedov <[email protected]>
Reviewed-by: Li Qiang <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20191010131527[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agonuma: Introduce MachineClass::auto_enable_numa for implicit NUMA node
Tao Xu [Thu, 5 Sep 2019 08:32:38 +0000 (16:32 +0800)]
numa: Introduce MachineClass::auto_enable_numa for implicit NUMA node

Add MachineClass::auto_enable_numa field. When it is true, a NUMA node
is expected to be created implicitly.

Acked-by: David Gibson <[email protected]>
Suggested-by: Igor Mammedov <[email protected]>
Suggested-by: Eduardo Habkost <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Signed-off-by: Tao Xu <[email protected]>
Message-Id: <20190905083238[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agotests: cpu-plug-test: fix device_add for pc/q35 machines
Igor Mammedov [Fri, 30 Aug 2019 11:07:23 +0000 (07:07 -0400)]
tests: cpu-plug-test: fix device_add for pc/q35 machines

Commit bc1fb850a3 silently broke device_add test for CPU hotplug which
resulted in test successfully passing though it wasn't actually run.
Fix it by making sure that all non present CPUs reported
by "query-hotpluggable-cpus" are hotplugged instead of making up
and hardcoding values.

Use of query-hotpluggable-cpus also allows consolidatiate device_add
cpu testcases and reuse the same test function for all targets.

While at it also add a check that at least one CPU was hotplugged,
to avoid silent breakage in the future.

Fixes: bc1fb850a3 (vl.c deprecate incorrect CPUs topology)
Signed-off-by: Igor Mammedov <[email protected]>
Message-Id: <20190830110723[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agotests: add qtest_qmp_device_add_qdict() helper
Igor Mammedov [Fri, 30 Aug 2019 11:07:22 +0000 (07:07 -0400)]
tests: add qtest_qmp_device_add_qdict() helper

Add an API that takes QDict directly, so users could skip steps
of first building json dictionary and converting it back to
QDict in existing qtest_qmp_device_add() and instead use QDict
directly without intermediate conversion.

Signed-off-by: Igor Mammedov <[email protected]>
Message-Id: <20190830110723[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>
5 years agoMerge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191015' into...
Peter Maydell [Tue, 15 Oct 2019 17:15:59 +0000 (18:15 +0100)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191015' into staging

target-arm queue:
 * Add Aspeed AST2600 SoC support (but no new board model yet)
 * aspeed/wdt: Check correct register for clock source
 * bcm2835: code cleanups, better logging, trace events
 * implement v2.0 of the Arm semihosting specification
 * provide new 'transaction-based' ptimer API and use it
   for the Arm devices that use ptimers
 * ARM: KVM: support more than 256 CPUs

# gpg: Signature made Tue 15 Oct 2019 18:09:42 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [ultimate]
# gpg:                 aka "Peter Maydell <[email protected]>" [ultimate]
# gpg:                 aka "Peter Maydell <[email protected]>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20191015: (67 commits)
  hw/misc/bcm2835_mbox: Add trace events
  hw/arm/bcm2835: Add various unimplemented peripherals
  hw/arm/bcm2835: Rename some definitions
  hw/arm/bcm2835_peripherals: Name various address spaces
  hw/arm/bcm2835_peripherals: Improve logging
  hw/arm/raspi: Use the IEC binary prefix definitions
  aspeed/soc: Add ASPEED Video stub
  aspeed: add support for the Aspeed MII controller of the AST2600
  aspeed: Parameterise number of MACs
  m25p80: Add support for w25q512jv
  aspeed/soc: Add AST2600 support
  aspeed: Introduce an object class per SoC
  aspeed/i2c: Add AST2600 support
  aspeed/i2c: Introduce an object class per SoC
  hw/gpio: Add in AST2600 specific implementation
  aspeed/smc: Add AST2600 support
  aspeed/smc: Introduce segment operations
  hw: wdt_aspeed: Add AST2600 support
  watchdog/aspeed: Introduce an object class per SoC
  aspeed/sdmc: Add AST2600 support
  ...

Signed-off-by: Peter Maydell <[email protected]>
5 years agohw/misc/bcm2835_mbox: Add trace events
Philippe Mathieu-Daudé [Thu, 26 Sep 2019 17:34:15 +0000 (19:34 +0200)]
hw/misc/bcm2835_mbox: Add trace events

Add trace events for read/write accesses and IRQ.

Properties are structures used for the ARM particular MBOX.
Since one call in bcm2835_property.c concerns the mbox block,
name this trace event in the same bcm2835_mbox* namespace.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: 20190926173428[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agohw/arm/bcm2835: Add various unimplemented peripherals
Philippe Mathieu-Daudé [Thu, 26 Sep 2019 17:34:13 +0000 (19:34 +0200)]
hw/arm/bcm2835: Add various unimplemented peripherals

Base addresses and sizes taken from the "BCM2835 ARM Peripherals"
datasheet from February 06 2012:
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: 20190926173428[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agohw/arm/bcm2835: Rename some definitions
Philippe Mathieu-Daudé [Thu, 26 Sep 2019 17:34:12 +0000 (19:34 +0200)]
hw/arm/bcm2835: Rename some definitions

The UART1 is part of the AUX peripheral,
the PCM_CLOCK (yet unimplemented) is part of the CPRMAN.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: 20190926173428[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agohw/arm/bcm2835_peripherals: Name various address spaces
Philippe Mathieu-Daudé [Thu, 26 Sep 2019 17:34:11 +0000 (19:34 +0200)]
hw/arm/bcm2835_peripherals: Name various address spaces

Various address spaces from the BCM2835 are reported as
'anonymous' in memory tree:

  (qemu) info mtree

  address-space: anonymous
    0000000000000000-000000000000008f (prio 0, i/o): bcm2835-mbox
      0000000000000010-000000000000001f (prio 0, i/o): bcm2835-fb
      0000000000000080-000000000000008f (prio 0, i/o): bcm2835-property

  address-space: anonymous
    0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu
      0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff
      0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff

  [...]

Since the address_space_init() function takes a 'name' argument,
set it to correctly describe each address space:

  (qemu) info mtree

  address-space: bcm2835-mbox-memory
    0000000000000000-000000000000008f (prio 0, i/o): bcm2835-mbox
      0000000000000010-000000000000001f (prio 0, i/o): bcm2835-fb
      0000000000000080-000000000000008f (prio 0, i/o): bcm2835-property

  address-space: bcm2835-fb-memory
    0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu
      0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff
      0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff

  address-space: bcm2835-property-memory
    0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu
      0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff
      0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff

  address-space: bcm2835-dma-memory
    0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu
      0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff
      0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
      00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Cleber Rosa <[email protected]>
Message-id: 20190926173428[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agohw/arm/bcm2835_peripherals: Improve logging
Philippe Mathieu-Daudé [Thu, 26 Sep 2019 17:34:10 +0000 (19:34 +0200)]
hw/arm/bcm2835_peripherals: Improve logging

Various logging improvements as once:
- Use 0x prefix for hex numbers
- Display value written during write accesses
- Move some logs from GUEST_ERROR to UNIMP

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Cleber Rosa <[email protected]>
Message-id: 20190926173428[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agohw/arm/raspi: Use the IEC binary prefix definitions
Philippe Mathieu-Daudé [Thu, 26 Sep 2019 17:34:09 +0000 (19:34 +0200)]
hw/arm/raspi: Use the IEC binary prefix definitions

IEC binary prefixes ease code review: the unit is explicit.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Cleber Rosa <[email protected]>
Message-id: 20190926173428[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/soc: Add ASPEED Video stub
Joel Stanley [Wed, 25 Sep 2019 14:32:48 +0000 (16:32 +0200)]
aspeed/soc: Add ASPEED Video stub

Signed-off-by: Joel Stanley <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed: add support for the Aspeed MII controller of the AST2600
Cédric Le Goater [Wed, 25 Sep 2019 14:32:47 +0000 (16:32 +0200)]
aspeed: add support for the Aspeed MII controller of the AST2600

The AST2600 SoC has an extra controller to set the PHY registers.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed: Parameterise number of MACs
Joel Stanley [Wed, 25 Sep 2019 14:32:46 +0000 (16:32 +0200)]
aspeed: Parameterise number of MACs

To support the ast2600's four MACs allow SoCs to specify the number
they have, and create that many.

Signed-off-by: Joel Stanley <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Message-id: 20190925143248[email protected]
[clg: - included a check on sc->macs_num when realizing the macs
      - included interrupt definitions for the AST2600 ]
Signed-off-by: Cédric Le Goater <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
5 years agom25p80: Add support for w25q512jv
Cédric Le Goater [Wed, 25 Sep 2019 14:32:44 +0000 (16:32 +0200)]
m25p80: Add support for w25q512jv

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/soc: Add AST2600 support
Cédric Le Goater [Wed, 25 Sep 2019 14:32:43 +0000 (16:32 +0200)]
aspeed/soc: Add AST2600 support

Initial definitions for a simple machine using an AST2600 SoC (Cortex
CPU).

The Cortex CPU and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new Aspeed SoC
class with instance_init and realize handlers to handle the differences
with the AST2400 and the AST2500 SoCs. This will add extra work to
keep in sync both models with future extensions but it makes the code
clearer.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed: Introduce an object class per SoC
Cédric Le Goater [Wed, 25 Sep 2019 14:32:42 +0000 (16:32 +0200)]
aspeed: Introduce an object class per SoC

It prepares ground for the AST2600.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/i2c: Add AST2600 support
Cédric Le Goater [Wed, 25 Sep 2019 14:32:41 +0000 (16:32 +0200)]
aspeed/i2c: Add AST2600 support

The I2C controller of the AST2400 and AST2500 SoCs have one IRQ shared
by all I2C busses. The AST2600 SoC I2C controller has one IRQ per bus
and 16 busses.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/i2c: Introduce an object class per SoC
Cédric Le Goater [Wed, 25 Sep 2019 14:32:40 +0000 (16:32 +0200)]
aspeed/i2c: Introduce an object class per SoC

It prepares ground for register differences between SoCs.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agohw/gpio: Add in AST2600 specific implementation
Rashmica Gupta [Wed, 25 Sep 2019 14:32:39 +0000 (16:32 +0200)]
hw/gpio: Add in AST2600 specific implementation

The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
addtional two sets of 1.8V gpios.

Signed-off-by: Rashmica Gupta <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Acked-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/smc: Add AST2600 support
Cédric Le Goater [Wed, 25 Sep 2019 14:32:38 +0000 (16:32 +0200)]
aspeed/smc: Add AST2600 support

The AST2600 SoC SMC controller is a SPI only controller now and has a
few extensions which we will need to take into account when SW
requires it. This is enough to support u-boot and Linux.

Signed-off-by: Cédric Le Goater <[email protected]>
Acked-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/smc: Introduce segment operations
Cédric Le Goater [Wed, 25 Sep 2019 14:32:37 +0000 (16:32 +0200)]
aspeed/smc: Introduce segment operations

AST2600 will use a different encoding for the addresses defined in the
Segment Register.

Signed-off-by: Cédric Le Goater <[email protected]>
Acked-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agohw: wdt_aspeed: Add AST2600 support
Joel Stanley [Wed, 25 Sep 2019 14:32:36 +0000 (16:32 +0200)]
hw: wdt_aspeed: Add AST2600 support

The AST2600 has four watchdogs, and they each have a 0x40 of registers.

When running as part of an ast2600 system we must check a different
offset for the system reset control register in the SCU.

Signed-off-by: Joel Stanley <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Message-id: 20190925143248[email protected]
[clg: - reworked model integration into new object class ]
Signed-off-by: Cédric Le Goater <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
5 years agowatchdog/aspeed: Introduce an object class per SoC
Cédric Le Goater [Wed, 25 Sep 2019 14:32:35 +0000 (16:32 +0200)]
watchdog/aspeed: Introduce an object class per SoC

It cleanups the current models for the Aspeed AST2400 and AST2500 SoCs
and prepares ground for future SoCs.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/sdmc: Add AST2600 support
Joel Stanley [Wed, 25 Sep 2019 14:32:34 +0000 (16:32 +0200)]
aspeed/sdmc: Add AST2600 support

The AST2600 SDMC controller is slightly different from its predecessor
(DRAM training). Max memory is now 2G on the AST2600.

Signed-off-by: Joel Stanley <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Message-id: 20190925143248[email protected]
[clg: - improved commit log
      - reworked model integration into new object class ]
Signed-off-by: Cédric Le Goater <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/sdmc: Introduce an object class per SoC
Cédric Le Goater [Wed, 25 Sep 2019 14:32:33 +0000 (16:32 +0200)]
aspeed/sdmc: Introduce an object class per SoC

Use class handlers and class constants to differentiate the
characteristics of the memory controller and remove the 'silicon_rev'
property.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/timer: Add support for IRQ status register on the AST2600
Cédric Le Goater [Wed, 25 Sep 2019 14:32:32 +0000 (16:32 +0200)]
aspeed/timer: Add support for IRQ status register on the AST2600

The AST2600 timer replaces control register 2 with a interrupt status
register. It is set by hardware when an IRQ occurs and cleared by
software.

Modify the vmstate version to take into account the new fields.

Based on previous work from Joel Stanley.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/timer: Add AST2600 support
Cédric Le Goater [Wed, 25 Sep 2019 14:32:31 +0000 (16:32 +0200)]
aspeed/timer: Add AST2600 support

The AST2600 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.

On the AST2600, it is not configurable via 0x38 (control register 3)
as it is on the AST2500.

Based on previous work from Joel Stanley.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/timer: Add support for control register 3
Cédric Le Goater [Wed, 25 Sep 2019 14:32:30 +0000 (16:32 +0200)]
aspeed/timer: Add support for control register 3

The AST2500 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.

This models the behaviour expected by the AST2500 while maintaining
the same behaviour for the AST2400.

The vmstate version is not increased yet because the structure is
modified again in the following patches.

Based on previous work from Joel Stanley.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/timer: Introduce an object class per SoC
Cédric Le Goater [Wed, 25 Sep 2019 14:32:29 +0000 (16:32 +0200)]
aspeed/timer: Introduce an object class per SoC

The most important changes will be on the register range 0x34 - 0x3C
memops. Introduce class read/write operations to handle the
differences between SoCs.

Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-id: 20190925143248[email protected]
Signed-off-by: Peter Maydell <[email protected]>
5 years agohw: aspeed_scu: Add AST2600 support
Joel Stanley [Wed, 25 Sep 2019 14:32:28 +0000 (16:32 +0200)]
hw: aspeed_scu: Add AST2600 support

The SCU controller on the AST2600 SoC has extra registers. Increase
the number of regs of the model and introduce a new field in the class
to customize the MemoryRegion operations depending on the SoC model.

Signed-off-by: Joel Stanley <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Message-id: 20190925143248[email protected]
[clg: - improved commit log
      - changed vmstate version
      - reworked model integration into new object class
      - included AST2600_HPLL_PARAM value ]
Signed-off-by: Cédric Le Goater <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
5 years agohw/sd/aspeed_sdhci: New device
Eddie James [Wed, 25 Sep 2019 14:32:27 +0000 (16:32 +0200)]
hw/sd/aspeed_sdhci: New device

The Aspeed SOCs have two SD/MMC controllers. Add a device that
encapsulates both of these controllers and models the Aspeed-specific
registers and behavior.

Tested by reading from mmcblk0 in Linux:
qemu-system-arm -machine romulus-bmc -nographic \
 -drive file=flash-romulus,format=raw,if=mtd \
 -device sd-card,drive=sd0 -drive file=_tmp/kernel,format=raw,if=sd,id=sd0

Signed-off-by: Eddie James <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Message-id: 20190925143248[email protected]
[clg: - changed the controller MMIO window size to 0x1000
      - moved the MMIO mapping of the SDHCI slots at the SoC level
      - merged code to add SD drives on the SD buses at the machine level ]
Signed-off-by: Cédric Le Goater <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
5 years agoaspeed/wdt: Check correct register for clock source
Amithash Prasad [Wed, 25 Sep 2019 14:32:26 +0000 (16:32 +0200)]
aspeed/wdt: Check correct register for clock source

When WDT_RESTART is written, the data is not the contents
of the WDT_CTRL register. Hence ensure we are looking at
WDT_CTRL to check if bit WDT_CTRL_1MHZ_CLK is set or not.

Signed-off-by: Amithash Prasad <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Message-id: 20190925143248[email protected]
[clg: improved Suject prefix ]
Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
5 years agotarget/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension
Peter Maydell [Mon, 16 Sep 2019 14:15:44 +0000 (15:15 +0100)]
target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension

SH_EXT_STDOUT_STDERR is a v2.0 semihosting extension: the guest
can open ":tt" with a file mode requesting append access in
order to open stderr, in addition to the existing "open for
read for stdin or write for stdout". Implement this and
report it via the :semihosting-features data.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension
Peter Maydell [Mon, 16 Sep 2019 14:15:43 +0000 (15:15 +0100)]
target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension

SH_EXT_EXIT_EXTENDED is a v2.0 semihosting extension: it
indicates that the implementation supports the SYS_EXIT_EXTENDED
function. This function allows both A64 and A32/T32 guests to
exit with a specified exit status, unlike the older SYS_EXIT
function which only allowed this for A64 guests. Implement
this extension.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Implement support for semihosting feature detection
Peter Maydell [Mon, 16 Sep 2019 14:15:42 +0000 (15:15 +0100)]
target/arm/arm-semi: Implement support for semihosting feature detection

Version 2.0 of the semihosting specification added support for
allowing a guest to detect whether the implementation supported
particular features. This works by the guest opening a magic
file ":semihosting-features", which contains a fixed set of
data with some magic numbers followed by a sequence of bytes
with feature flags. The file is expected to behave sensibly
for the various semihosting calls which operate on files
(SYS_FLEN, SYS_SEEK, etc).

Implement this as another kind of guest FD using our function
table dispatch mechanism. Initially we report no extended
features, so we have just one feature flag byte which is zero.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Factor out implementation of SYS_FLEN
Peter Maydell [Mon, 16 Sep 2019 14:15:41 +0000 (15:15 +0100)]
target/arm/arm-semi: Factor out implementation of SYS_FLEN

Factor out the implementation of SYS_FLEN via the new
function tables.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Factor out implementation of SYS_SEEK
Peter Maydell [Mon, 16 Sep 2019 14:15:40 +0000 (15:15 +0100)]
target/arm/arm-semi: Factor out implementation of SYS_SEEK

Factor out the implementation of SYS_SEEK via the new function
tables.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Factor out implementation of SYS_ISTTY
Peter Maydell [Mon, 16 Sep 2019 14:15:39 +0000 (15:15 +0100)]
target/arm/arm-semi: Factor out implementation of SYS_ISTTY

Factor out the implementation of SYS_ISTTY via the new function
tables.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Factor out implementation of SYS_READ
Peter Maydell [Mon, 16 Sep 2019 14:15:38 +0000 (15:15 +0100)]
target/arm/arm-semi: Factor out implementation of SYS_READ

Factor out the implementation of SYS_READ via the
new function tables.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Factor out implementation of SYS_WRITE
Peter Maydell [Mon, 16 Sep 2019 14:15:37 +0000 (15:15 +0100)]
target/arm/arm-semi: Factor out implementation of SYS_WRITE

Factor out the implementation of SYS_WRITE via the
new function tables.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Factor out implementation of SYS_CLOSE
Peter Maydell [Mon, 16 Sep 2019 14:15:36 +0000 (15:15 +0100)]
target/arm/arm-semi: Factor out implementation of SYS_CLOSE

Currently for the semihosting calls which take a file descriptor
(SYS_CLOSE, SYS_WRITE, SYS_READ, SYS_ISTTY, SYS_SEEK, SYS_FLEN)
we have effectively two implementations, one for real host files
and one for when we indirect via the gdbstub. We want to add a
third one to deal with the magic :semihosting-features file.

Instead of having a three-way if statement in each of these
cases, factor out the implementation of the calls to separate
functions which we dispatch to via function pointers selected
via the GuestFDType for the guest fd.

In this commit, we set up the framework for the dispatch,
and convert the SYS_CLOSE call to use it.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Use set_swi_errno() in gdbstub callback functions
Peter Maydell [Mon, 16 Sep 2019 14:15:35 +0000 (15:15 +0100)]
target/arm/arm-semi: Use set_swi_errno() in gdbstub callback functions

When we are routing semihosting operations through the gdbstub, the
work of sorting out the return value and setting errno if necessary
is done by callback functions which are invoked by the gdbstub code.
Clean up some ifdeffery in those functions by having them call
set_swi_errno() to set the semihosting errno.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Restrict use of TaskState*
Peter Maydell [Mon, 16 Sep 2019 14:15:34 +0000 (15:15 +0100)]
target/arm/arm-semi: Restrict use of TaskState*

The semihosting code needs accuss to the linux-user only
TaskState pointer so it can set the semihosting errno per-thread
for linux-user mode. At the moment we do this by having some
ifdefs so that we define a 'ts' local in do_arm_semihosting()
which is either a real TaskState * or just a CPUARMState *,
depending on which mode we're compiling for.

This is awkward if we want to refactor do_arm_semihosting()
into other functions which might need to be passed the TaskState.
Restrict usage of the TaskState local by:
 * making set_swi_errno() always take the CPUARMState pointer
   and (for the linux-user version) get TaskState from that
 * creating a new get_swi_errno() which reads the errno
 * having the two semihosting calls which need the TaskState
   for other purposes (SYS_GET_CMDLINE and SYS_HEAPINFO)
   define a variable with scope restricted to just that code

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Make semihosting code hand out its own file descriptors
Peter Maydell [Mon, 16 Sep 2019 14:15:33 +0000 (15:15 +0100)]
target/arm/arm-semi: Make semihosting code hand out its own file descriptors

Currently the Arm semihosting code returns the guest file descriptors
(handles) which are simply the fd values from the host OS or the
remote gdbstub. Part of the semihosting 2.0 specification requires
that we implement special handling of opening a ":semihosting-features"
filename. Guest fds which result from opening the special file
won't correspond to host fds, so to ensure that we don't end up
with duplicate fds we need to have QEMU code control the allocation
of the fd values we give the guest.

Add in an abstraction layer which lets us allocate new guest FD
values, and translate from a guest FD value back to the host one.
This also fixes an odd hole where a semihosting guest could
use the semihosting API to read, write or close file descriptors
that it had never allocated but which were being used by QEMU itself.
(This isn't a security hole, because enabling semihosting permits
the guest to do arbitrary file access to the whole host filesystem,
and so should only be done if the guest is completely trusted.)

Currently the only kind of guest fd is one which maps to a
host fd, but in a following commit we will add one which maps
to the :semihosting-features magic data.

If the guest is migrated with an open semihosting file descriptor
then subsequent attempts to use the fd will all fail; this is
not a change from the previous situation (where the host fd
being used on the source end would not be re-opened on the
destination end).

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Correct comment about gdb syscall races
Peter Maydell [Mon, 16 Sep 2019 14:15:32 +0000 (15:15 +0100)]
target/arm/arm-semi: Correct comment about gdb syscall races

In arm_gdb_syscall() we have a comment suggesting a race
because the syscall completion callback might not happen
before the gdb_do_syscallv() call returns. The comment is
correct that the callback may not happen but incorrect about
the effects. Correct it and note the important caveat that
callers must never do any work of any kind after return from
arm_gdb_syscall() that depends on its return value.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Always set some kind of errno for failed calls
Peter Maydell [Mon, 16 Sep 2019 14:15:31 +0000 (15:15 +0100)]
target/arm/arm-semi: Always set some kind of errno for failed calls

If we fail a semihosting call we should always set the
semihosting errno to something; we were failing to do
this for some of the "check inputs for sanity" cases.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20190916141544[email protected]

5 years agotarget/arm/arm-semi: Capture errno in softmmu version of set_swi_errno()
Peter Maydell [Mon, 16 Sep 2019 14:15:30 +0000 (15:15 +0100)]
target/arm/arm-semi: Capture errno in softmmu version of set_swi_errno()

The set_swi_errno() function is called to capture the errno
from a host system call, so that we can return -1 from the
semihosting function and later allow the guest to get a more
specific error code with the SYS_ERRNO function. It comes in
two versions, one for user-only and one for softmmu. We forgot
to capture the errno in the softmmu version; fix the error.

(Semihosting calls directed to gdb are unaffected because
they go through a different code path that captures the
error return from the gdbstub call in arm_semi_cb() or
arm_semi_flen_cb().)

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20190916141544[email protected]

5 years agohw/net/lan9118.c: Switch to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:40 +0000 (18:17 +0100)]
hw/net/lan9118.c: Switch to transaction-based ptimer API

Switch the cmsdk-apb-watchdog code away from bottom-half based
ptimers to the new transaction-based ptimer API.  This just requires
adding begin/commit calls around the various places that modify the
ptimer state, and using the new ptimer_init() function to create the
timer.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/watchdog/cmsdk-apb-watchdog.c: Switch to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:39 +0000 (18:17 +0100)]
hw/watchdog/cmsdk-apb-watchdog.c: Switch to transaction-based ptimer API

Switch the cmsdk-apb-watchdog code away from bottom-half based
ptimers to the new transaction-based ptimer API.  This just requires
adding begin/commit calls around the various places that modify the
ptimer state, and using the new ptimer_init() function to create the
timer.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/mss-timerc: Switch to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:38 +0000 (18:17 +0100)]
hw/timer/mss-timerc: Switch to transaction-based ptimer API

Switch the mss-timer code away from bottom-half based ptimers to
the new transaction-based ptimer API.  This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/imx_gpt.c: Switch to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:37 +0000 (18:17 +0100)]
hw/timer/imx_gpt.c: Switch to transaction-based ptimer API

Switch the imx_epit.c code away from bottom-half based ptimers to
the new transaction-based ptimer API.  This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/imx_epit.c: Switch to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:36 +0000 (18:17 +0100)]
hw/timer/imx_epit.c: Switch to transaction-based ptimer API

Switch the imx_epit.c code away from bottom-half based ptimers to
the new transaction-based ptimer API.  This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/exynos4210_rtc.c: Switch main ptimer to transaction-based API
Peter Maydell [Tue, 8 Oct 2019 17:17:35 +0000 (18:17 +0100)]
hw/timer/exynos4210_rtc.c: Switch main ptimer to transaction-based API

Switch the exynos41210_rtc main ptimer over to the transaction-based
API, completing the transition for this device.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/exynos4210_rtc.c: Switch 1Hz ptimer to transaction-based API
Peter Maydell [Tue, 8 Oct 2019 17:17:34 +0000 (18:17 +0100)]
hw/timer/exynos4210_rtc.c: Switch 1Hz ptimer to transaction-based API

Switch the exynos41210_rtc 1Hz ptimer over to the transaction-based
API. (We will switch the other ptimer used by this device in a
separate commit.)

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/exynos4210_pwm.c: Switch to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:33 +0000 (18:17 +0100)]
hw/timer/exynos4210_pwm.c: Switch to transaction-based ptimer API

Switch the exynos4210_pwm code away from bottom-half based ptimers to
the new transaction-based ptimer API.  This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/exynos4210_mct.c: Switch ltick to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:32 +0000 (18:17 +0100)]
hw/timer/exynos4210_mct.c: Switch ltick to transaction-based ptimer API

Switch the ltick ptimer over to the ptimer transaction API.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/exynos4210_mct.c: Switch LFRC to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:31 +0000 (18:17 +0100)]
hw/timer/exynos4210_mct.c: Switch LFRC to transaction-based ptimer API

Switch the exynos MCT LFRC timers over to the ptimer transaction API.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/exynos4210_mct.c: Switch GFRC to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:30 +0000 (18:17 +0100)]
hw/timer/exynos4210_mct.c: Switch GFRC to transaction-based ptimer API

We want to switch the exynos MCT code away from bottom-half based ptimers to
the new transaction-based ptimer API. The MCT is complicated
and uses multiple different ptimers, so it's clearer to switch
it a piece at a time. Here we change over only the GFRC.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/digic-timer.c: Switch to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:29 +0000 (18:17 +0100)]
hw/timer/digic-timer.c: Switch to transaction-based ptimer API

Switch the digic-timer.c code away from bottom-half based ptimers to
the new transaction-based ptimer API.  This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

5 years agohw/timer/cmsdk-apb-timer.c: Switch to transaction-based ptimer API
Peter Maydell [Tue, 8 Oct 2019 17:17:28 +0000 (18:17 +0100)]
hw/timer/cmsdk-apb-timer.c: Switch to transaction-based ptimer API

Switch the cmsdk-apb-timer code away from bottom-half based ptimers
to the new transaction-based ptimer API.  This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20191008171740[email protected]

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