qapi: rework qapi Exception

Use a base class QAPIError, and QAPIParseError for parser errors and
QAPISemError for semantic errors, suggested by Markus Armbruster.

Signed-off-by: Marc-André Lureau <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Message-Id: <20170113144135[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

docs: add master qapi texi files

The qapi2texi script generates a file to be included in a texi file. Add
"QEMU QMP Reference Manual" and "QEMU Guest Agent Protocol Reference"
master texi files.

Signed-off-by: Marc-André Lureau <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Message-Id: <20170113144135[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

qapi: add some sections in docs

Add some more section titles to organize the documentation we're going
to generate.

Signed-off-by: Marc-André Lureau <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Message-Id: <20170113144135[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

qapi: Move "command is experimental" notes down

Move these notes down and prefix with "Note:", to please the doc
generator we're going to add.

Signed-off-by: Marc-André Lureau <[email protected]>
Message-Id: <20170113144135[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
[Commit message tweaked]
Signed-off-by: Markus Armbruster <[email protected]>

qapi: Reorder doc comments for future doc generator

The doc generator we're going to add expects a fairly rigid doc
comment structure.  Reorder / rephrase some doc comments to please it.

Signed-off-by: Marc-André Lureau <[email protected]>
Message-Id: <20170113144135[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
[Commit message rewritten]
Signed-off-by: Markus Armbruster <[email protected]>

qga/schema: improve guest-set-vcpus Returns: section

Itemize the possible return values of guest-set-vcpus.

Drop the blank lines for consistency with itemized
lists elsewhere.

Signed-off-by: Marc-André Lureau <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Message-Id: <20170113144135[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

qapi: improve TransactionAction doc

TransactionAction is a flat union, document 'type' versions
exhaustively, and sort the members.

Signed-off-by: Marc-André Lureau <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Message-Id: <20170113144135[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

qapi: improve device_add schema

'device_add' is still incomplete for now, but we can fix a few
arguments:
- 'bus' is a common argument, regardless of the device
- 'id' is an optional argument

Signed-off-by: Marc-André Lureau <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Message-Id: <20170113144135[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

qapi: Format TODO comments more consistently

Consistently put a colon after TODO.  This will make the TODOs stand
out in the documentation we're going to generate.

Signed-off-by: Marc-André Lureau <[email protected]>
Message-Id: <20170113144135[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
[Commit message rewritten]
Signed-off-by: Markus Armbruster <[email protected]>

qapi: move QKeyCode doc body at the top

Following documentation guidelines.

Signed-off-by: Marc-André Lureau <[email protected]>
Message-Id: <20170113144135[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

qapi: replace 'o' for list items

Replace with '*', the common form for list items.

Signed-off-by: Marc-André Lureau <[email protected]>
Message-Id: <20170113144135[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging

x86 and machine queue, 2017-01-17

Includes i386, CPU, NUMA, and memory backends changes.

i386:
 target/i386: Fix bad patch application to translate.c

CPU:
 qmp: Report QOM type name on query-cpu-definitions

NUMA:
 numa: make -numa parser dynamically allocate CPUs masks

Memory backends:
 qom: remove unused header
 monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
 monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends

# gpg: Signature made Thu 12 Jan 2017 17:53:11 GMT
# gpg:                using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <[email protected]>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-and-machine-pull-request:
  qmp: Report QOM type name on query-cpu-definitions
  numa: make -numa parser dynamically allocate CPUs masks
  target/i386: Fix bad patch application to translate.c
  monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends
  monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
  qom: remove unused header

Signed-off-by: Peter Maydell <[email protected]>

Merge remote-tracking branch 'remotes/stsquad/tags/pull-travis-20170112-1' into staging

A couple of fixes to reduce the matrix some more that just missed the
last iteration.

# gpg: Signature made Thu 12 Jan 2017 13:01:49 GMT
# gpg:                using RSA key 0xFBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <[email protected]>"
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-travis-20170112-1:
  travis: add Trusty with clang stable build
  travis: trim out most clang builds

Signed-off-by: Peter Maydell <[email protected]>

sdl2: fix build failure on windows

Cc: Stefan Weil <[email protected]>
Cc: Samuel Thibault <[email protected]>
Signed-off-by: Gerd Hoffmann <[email protected]>
Reviewed-by: Stefan Weil <[email protected]>
Message-id: 1484295285[email protected]
Signed-off-by: Peter Maydell <[email protected]>

Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2' into staging

TriCore FPU patches

# gpg: Signature made Wed 11 Jan 2017 13:40:11 GMT
# gpg:                using RSA key 0x0AD2C6396B69CA14
# gpg: Good signature from "Bastian Koppelmann <[email protected]>"
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E  6E37 0AD2 C639 6B69 CA14

* remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2:
  target-tricore: Add updfl instruction
  target-tricore: Added new JNE instruction variant
  target-tricore: Added new MOV instruction variant
  target-tricore: Added MADD.F and MSUB.F instructions
  target-tricore: Added FTOUZ instruction

Signed-off-by: Peter Maydell <[email protected]>

Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20170111-1' into staging

vga: fixes for virtio-gpu and cirrus.

# gpg: Signature made Wed 11 Jan 2017 10:24:24 GMT
# gpg:                using RSA key 0x4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <[email protected]>"
# gpg:                 aka "Gerd Hoffmann <[email protected]>"
# gpg:                 aka "Gerd Hoffmann (private) <[email protected]>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/pull-vga-20170111-1:
  virtio-gpu: tag as not hotpluggable
  virtio-gpu: Fix memory leak in virtio_gpu_load()
  virtio-gpu: Recalculate VirtIOGPU::hostmem on VM load
  display: cirrus: ignore source pitch value as needed in blit_is_unsafe
  virtio-gpu: fix information leak in capset get dispatch

Signed-off-by: Peter Maydell <[email protected]>

qmp: Report QOM type name on query-cpu-definitions

The new typename attribute on query-cpu-definitions will be used
to help management software use device-list-properties to check
which properties can be set using -cpu or -global for the CPU
model.

Signed-off-by: Eduardo Habkost <[email protected]>
Message-Id: <1479320499[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>

numa: make -numa parser dynamically allocate CPUs masks

so it won't impose an additional limits on max_cpus limits
supported by different targets.

It removes global MAX_CPUMASK_BITS constant and need to
bump it up whenever max_cpus is being increased for
a target above MAX_CPUMASK_BITS value.

Use runtime max_cpus value instead to allocate sufficiently
sized node_cpu bitmasks in numa parser.

Signed-off-by: Igor Mammedov <[email protected]>
Message-Id: <1479466974[email protected]>
Reviewed-by: Eduardo Habkost <[email protected]>
[ehabkost: Added asserts to ensure cpu_index < max_cpus]
Signed-off-by: Eduardo Habkost <[email protected]>

target/i386: Fix bad patch application to translate.c

In commit c52ab08aee6f7d4717fc6b517174043126bd302f,
the patch snippet for the "syscall" insn got applied to "iret".

Signed-off-by: Doug Evans <[email protected]>
Message-Id: <f403045cde4049058c05446d5c04@google.com>
Signed-off-by: Eduardo Habkost <[email protected]>

monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends

Considering 'id' is mandatory for user_creatable objects/backends
and user_creatable_add_type() always has it as an argument
regardless of where from it is called CLI/monitor or QMP,
Fix issue by adding 'id' property to hostmem backends and
set it in user_creatable_add_type() for every object that
implements 'id' property. Then later at query-memdev time
get 'id' from object directly.

Signed-off-by: Igor Mammedov <[email protected]>
Message-Id: <1484052795[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>

monitor: reuse user_creatable_add_opts() instead of user_creatable_add()

Simplify code by dropping ~57LOC by merging user_creatable_add()
into user_creatable_add_opts() and using the later from monitor.
Along with it allocate opts_visitor_new() once in user_creatable_add_opts().

As result we have one less API func and a more readable/simple
user_creatable_add_opts() vs user_creatable_add().

Signed-off-by: Igor Mammedov <[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Message-Id: <1484052795[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>

Merge remote-tracking branch 'remotes/kraxel/tags/pull-audio-20170111-1' into staging

audio: qomify drivers, hotplug fixes.

# gpg: Signature made Wed 11 Jan 2017 09:32:09 GMT
# gpg:                using RSA key 0x4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <[email protected]>"
# gpg:                 aka "Gerd Hoffmann <[email protected]>"
# gpg:                 aka "Gerd Hoffmann (private) <[email protected]>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/pull-audio-20170111-1:
  es1370: wire up reset via DeviceClass
  audio: ac97: add exit function
  audio: es1370: add exit function
  hw/audio: QOM'ify pl041.c
  hw/audio: QOM'ify marvell_88w8618.c

Signed-off-by: Peter Maydell <[email protected]>

qom: remove unused header

Signed-off-by: Igor Mammedov <[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Message-Id: <1484052795[email protected]>
Signed-off-by: Eduardo Habkost <[email protected]>

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170110' into staging

TCG opcodes for extract, clz, ctz, ctpop

# gpg: Signature made Wed 11 Jan 2017 02:12:41 GMT
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <[email protected]>"
# gpg:                 aka "Richard Henderson <[email protected]>"
# gpg:                 aka "Richard Henderson <[email protected]>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-tcg-20170110: (65 commits)
  tcg/i386: Handle ctpop opcode
  tcg/ppc: Handle ctpop opcode
  tcg: Use ctpop to generate ctz if needed
  tests: New test-bitcnt
  qemu/host-utils.h: Reduce the operation count in the fallback ctpop
  target-i386: Use ctpop helper
  target-tilegx: Use ctpop helper
  target-sparc: Use ctpop helper
  target-s390x: Avoid a loop for popcnt
  target-ppc: Use ctpop helper
  target-alpha: Use ctpop helper
  tcg: Add opcode for ctpop
  target-xtensa: Use clrsb helper
  target-tricore: Use clrsb helper
  target-arm: Use clrsb helper
  tcg: Add helpers for clrsb
  tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR
  tcg/i386: Handle ctz and clz opcodes
  tcg/i386: Allow bmi2 shiftx to have non-matching operands
  tcg/i386: Hoist common arguments in tcg_out_op
  ...

Signed-off-by: Peter Maydell <[email protected]>

libqtest: handle zero length memwrite/memread

Some recently added tests pass a zero length to qtest_memwrite().
Unfortunately, the qtest protocol doesn't implement an on-the-wire
syntax for zero-length writes and the current code happily sends
garbage to QEMU. This causes intermittent failures.

It isn't worth the pain to enhance the protocol, so this patch
simply fixes the issue by "just return, doing nothing". The same
fix is applied to qtest_memread() since the issue also exists in
the QEMU part of the "memread" command.

Suggested-by: Peter Maydell <[email protected]>
Signed-off-by: Greg Kurz <[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: 148412457273.22750.983275587432075569.stgit@bahia
Signed-off-by: Peter Maydell <[email protected]>

travis: add Trusty with clang stable build

Although we've reduced the matrix to avoid repeating clang builds we can
still add an additional clang build to use the latest stable version of
clang which will typically be available on current distros.

Signed-off-by: Alex Bennée <[email protected]>

travis: trim out most clang builds

We test with both gcc and clang in order to detect cases
where clang issues warnings that gcc misses. To achieve
this though we don't need to build QEMU in multiple
different configurations. Just a single clang-on-linux
build will be sufficient, if we have an "all enabled"
config.

This cuts the number of build jobs from 21 to 16,
reducing the load imposed on shared Travis CI infra.
This will make it practical to enable jobs for other
interesting & useful configurations without DOS'ing
Travis to much.

Signed-off-by: Daniel P. Berrange <[email protected]>
Reviewed-by: Stefan Hajnoczi <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>

target-tricore: Add updfl instruction

Signed-off-by: Bastian Koppelmann <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>

target-tricore: Added new JNE instruction variant

If D[15] is != sign_ext(const4) then PC will be set to (PC +
zero_ext(disp4 + 16)).

[BK: fixed style errors]
Signed-off-by: Peer Adelt <[email protected]>
Message-Id: <1465314555[email protected]>
Signed-off-by: Bastian Koppelmann <[email protected]>

target-tricore: Added new MOV instruction variant

Puts the content of data register D[a] into E[c][63:32] and the
content of data register D[b] into E[c][31:0].

[BK: fix style error]
[BK: Allocate temporaries only when needed]
Signed-off-by: Peer Adelt <[email protected]>
Message-Id: <1465314555[email protected]>
Signed-off-by: Bastian Koppelmann <[email protected]>

target-tricore: Added MADD.F and MSUB.F instructions

Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d].
The result is put in D[c]. All operands are floating-point numbers.

Signed-off-by: Bastian Koppelmann <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>

target-tricore: Added FTOUZ instruction

Converts a 32-bit floating point number to an unsigned int. The
result is rounded towards zero.

Signed-off-by: Bastian Koppelmann <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>

virtio-gpu: tag as not hotpluggable

qemu can't hotplug display devices.

Signed-off-by: Gerd Hoffmann <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Message-id: 1483970138[email protected]

virtio-gpu: Fix memory leak in virtio_gpu_load()

Coverity points out that if we fail in the "creating resources"
loop in virtio_gpu_load() we will leak various resources (CID 1356431).
Failing a VM load is going to leave the simulation in a complete mess,
but we can tidy up to the point that a full system reset should
get us back to sanity.

Signed-off-by: Peter Maydell <[email protected]>
Message-id: 1483969123[email protected]
Signed-off-by: Gerd Hoffmann <[email protected]>

virtio-gpu: Recalculate VirtIOGPU::hostmem on VM load

The 'hostmem' field in VirtIOGPU is used to track the total memory
used in pixmaps so that we can impose a maximum limit on it.
However this field is neither migrated nor recalculated on
VM load, which means that after a migration it will be incorrectly
too low, which can allow the guest to use more pixmap memory
than it should. The per-resource hostmem fields are not filled
in either as we reallocate them in the load function.

Recalculate the memory used for each pixmap and the total memory
used as we reallocate the pixmaps in virtio_gpu_load().

Signed-off-by: Peter Maydell <[email protected]>
Message-id: 1483969123[email protected]
Signed-off-by: Gerd Hoffmann <[email protected]>

display: cirrus: ignore source pitch value as needed in blit_is_unsafe

Commit 4299b90 added a check which is too broad, given that the source
pitch value is not required to be initialized for solid fill operations.
This patch refines the blit_is_unsafe() check to ignore source pitch in
that case. After applying the above commit as a security patch, we
noticed the SLES 11 SP4 guest gui failed to initialize properly.

Signed-off-by: Bruce Rogers <[email protected]>
Message-id: 20170109203520[email protected]
Signed-off-by: Gerd Hoffmann <[email protected]>

virtio-gpu: fix information leak in capset get dispatch

In virgl_cmd_get_capset function, it uses g_malloc to allocate
a response struct to the guest. As the 'resp'struct hasn't been full
initialized it will lead the 'resp->padding' field to the guest.
Use g_malloc0 to avoid this.

Signed-off-by: Li Qiang <[email protected]>
Reviewed-by: Marc-André Lureau <[email protected]>
Message-id: 58188cae.4a6ec20a[email protected]

[ kraxel: resolved conflict ]

Signed-off-by: Gerd Hoffmann <[email protected]>

es1370: wire up reset via DeviceClass

Instead of using qemu_register_reset().
That way we get proper cleanup for free.

Signed-off-by: Gerd Hoffmann <[email protected]>
Message-id: 1484054281[email protected]

audio: ac97: add exit function

Currently the ac97 device emulation doesn't have a exit function,
hot unplug this device will leak some memory. Add a exit function to
avoid this.

Signed-off-by: Li Qiang <[email protected]>
Reviewed-by: Marc-André Lureau <[email protected]>
Message-id: 58520052.4825ed0a[email protected]
Signed-off-by: Gerd Hoffmann <[email protected]>

audio: es1370: add exit function

Currently the es1370 device emulation doesn't have a exit function,
hot unplug this device will leak some memory. Add a exit function to
avoid this.

Signed-off-by: Li Qiang <[email protected]>
Reviewed-by: Marc-André Lureau <[email protected]>
Message-id: 585200c9.a968ca0a[email protected]
Signed-off-by: Gerd Hoffmann <[email protected]>

hw/audio: QOM'ify pl041.c

split the old SysBus init function into an instance_init
and Device realize function

Signed-off-by: xiaoqiang zhao <[email protected]>
Message-id: 20161231011720[email protected]
Signed-off-by: Gerd Hoffmann <[email protected]>

hw/audio: QOM'ify marvell_88w8618.c

split the old SysBus init function into an instance_init
and Device realize function

Signed-off-by: xiaoqiang zhao <[email protected]>
Message-id: 20161231011720[email protected]
Signed-off-by: Gerd Hoffmann <[email protected]>

tcg/i386: Handle ctpop opcode

Signed-off-by: Richard Henderson <[email protected]>

tcg/ppc: Handle ctpop opcode

Signed-off-by: Richard Henderson <[email protected]>

tcg: Use ctpop to generate ctz if needed

Particularly when andc is also available, this is two insns
shorter than using clz to compute ctz.

Signed-off-by: Richard Henderson <[email protected]>

tests: New test-bitcnt

Add some unit tests for bit count functions (currently only ctpop). As
the routines are based on the Hackers Delight optimisations I based
the test patterns on their tests.

Signed-off-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

qemu/host-utils.h: Reduce the operation count in the fallback ctpop

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

target-i386: Use ctpop helper

Signed-off-by: Richard Henderson <[email protected]>

target-tilegx: Use ctpop helper

Signed-off-by: Richard Henderson <[email protected]>

target-sparc: Use ctpop helper

Acked-by: Mark Cave-Ayland <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

target-s390x: Avoid a loop for popcnt

Signed-off-by: Richard Henderson <[email protected]>

target-ppc: Use ctpop helper

Signed-off-by: Richard Henderson <[email protected]>

target-alpha: Use ctpop helper

Signed-off-by: Richard Henderson <[email protected]>

tcg: Add opcode for ctpop

The number of actual invocations of ctpop itself does not warrent
an opcode, but it is very helpful for POWER7 to use in generating
an expansion for ctz.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

target-xtensa: Use clrsb helper

Signed-off-by: Richard Henderson <[email protected]>

target-tricore: Use clrsb helper

Tested-by: Bastian Koppelmann <[email protected]>
Reviewed-by: Bastian Koppelmann <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

target-arm: Use clrsb helper

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Add helpers for clrsb

The number of actual invocations does not warrent an opcode,
and the backends generating it.  But at least we can eliminate
redundant helpers.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR

The ISA manual documents the output is undefined if the input was zero.

However, we document in target-i386 that the behavior of real silicon
is to preserve the contents of the output register.  We also mention
that there are real applications that depend on this.  That this is
baked into silicon is mentioned as a potential cause for some false
sharing behaviour wrt lzcnt/tzcnt.

Taking advantage of this allows us to save 2 insns in the normal case,
and 4 insns for i686 emulating a 64-bit clz.

Signed-off-by: Richard Henderson <[email protected]>

tcg/i386: Handle ctz and clz opcodes

Signed-off-by: Richard Henderson <[email protected]>

tcg/i386: Allow bmi2 shiftx to have non-matching operands

Previously we could not have different constraints for different ISA levels,
which prevented us from eliding the matching constraint for shifts.

We do now have to make sure that the operands match for constant shifts.
We can also handle some small left shifts via lea.

Signed-off-by: Richard Henderson <[email protected]>

tcg/i386: Hoist common arguments in tcg_out_op

Signed-off-by: Richard Henderson <[email protected]>

tcg/i386: Fuly convert tcg_target_op_def

Use a switch instead of searching a table.  Share constraints between
32-bit and 64-bit, when at all possible.

Signed-off-by: Richard Henderson <[email protected]>

tcg/s390: Handle clz opcode

Signed-off-by: Richard Henderson <[email protected]>

tcg/mips: Handle clz opcode

Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Handle ctz and clz opcodes

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/aarch64: Handle ctz and clz opcodes

Signed-off-by: Richard Henderson <[email protected]>

tcg/ppc: Handle ctz and clz opcodes

Signed-off-by: Richard Henderson <[email protected]>

target-i386: Use clz and ctz opcodes

Signed-off-by: Richard Henderson <[email protected]>

target-arm: Use clz opcode

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

target-xtensa: Use clz opcode

Signed-off-by: Richard Henderson <[email protected]>

target-unicore32: Use clz opcode

Signed-off-by: Richard Henderson <[email protected]>

target-tricore: Use clz opcode

Tested-by: Bastian Koppelmann <[email protected]>
Reviewed-by: Bastian Koppelmann <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

target-tilegx: Use clz and ctz opcodes

Signed-off-by: Richard Henderson <[email protected]>

target-s390x: Use clz opcode

Signed-off-by: Richard Henderson <[email protected]>

target-ppc: Use clz and ctz opcodes

Signed-off-by: Richard Henderson <[email protected]>

target-openrisc: Use clz and ctz opcodes

Signed-off-by: Richard Henderson <[email protected]>

target-mips: Use clz opcode

Signed-off-by: Richard Henderson <[email protected]>

target-microblaze: Use clz opcode

Signed-off-by: Richard Henderson <[email protected]>

target-cris: Use clz opcode

Signed-off-by: Richard Henderson <[email protected]>

target-alpha: Use the ctz and clz opcodes

Signed-off-by: Richard Henderson <[email protected]>

disas/ppc: Handle popcnt and cnttz

Signed-off-by: Richard Henderson <[email protected]>

disas/i386.c: Handle tzcnt

Signed-off-by: Richard Henderson <[email protected]>

tcg: Add clz and ctz opcodes

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Allow an operand to be matching or a constant

This allows an output operand to match an input operand
only when the input operand needs a register.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Pass the opcode width to target_parse_constraint

This will let us choose how to interpret a given constraint
depending on whether the opcode is 32- or 64-bit.  Which will
let us share more constraint combinations between opcodes.

At the same time, change the interface to return the advanced
pointer instead of passing it in/out by reference.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Transition flat op_defs array to a target callback

This will allow the target to tailor the constraints to the
auto-detected ISA extensions.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Add markup for output requires new register

This is the same concept as, and same markup as, the
early clobber markup in gcc.

Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/optimize: Fold movcond 0/1 into setcond

Signed-off-by: Richard Henderson <[email protected]>

target-s390x: Use the new deposit and extract ops

Use the new primitives for RISBG.

Signed-off-by: Richard Henderson <[email protected]>

target-ppc: Use the new deposit and extract ops

Use the new primitives for RDWINM and RLDICL.

Reviewed-by: David Gibson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

target-mips: Use the new extract op

Use extract for EXT and DEXT.

Reviewed-by: Yongbok Kim <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

target-i386: Use new deposit and extract ops

A couple of places where it was easy to identify a right-shift
followed by an extract or and-with-immediate, and the obvious
sign-extract from a high byte register.

Acked-by: Eduardo Habkost <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

target-arm: Use new deposit and extract ops

Use the new primitives for UBFX and SBFX.

Signed-off-by: Richard Henderson <[email protected]>

target-alpha: Use deposit and extract ops

Signed-off-by: Richard Henderson <[email protected]>

tcg/s390: Support deposit into zero

Since we can no longer use matching constraints, this does
mean we must handle that data movement by hand.

Signed-off-by: Richard Henderson <[email protected]>

tcg/s390: Implement field extraction opcodes

Signed-off-by: Richard Henderson <[email protected]>

tcg/s390: Expose host facilities to tcg-target.h

This lets us expose facilities to TCG_TARGET_HAS_* defines
directly, rather than hiding behind function calls.

Signed-off-by: Richard Henderson <[email protected]>

tcg/ppc: Implement field extraction opcodes

Reviewed-by: David Gibson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/mips: Implement field extraction opcodes

Signed-off-by: Richard Henderson <[email protected]>