trace: add build framework for merging trace-events files
Switch make rules over to use trace-events-all as the
master trace events input file. Add rule that will
construct trace-events-all from $(trace-events-y).
Lluís Vilanova [Thu, 9 Jun 2016 17:31:47 +0000 (19:31 +0200)]
trace: [all] Add "guest_mem_before" event
The event is described in "trace-events". Note that the "MO_AMASK" flag
is not traced, since it does not seem to affect the visible semantics of
instructions.
[s/inline inline/inline/ to fix clang build.
--Stefan]
Lluís Vilanova [Thu, 9 Jun 2016 17:31:41 +0000 (19:31 +0200)]
exec: [tcg] Track which vCPU is performing translation and execution
Information is tracked inside the TCGContext structure, and later used
by tracing events with the 'tcg' and 'vcpu' properties.
The 'cpu' field is used to check tracing of translation-time
events ("*_trans"). The 'tcg_env' field is used to pass it to
execution-time events ("*_exec").
Peter Maydell [Mon, 20 Jun 2016 11:53:35 +0000 (12:53 +0100)]
Merge remote-tracking branch 'remotes/otubo/tags/pull-seccomp-20160620' into staging
seccomp branch queue
# gpg: Signature made Mon 20 Jun 2016 10:06:59 BST
# gpg: using RSA key 0xFD0CFF5B12F8BD2F
# gpg: Good signature from "Eduardo Otubo (Software Engineer @ ProfitBricks) <[email protected]>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1C96 46B6 E1D1 C38A F2EC 3FDE FD0C FF5B 12F8 BD2F
* remotes/otubo/tags/pull-seccomp-20160620:
seccomp: Add support for ppc/ppc64
* remotes/pmaydell/tags/pull-target-arm-20160617: (22 commits)
ACPI: ARM: Present GIC version in MADT table
hw/timer: Add value matching support to aspeed_timer
target-arm/monitor.c: Advertise emulated GICv3 in capabilities
target-arm/machine.c: Allow user to request GICv3 emulation
hw/intc/arm_gicv3: Add IRQ handling CPU interface registers
hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers
hw/intc/arm_gicv3: Implement gicv3_cpuif_update()
hw/intc/arm_gicv3: Implement GICv3 CPU interface registers
hw/intc/arm_gicv3: Implement gicv3_set_irq()
hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions
hw/intc/arm_gicv3: Implement GICv3 redistributor registers
hw/intc/arm_gicv3: Implement GICv3 distributor registers
hw/intc/arm_gicv3: Implement functions to identify next pending irq
hw/intc/arm_gicv3: ARM GICv3 device framework
hw/intc/arm_gicv3: Add vmstate descriptors
hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure
hw/intc/arm_gicv3: Add state information
target-arm: Add mp-affinity property for ARM CPU class
target-arm: Provide hook to tell GICv3 about changes of security state
target-arm: Define new arm_is_el3_or_mon() function
...
Shannon Zhao [Fri, 17 Jun 2016 14:23:48 +0000 (15:23 +0100)]
ACPI: ARM: Present GIC version in MADT table
In ACPI 5.1 Errata, it adds GIC version in GIC distributor structure.
This is useful for guest kernel to identify which version GIC hardware
is. Update GIC distributor structure and present GIC version in MADT
table.
Peter Maydell [Fri, 17 Jun 2016 14:23:48 +0000 (15:23 +0100)]
target-arm/machine.c: Allow user to request GICv3 emulation
Now we have an emulated GICv3, remove the restriction in
gicv3_class_name() so that the user can request a GICv3 with
-machine gic-version=3 even when not using KVM.
Peter Maydell [Fri, 17 Jun 2016 14:23:47 +0000 (15:23 +0100)]
hw/intc/arm_gicv3: Implement gicv3_cpuif_update()
Implement the gicv3_cpuif_update() function which deals with correctly
asserting IRQ and FIQ based on the current running priority of the CPU,
the priority of the highest priority pending interrupt and the CPU's
current exception level and security state.
Peter Maydell [Fri, 17 Jun 2016 14:23:47 +0000 (15:23 +0100)]
hw/intc/arm_gicv3: Implement GICv3 CPU interface registers
Implement the CPU interface registers for the GICv3; these are
CPU system registers, not MMIO registers.
This commit implements all the registers which are simple
accessors for GIC state, but not those which act as interfaces
for acknowledging, dismissing or generating interrupts. (Those
will be added in a later commit.)
Signed-off-by: Shlomo Pongratz <[email protected]> Reviewed-by: Shannon Zhao <[email protected]> Tested-by: Shannon Zhao <[email protected]> Signed-off-by: Peter Maydell <[email protected]>
Message-id: 1465915112[email protected]
[PMM: significantly overhauled/rewritten:
* use the new data structures
* restructure register read/write to handle different width accesses
natively, since almost all registers are 32-bit only, rather
than implementing everything as byte accesses
* implemented security extension support
] Signed-off-by: Peter Maydell <[email protected]>
Signed-off-by: Shlomo Pongratz <[email protected]> Reviewed-by: Shannon Zhao <[email protected]> Tested-by: Shannon Zhao <[email protected]> Signed-off-by: Peter Maydell <[email protected]>
Message-id: 1465915112[email protected]
[PMM: significantly overhauled/rewritten:
* use the new bitmap data structures
* restructure register read/write to handle different width accesses
natively, since almost all registers are 32-bit only, rather
than implementing everything as byte accesses
* implemented security extension support
] Signed-off-by: Peter Maydell <[email protected]>
Peter Maydell [Fri, 17 Jun 2016 14:23:46 +0000 (15:23 +0100)]
hw/intc/arm_gicv3: Implement functions to identify next pending irq
Implement the GICv3 logic to recalculate the highest priority pending
interrupt for each CPU after some part of the GIC state has changed.
We avoid unnecessary full recalculation where possible.
Shlomo Pongratz [Fri, 17 Jun 2016 14:23:46 +0000 (15:23 +0100)]
hw/intc/arm_gicv3: ARM GICv3 device framework
This patch includes the device class itself, some ID register
value functions which will be needed by both distributor
and redistributor, and some skeleton functions for handling
interrupts coming in and going out, which will be filled in
in a subsequent patch.
Pavel Fedin [Fri, 17 Jun 2016 14:23:46 +0000 (15:23 +0100)]
hw/intc/arm_gicv3: Add vmstate descriptors
Add state structure descriptors for the GICv3 state. We mark
the KVM GICv3 device as having a migration blocker until the
code to save and restore the state in the kernel is implemented.
Peter Maydell [Fri, 17 Jun 2016 14:23:46 +0000 (15:23 +0100)]
hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure
Move the GICv3 parent_irq and parent_fiq pointers into the
GICv3CPUState structure rather than giving them their own array.
This will make it easy to assert the IRQ and FIQ lines for a
particular CPU interface without having to know or calculate
the CPU index for the GICv3CPUState we are working on.
Pavel Fedin [Fri, 17 Jun 2016 14:23:46 +0000 (15:23 +0100)]
hw/intc/arm_gicv3: Add state information
Add state information to GICv3 object structure and implement
arm_gicv3_common_reset().
This commit includes accessor functions for the fields which are
stored as bitmaps in uint32_t arrays.
Signed-off-by: Pavel Fedin <[email protected]> Reviewed-by: Shannon Zhao <[email protected]> Tested-by: Shannon Zhao <[email protected]> Signed-off-by: Peter Maydell <[email protected]>
Message-id: 1465915112[email protected]
[PMM: significantly overhauled:
* Add missing qom/cpu.h include
* Remove legacy-only state fields (we can add them later if/when we add
legacy emulation)
* Use arrays of uint32_t to store the various distributor bitmaps,
and provide accessor functions for the various set/test/etc operations
* Add various missing register offset #defines
* Accessor macros which combine distributor and redistributor behaviour
removed
* Fields in state structures renamed to match architectural register names
* Corrected the reset value for GICR_IENABLER0 since we don't support
legacy mode
* Added ARM_LINUX_BOOT_IF interface for "we are directly booting a kernel in
non-secure" so that we can fake up the firmware-mandated reconfiguration
only when we need it
] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Shannon Zhao <[email protected]>
Peter Maydell [Fri, 17 Jun 2016 14:23:46 +0000 (15:23 +0100)]
target-arm: Provide hook to tell GICv3 about changes of security state
The GICv3 CPU interface needs to know when the CPU it is attached
to makes an exception level or mode transition that changes the
security state, because whether it is asserting IRQ or FIQ can change
depending on these things. Provide a mechanism for letting the GICv3
device register a hook to be called on such changes.
Peter Maydell [Fri, 17 Jun 2016 14:23:45 +0000 (15:23 +0100)]
target-arm: Define new arm_is_el3_or_mon() function
The GICv3 system registers need to know if the CPU is AArch64
in EL3 or AArch32 in Monitor mode. This happens to be the first
part of the check for arm_is_secure(), so factor it out into a
new arm_is_el3_or_mon() function that the GIC can also use.
Peter Maydell [Fri, 17 Jun 2016 14:23:45 +0000 (15:23 +0100)]
bitops.h: Implement half-shuffle and half-unshuffle ops
A half-shuffle operation takes a word with zeros in the high half:
0000 0000 0000 0000 ABCD EFGH IJKL MNOP
and spreads the bits out so they are in every other bit of the word:
0A0B 0C0D 0E0F 0G0H 0I0J 0K0L 0M0N 0O0P
A half-unshuffle performs the reverse operation.
Provide functions in bitops.h which implement these operations
for 32-bit and 64-bit inputs, and add tests for them.
Peter Maydell [Fri, 17 Jun 2016 12:42:11 +0000 (13:42 +0100)]
nbd/client.c: Correct trace format string
The trace format string in nbd_send_request uses PRIu16 for
request->type, but request->type is a uint32_t. This provokes
compiler warnings on the OSX clang. Use PRIu32 instead.
Chao Peng [Thu, 16 Jun 2016 01:59:10 +0000 (09:59 +0800)]
vnc: Wrap vnc initialization code with CONFIG_VNC
commit f8c75b2486 (vnc: Initialization stubs) removed CONFIG_VNC in vl.c
code. However qemu_find_opts("vnc") is NULL when vnc is configured out.
Crash will happen in qemu_opts_foreach() before stub vnc_init_func() is
called. This patch add it back.
Eduardo Habkost [Thu, 28 Jan 2016 14:22:35 +0000 (12:22 -0200)]
qdev: Use GList for global properties
If the same GlobalProperty struct is registered twice, the list
entry gets corrupted, making tqe_next points to itself, and
qdev_prop_set_globals() gets stuck in a loop. The bug can be
easily reproduced by running:
$ qemu-system-x86_64 -rtc-td-hack -rtc-td-hack
Change global_props to use GList instead of queue.h, making the
code simpler and able to deal with properties being registered
twice.
Peter Maydell [Fri, 17 Jun 2016 13:09:46 +0000 (14:09 +0100)]
Merge remote-tracking branch 'remotes/amit-migration/tags/migration-for-2.7-5' into staging
Migration:
- many compression/decompression fixes
- trace improvements
- static checker fix for detecting size mismatch in unused fields
- fix VM save after snapshot
# gpg: Signature made Fri 17 Jun 2016 13:59:44 BST
# gpg: using RSA key 0xEB0B4DFC657EF670
# gpg: Good signature from "Amit Shah <[email protected]>"
# gpg: aka "Amit Shah <[email protected]>"
# gpg: aka "Amit Shah <[email protected]>"
# Primary key fingerprint: 48CA 3722 5FE7 F4A8 B337 2735 1E9A 3B5F 8540 83B6
# Subkey fingerprint: CC63 D332 AB8F 4617 4529 6534 EB0B 4DFC 657E F670
* remotes/amit-migration/tags/migration-for-2.7-5:
vmstate-static-checker: fix size mismatch detection in unused fields
migration: code clean up
migration: refine the decompression code
migration: refine the compression code
migration: protect the quit flag by lock
migration: refine ram_save_compressed_page
qemu-file: Fix qemu_put_compression_data flaw
migration: remove useless code
migration: Fix a potential issue
migration: Fix multi-thread compression bug
migration: fix inability to save VM after snapshot
migration: Trace improvements
migration: Don't use *_to_cpup() and cpu_to_*w()
Liang Li [Thu, 5 May 2016 07:32:59 +0000 (15:32 +0800)]
migration: code clean up
Use 'QemuMutex comp_done_lock' and 'QemuCond comp_done_cond' instead
of 'QemuMutex *comp_done_lock' and 'QemuCond comp_done_cond'. To keep
consistent with 'QemuMutex decomp_done_lock' and
'QemuCond comp_done_cond'.
Liang Li [Thu, 5 May 2016 07:32:56 +0000 (15:32 +0800)]
migration: protect the quit flag by lock
quit_comp_thread and quit_decomp_thread are accessed by several
thread, it's better to protect them with locks. We use a per
thread flag to replace the global one, and the new flag is protected
by a lock.
Liang Li [Thu, 5 May 2016 07:32:55 +0000 (15:32 +0800)]
migration: refine ram_save_compressed_page
Use qemu_put_compression_data to do the compression directly
instead of using do_compress_ram_page, avoid some data copy.
very small improvement, at the same time, add code to check
if the compression is successful.
Liang Li [Thu, 5 May 2016 07:32:54 +0000 (15:32 +0800)]
qemu-file: Fix qemu_put_compression_data flaw
Current qemu_put_compression_data can only work with no writable
QEMUFile, and can't work with the writable QEMUFile. But it does
not provide any measure to prevent users from using it with a
writable QEMUFile.
We should fix this flaw to make it works with writable QEMUFile.
Liang Li [Thu, 5 May 2016 07:32:52 +0000 (15:32 +0800)]
migration: Fix a potential issue
At the end of live migration and before vm_start() on the destination
side, we should make sure all the decompression tasks are finished, if
this can not be guaranteed, the VM may get the incorrect memory data,
or the updated memory may be overwritten by the decompression thread.
Add the code to fix this potential issue.
Liang Li [Thu, 5 May 2016 07:32:51 +0000 (15:32 +0800)]
migration: Fix multi-thread compression bug
Recently, a bug related to multiple thread compression feature for
live migration is reported. The destination side will be blocked
during live migration if there are heavy workload in host and
memory intensive workload in guest, this is most likely to happen
when there is one decompression thread.
Some parts of the decompression code are incorrect:
1. The main thread receives data from source side will enter a busy
loop to wait for a free decompression thread.
2. A lock is needed to protect the decomp_param[idx]->start, because
it is checked in the main thread and is updated in the decompression
thread.
Fix these two issues by following the code pattern for compression.
Denis V. Lunev [Wed, 15 Jun 2016 15:06:43 +0000 (18:06 +0300)]
migration: fix inability to save VM after snapshot
The following sequence of operations fails:
virsh start vm
virsh snapshot-create vm
virshh save vm --file file
with the following error
error: Failed to save domain vm to file
error: internal error: unable to execute QEMU command 'migrate':
There's a migration process in progress
The problem is that qemu_savevm_state() calls migrate_init() which sets
migration state to MIGRATION_STATUS_SETUP and never cleaned it up.
This patch do the job.
A couple of improvements to tracing that have come out of helping
people with migration problems:
* vmstate_n_elems trace the count/name - for when you have problems
getting array counts right
* vmstate_subsection_load_bad - add the idstr, for when you receive a
subsection you weren't expecting.
Peter Maydell [Fri, 10 Jun 2016 16:09:22 +0000 (17:09 +0100)]
migration: Don't use *_to_cpup() and cpu_to_*w()
The *_to_cpup() and cpu_to_*w() functions just compose a pointer
dereference with a byteswap. Instead use ld*_p() and st*_p(),
which handle potential pointer misalignment and avoid the need
to cast the pointer.
Peter Maydell [Fri, 17 Jun 2016 11:36:27 +0000 (12:36 +0100)]
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160617' into staging
ppc patch queue for 2016-06-17
Here's the current accumulated set of spapr, ppc and related patches.
* The big thing in here is CPU hotplug for spapr
- This includes a number of acked generic changes adding new
infrastructure for hotplugging cpu cores
* A number of TCG bug fixes are also included
* This adds a new testcase to make it harder to accidentally break
Macintosh (and other openbios) platforms
# gpg: Signature made Fri 17 Jun 2016 07:35:29 BST
# gpg: using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <[email protected]>"
# gpg: aka "David Gibson (Red Hat) <[email protected]>"
# gpg: aka "David Gibson (ozlabs.org) <[email protected]>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.7-20160617:
spapr: implement query-hotpluggable-cpus callback
hmp: Add 'info hotpluggable-cpus' HMP command
QMP: Add query-hotpluggable-cpus
spapr: CPU hot unplug support
spapr: CPU hotplug support
spapr: convert boot CPUs into CPU core devices
spapr: Move spapr_cpu_init() to spapr_cpu_core.c
spapr: Abstract CPU core device and type specific core devices
qom: API to get instance_size of a type
spapr_drc: Prevent detach racing against attach for CPU DR
xics,xics_kvm: Handle CPU unplug correctly
cpu: Abstract CPU core type
qdev: hotplug: Introduce HotplugHandler.pre_plug() callback
target-ppc: Fix rlwimi, rlwinm, rlwnm
vfio: Fix broken EEH
target-ppc: Bug in BookE wait instruction
ppc / sparc: Add a tester for checking whether OpenBIOS runs successfully
hw/ppc/spapr: Silence deprecation message in qtest mode
Peter Maydell [Fri, 17 Jun 2016 10:25:46 +0000 (11:25 +0100)]
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
pc, pci, virtio: new features, cleanups, fixes
Beginning of reconnect support for vhost-user.
Misc cleanups and fixes.
Signed-off-by: Michael S. Tsirkin <[email protected]>
# gpg: Signature made Fri 17 Jun 2016 01:28:39 BST
# gpg: using RSA key 0x281F0DB8D28D5469
# gpg: Good signature from "Michael S. Tsirkin <[email protected]>"
# gpg: aka "Michael S. Tsirkin <[email protected]>"
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* remotes/mst/tags/for_upstream:
MAINTAINERS: add Marcel to PCI
msi_init: change return value to 0 on success
fix some coding style problems
pci core: assert ENOSPC when add capability
test: start vhost-user reconnect test
tests: append i386 tests
vhost-net: save & restore vring enable state
vhost-net: save & restore vhost-user acked features
vhost-net: do not crash if backend is not present
vhost-user: disconnect on start failure
qemu-char: add qemu_chr_disconnect to close a fd accepted by listen fd
tests/vhost-user-bridge: workaround stale vring base
tests/vhost-user-bridge: add client mode
vhost-user: add ability to know vhost-user backend disconnection
pci: fix pci_requester_id()
Signed-off-by: Peter Maydell <[email protected]>
Conflicts:
tests/Makefile.include
Igor Mammedov [Fri, 10 Jun 2016 00:59:06 +0000 (06:29 +0530)]
QMP: Add query-hotpluggable-cpus
It will allow mgmt to query present and hotpluggable CPU objects,
it is required from a target platform that wishes to support command
to implement and set MachineClass.query_hotpluggable_cpus callback,
which will return a list of possible CPU objects with options that
would be needed for hotplugging possible CPU objects.
There are:
'type': 'str' - QOM CPU object type for usage with device_add
'vcpus-count': 'int' - number of logical VCPU threads per
CPU object (mgmt needs to know)
and a set of optional fields that are to used for hotplugging a CPU
objects and would allows mgmt tools to know what/where it could be
hotplugged;
[node],[socket],[core],[thread]
For present CPUs there is a 'qom-path' field which would allow mgmt to
inspect whatever object/abstraction the target platform considers
as CPU object.
Bharata B Rao [Fri, 10 Jun 2016 00:59:05 +0000 (06:29 +0530)]
spapr: CPU hot unplug support
Remove the CPU core device by removing the underlying CPU thread devices.
Hot removal of CPU for sPAPR guests is achieved by sending the hot unplug
notification to the guest. Release the vCPU object after CPU hot unplug so
that vCPU fd can be parked and reused.
Bharata B Rao [Fri, 10 Jun 2016 00:59:04 +0000 (06:29 +0530)]
spapr: CPU hotplug support
Set up device tree entries for the hotplugged CPU core and use the
exising RTAS event logging infrastructure to send CPU hotplug notification
to the guest.
Bharata B Rao [Fri, 10 Jun 2016 00:59:03 +0000 (06:29 +0530)]
spapr: convert boot CPUs into CPU core devices
Introduce sPAPRMachineClass.dr_cpu_enabled to indicate support for
CPU core hotplug. Initialize boot time CPUs as core deivces and prevent
topologies that result in partially filled cores. Both of these are done
only if CPU core hotplug is supported.
Note: An unrelated change in the call to xics_system_init() is done
in this patch as it makes sense to use the local variable smt introduced
in this patch instead of kvmppc_smt_threads() call here.
TODO: We derive sPAPR core type by looking at -cpu <model>. However
we don't take care of "compat=" feature yet for boot time as well
as hotplug CPUs.
Bharata B Rao [Fri, 10 Jun 2016 00:59:02 +0000 (06:29 +0530)]
spapr: Move spapr_cpu_init() to spapr_cpu_core.c
Start consolidating CPU init related routines in spapr_cpu_core.c. As
part of this, move spapr_cpu_init() and its dependencies from spapr.c
to spapr_cpu_core.c
No functionality change in this patch.
Signed-off-by: Bharata B Rao <[email protected]>
[dwg: Rename TIMEBASE_FREQ to SPAPR_TIMEBASE_FREQ, since it's now in a
public(ish) header] Signed-off-by: David Gibson <[email protected]>
Bharata B Rao [Fri, 10 Jun 2016 00:59:01 +0000 (06:29 +0530)]
spapr: Abstract CPU core device and type specific core devices
Add sPAPR specific abastract CPU core device that is based on generic
CPU core device. Use this as base type to create sPAPR CPU specific core
devices.
TODO:
- Add core types for other remaining CPU types
- Handle CPU model alias correctly
Bharata B Rao [Thu, 12 May 2016 03:48:21 +0000 (09:18 +0530)]
spapr_drc: Prevent detach racing against attach for CPU DR
If a CPU is hot removed while hotplug of the same is still in progress,
the guest crashes. Prevent this by ensuring that detach is done only
after attach has completed.
The existing code already prevents such race for PCI hotplug. However
given that CPU is a logical DR unlike PCI and starts with ISOLATED
state, we need a logic that works for CPU too.
Bharata B Rao [Thu, 12 May 2016 03:48:20 +0000 (09:18 +0530)]
xics,xics_kvm: Handle CPU unplug correctly
XICS is setup for each CPU during initialization. Provide a routine
to undo the same when CPU is unplugged. While here, move ss->cs management
into xics from xics_kvm since there is nothing KVM specific in it.
Also ensure xics reset doesn't set irq for CPUs that are already unplugged.
This allows reboot of a VM that has undergone CPU hotplug and unplug
to work correctly.
Gavin Shan [Wed, 15 Jun 2016 04:28:27 +0000 (14:28 +1000)]
vfio: Fix broken EEH
vfio_eeh_container_op() is the backend that communicates with
host kernel to support EEH functionality in QEMU. However, the
functon should return the value from host kernel instead of 0
unconditionally.
dwg: Specifically the problem occurs for the handful of EEH
sub-operations which can return a non-zero, non-error result.
Thomas Huth [Tue, 14 Jun 2016 13:57:56 +0000 (15:57 +0200)]
ppc / sparc: Add a tester for checking whether OpenBIOS runs successfully
Since the mac99 and g3beige PowerPC machines recently broke without
being noticed, it would be good to have a tester for "make check"
that detects such issues immediately. A simple way to test the firmware
of these machines is to use the "-prom-env" parameter of QEMU. This
parameter can be used to put some Forth code into the 'boot-command'
firmware variable which then can signal success to the tester by
writing a magic value to a known memory location. And since some of the
Sparc machines are also using OpenBIOS, they are now tested with this
prom-env-tester, too.
Reviewed-by: Markus Armbruster <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
[dwg: Removed sparc64, because it trips a TCG bug on 32-bit hosts] Signed-off-by: David Gibson <[email protected]>
projects / qemu.git / log