Peter Maydell [Mon, 29 Feb 2016 11:49:50 +0000 (11:49 +0000)]
Merge remote-tracking branch 'remotes/kraxel/tags/pull-ui-20160229-1' into staging
ui: spice dmabuf fix, MAINTAINERS updates.
# gpg: Signature made Mon 29 Feb 2016 10:41:15 GMT using RSA key ID D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <[email protected]>"
# gpg: aka "Gerd Hoffmann <[email protected]>"
# gpg: aka "Gerd Hoffmann (private) <[email protected]>"
* remotes/kraxel/tags/pull-ui-20160229-1:
MAINTAINERS: Add an entry for the include/ui/ folder
MAINTAINERS: Add spice-display.h to the SPICE section
spice/gl: Enable dmabuf only for spice >= 0.13.1
Peter Maydell [Mon, 29 Feb 2016 10:51:11 +0000 (10:51 +0000)]
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160229' into staging
ppc patch queue for 2016-02-29
Some more accumulated patches for target-ppc, pseries machine type and
related devices to fit in before the qemu-2.6 soft freeze.
* Mostly bugfixes and small cleanups for spapr and Mac platforms
# gpg: Signature made Mon 29 Feb 2016 06:56:34 GMT using RSA key ID 20D9B392
# gpg: Good signature from "David Gibson <[email protected]>"
# gpg: aka "David Gibson (Red Hat) <[email protected]>"
# gpg: aka "David Gibson (ozlabs.org) <[email protected]>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.6-20160229:
xics: report errors with the QEMU Error API
migration: allow machine to enforce configuration section migration
spapr: skip configuration section during migration of older machines
dbdma: warn when using unassigned channel
spapr: disable vmdesc submission for old machines
spapr_pci: fix irq leak in RTAS ibm,change-msi
spapr_pci: kill useless variable in rtas_ibm_change_msi()
spapr_rng: disable hotpluggability
Michal Privoznik [Wed, 24 Feb 2016 12:42:18 +0000 (13:42 +0100)]
spice/gl: Enable dmabuf only for spice >= 0.13.1
After 474114b7 the dmabuf feature is enabled whenever spice
greater than or equal to spice 0.13.0 is found. This is because
two new functions are required: spice_qxl_gl_scanout and
spice_qxl_gl_draw_async. These were, however, introduce in 0.13.1
release. Well, technically they haven't been released yet, but
for sure they are not going to be part of 0.13.0 release (for the
ABI stability sake).
Greg Kurz [Fri, 26 Feb 2016 09:44:07 +0000 (10:44 +0100)]
xics: report errors with the QEMU Error API
Using the return value to report errors is error prone:
- xics_alloc() returns -1 on error but spapr_vio_busdev_realize() errors
on 0
- xics_alloc_block() returns the unclear value of ics->offset - 1 on error
but both rtas_ibm_change_msi() and spapr_phb_realize() error on 0
This patch adds an errp argument to xics_alloc() and xics_alloc_block() to
report errors. The return value of these functions is a valid IRQ number
if errp is NULL. It is undefined otherwise.
The corresponding error traces get promotted to error messages. Note that
the "can't allocate IRQ" error message in spapr_vio_busdev_realize() also
moves to xics_alloc(). Similar error message consolidation isn't really
applicable to xics_alloc_block() because callers have extra context (device
config address, MSI or MSIX).
Greg Kurz [Thu, 18 Feb 2016 11:32:25 +0000 (12:32 +0100)]
migration: allow machine to enforce configuration section migration
Migration of pseries-2.3 doesn't have configuration section. Unfortunately,
QEMU 2.4/2.4.1/2.5 are buggy and always stream and expect the configuration
section, and break migration both ways.
This patch introduces a property which allows to enforce a configuration
section for machines who don't have one.
It can be set at startup:
-machine enforce-config-section=on
or later from the QEMU monitor:
qom-set /machine enforce-config-section on
It is up to the tooling to set or unset this property according to the
version of the QEMU at the other end of the pipe.
Greg Kurz [Thu, 18 Feb 2016 11:32:18 +0000 (12:32 +0100)]
spapr: skip configuration section during migration of older machines
Since QEMU 2.4, we have a configuration section in the migration stream.
This must be skipped for older machines, like it is already done for x86.
This patch fixes the migration of pseries-2.3 from/to QEMU 2.3, but it
breaks migration of the same machine from/to QEMU 2.4/2.4.1/2.5. We do
that anyway because QEMU 2.3 is likely to be more widely deployed than
newer QEMU versions.
Greg Kurz [Tue, 23 Feb 2016 16:47:59 +0000 (17:47 +0100)]
spapr: disable vmdesc submission for old machines
Since QEMU 2.3, we have a vmdesc section in the migration stream.
This section is not mandatory but when migrating a pseries-2.2
machine from QEMU 2.2, you get a warning at the destination:
qemu-system-ppc64: Expected vmdescription section, but got 0
The warning goes away if we decide to skip vmdesc as well for
older pseries, like it is already done for pc's.
This can only be observed with -cpu POWER7 because POWER8
cannot migrate from QEMU 2.2 to 2.3 (insns_flags2 mismatch).
Greg Kurz [Thu, 25 Feb 2016 18:02:18 +0000 (19:02 +0100)]
spapr_pci: fix irq leak in RTAS ibm,change-msi
This RTAS call is used to request new interrupts or to free all interrupts.
If the driver has already allocated interrupts and asks again for a non-null
number of irqs, then the rtas_ibm_change_msi() function will silently leak
the previous interrupts.
It happens because xics_free() is only called when the driver releases all
interrupts (!req_num case). Note that the previously allocated spapr_pci_msi
is not leaked because the GHashTable is created with destroy functions and
g_hash_table_insert() hence frees the old value.
This patch makes sure any previously allocated MSIs are released when a
new allocation succeeds.
This happens because spapr_rng isn't plugged to any bus and sPAPR does
not provide hotplug support for it: qdev_get_hotplug_handler() hence
return NULL and we hit the assertion.
And anyway, it doesn't make much sense to unplug this device since hcalls
cannot be unregistered. Even the idea of hotplugging a RNG device instead
of declaring it on the QEMU command line looks weird.
This patch simply disables hotpluggability for the spapr-rng class.
Peter Maydell [Fri, 26 Feb 2016 16:02:00 +0000 (16:02 +0000)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160226' into staging
target-arm queue:
* Clean up handling of bad mode switches writing to CPSR, and implement
the ARMv8 requirement that they set PSTATE.IL
* Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps on perf monitor
register accesses
* Don't implement stellaris-pl061-only registers on generic-pl061
* Fix SD card handling for raspi
* Add missing include files to MAINTAINERS
* Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW
* Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
* remotes/pmaydell/tags/pull-target-arm-20160226:
target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW
sdhci: add quirk property for card insert interrupt status on Raspberry Pi
sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts"
MAINTAINERS: Add some missing ARM related header files
raspi: fix SD card with recent sdhci changes
ARM: PL061: Checking register r/w accesses to reserved area
target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps
target-arm: Fix handling of SDCR for 32-bit code
target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1
target-arm: Make mode switches from Hyp via CPS and MRS illegal
target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL
target-arm: Forbid mode switch to Mon from Secure EL1
target-arm: Add Hyp mode checks to bad_mode_switch()
target-arm: Add comment about not implementing NSACR.RFR
target-arm: In cpsr_write() ignore mode switches from User mode
linux-user: Use restrictive mask when calling cpsr_write()
target-arm: Raw CPSR writes should skip checks and bank switching
target-arm: Add write_type argument to cpsr_write()
target-arm: Give CPSR setting on 32-bit exception return its own helper
* remotes/amit-migration/tags/migration-for-2.6-5:
migration (postcopy): move bdrv_invalidate_cache_all of of coroutine context
migration (ordinary): move bdrv_invalidate_cache_all of of coroutine context
migration/vmstate: document VMStateFlags
MAINTAINERS: Add docs/migration.txt to the "Migration" section
migration/postcopy-ram: Guard use of sys/eventfd.h with CONFIG_EVENTFD
migration: reorder code to make it symmetric
Denis V. Lunev [Wed, 24 Feb 2016 08:53:39 +0000 (11:53 +0300)]
migration (postcopy): move bdrv_invalidate_cache_all of of coroutine context
There is a possibility to hit an assert in qcow2_get_specific_info that
s->qcow_version is undefined. This happens when VM in starting from
suspended state, i.e. it processes incoming migration, and in the same
time 'info block' is called.
The problem is that qcow2_invalidate_cache() closes the image and
memset()s BDRVQcowState in the middle.
The patch moves processing of bdrv_invalidate_cache_all out of
coroutine context for postcopy migration to avoid that. This function
is called with the following stack:
process_incoming_migration_co
qemu_loadvm_state
qemu_loadvm_state_main
loadvm_process_command
loadvm_postcopy_handle_run
Denis V. Lunev [Wed, 24 Feb 2016 08:53:38 +0000 (11:53 +0300)]
migration (ordinary): move bdrv_invalidate_cache_all of of coroutine context
There is a possibility to hit an assert in qcow2_get_specific_info that
s->qcow_version is undefined. This happens when VM in starting from
suspended state, i.e. it processes incoming migration, and in the same
time 'info block' is called.
The problem is that qcow2_invalidate_cache() closes the image and
memset()s BDRVQcowState in the middle.
The patch moves processing of bdrv_invalidate_cache_all out of
coroutine context for standard migration to avoid that.
Peter Maydell [Fri, 19 Feb 2016 14:07:43 +0000 (14:07 +0000)]
target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
The v8 ARM ARM defines that unused spaces in the ID_AA64* system
register ranges are Reserved and must RAZ, rather than being UNDEF.
Implement this.
In particular, ARM v8.2 adds a new feature register ID_AA64MMFR2,
and newer versions of the Linux kernel will attempt to read this,
which causes them not to boot up on versions of QEMU missing this fix.
Since the encoding .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6
is actually defined in ARMv8 (as ID_MMFR4), we give it an entry in
the ARMCPU struct so CPUs can override it, though since none do
this too will just RAZ.
Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW due to the register not
having any underlying state. This fixes an issue with booting
KVM enabled kernels when EL2 is on.
Andrew Baumann [Thu, 25 Feb 2016 21:35:30 +0000 (13:35 -0800)]
sdhci: add quirk property for card insert interrupt status on Raspberry Pi
This quirk is a workaround for the following hardware behaviour, on
which UEFI (specifically, the bootloader for Windows on Pi2) depends:
1. at boot with an SD card present, the interrupt status/enable
registers are initially zero
2. upon enabling it in the interrupt enable register, the card insert
bit in the interrupt status register is immediately set
3. after a subsequent controller reset, the card insert interrupt does
not fire, even if enabled in the interrupt enable register
This change was poorly tested on my part. It squelched card insertion
interrupts on reset, but that was not necessary because sdhci_reset()
clears all the registers (via the call to memset), so the subsequent
sdhci_insert_eject_cb() call never sees the card insert interrupt
enabled. However, not calling the insert_eject_cb results in prnsts
remaining 0, when it actually needs to be updated to indicate card
presence and R/O status.
Wei Huang [Thu, 18 Feb 2016 16:56:20 +0000 (11:56 -0500)]
ARM: PL061: Checking register r/w accesses to reserved area
pl061.c emulates two GPIO devices, ARM PL061 and TI Stellaris, which
share the same read/write functions (pl061_read and pl061_write).
However PL061 and Stellaris have different GPIO register definitions
and pl061_read()/pl061_write() doesn't check it. This patch enforces
checking on offset, preventing R/W into the reserved memory area.
Peter Maydell [Fri, 19 Feb 2016 14:39:44 +0000 (14:39 +0000)]
target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps
Implement the performance monitor register traps controlled
by MDCR_EL3.TPM and MDCR_EL2.TPM. Most of the performance
registers already have an access function to deal with the
user-enable bit, and the TPM checks can be added there. We
also need a new access function which only implements the
TPM checks for use by the few not-EL0-accessible registers
and by PMUSERENR_EL0 (which is always EL0-readable).
Peter Maydell [Fri, 19 Feb 2016 14:39:43 +0000 (14:39 +0000)]
target-arm: Fix handling of SDCR for 32-bit code
Fix two issues with our implementation of the SDCR:
* it is only present from ARMv8 onwards
* it does not contain several of the trap bits present in its 64-bit
counterpart the MDCR_EL3
Put the register description in the right place so that it does not
get enabled for ARMv7 and earlier, and give it a write function so that
we can mask out the bits which should not be allowed to have an effect
if EL3 is 32-bit.
Peter Maydell [Tue, 23 Feb 2016 15:36:44 +0000 (15:36 +0000)]
target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1
If HCR.TGE is 1 then mode changes via CPS and MSR from Monitor to
NonSecure PL1 modes are illegal mode changes. Implement this check
in bad_mode_switch().
(We don't currently implement HCR.TGE, but this is the only missing
check from the v8 ARM ARM G1.9.3 and so it's worth adding now; the
rest of the HCR.TGE checks can be added later as necessary.)
Peter Maydell [Tue, 23 Feb 2016 15:36:44 +0000 (15:36 +0000)]
target-arm: Make mode switches from Hyp via CPS and MRS illegal
Mode switches from Hyp to any other mode via the CPS and MRS
instructions are illegal mode switches (though obviously switching
via exception return is valid). Add this check to bad_mode_switch().
Peter Maydell [Tue, 23 Feb 2016 15:36:44 +0000 (15:36 +0000)]
target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL
In v8, the illegal mode changes which are UNPREDICTABLE in v7 are
given architected behaviour:
* the mode field is unchanged
* PSTATE.IL is set (so any subsequent instructions will UNDEF)
* any other CPSR fields are written to as normal
This is pretty much the same behaviour we picked for our
UNPREDICTABLE handling, with the exception that for v8 we
need to set the IL bit.
Peter Maydell [Tue, 23 Feb 2016 15:36:44 +0000 (15:36 +0000)]
target-arm: Forbid mode switch to Mon from Secure EL1
In v8 trying to switch mode to Mon from Secure EL1 is an
illegal mode switch. (In v7 this is impossible as all secure
modes except User are at EL3.) We can handle this case by
making a switch to Mon valid only if the current EL is 3,
which then gives the correct answer whether EL3 is AArch32
or AArch64.
Peter Maydell [Tue, 23 Feb 2016 15:36:44 +0000 (15:36 +0000)]
target-arm: Add comment about not implementing NSACR.RFR
QEMU doesn't implement the NSACR.RFR bit, which is a permitted
IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8.
Add a comment to bad_mode_switch() to note that this is why
FIQ is always a valid mode regardless of the CPU's Secure state.
Peter Maydell [Tue, 23 Feb 2016 15:36:43 +0000 (15:36 +0000)]
target-arm: In cpsr_write() ignore mode switches from User mode
The only case where we can attempt a cpsr_write() mode switch from
User is from the gdbstub; all other cases are handled in the
calling code (notably translate.c). Architecturally attempts to
alter the mode bits from user mode are simply ignored (and not
treated as a bad mode switch, which in v8 sets CPSR.IL). Make
mode switches from User ignored in cpsr_write() as well, for
consistency.
Peter Maydell [Tue, 23 Feb 2016 15:36:43 +0000 (15:36 +0000)]
linux-user: Use restrictive mask when calling cpsr_write()
When linux-user code is calling cpsr_write(), use a restrictive
mask to ensure we are limiting the set of CPSR bits we update.
In particular, don't allow the mode bits to be changed.
Peter Maydell [Tue, 23 Feb 2016 15:36:43 +0000 (15:36 +0000)]
target-arm: Raw CPSR writes should skip checks and bank switching
Raw CPSR writes should skip the architectural checks for whether
we're allowed to set the A or F bits and should also not do
the switching of register banks if the mode changes. Handle
this inside cpsr_write(), which allows us to drop the "manually
set the mode bits to avoid the bank switch" code from all the
callsites which are using CPSRWriteRaw.
This fixes a bug in 32-bit KVM handling where we had forgotten
the "manually set the mode bits" part and could thus potentially
trash the register state if the mode from the last exit to userspace
differed from the mode on this exit.
Peter Maydell [Tue, 23 Feb 2016 15:36:43 +0000 (15:36 +0000)]
target-arm: Add write_type argument to cpsr_write()
Add an argument to cpsr_write() to indicate what kind of CPSR
write is being requested, since the exact behaviour should
differ for the different cases.
Peter Maydell [Tue, 23 Feb 2016 15:36:43 +0000 (15:36 +0000)]
target-arm: Give CPSR setting on 32-bit exception return its own helper
The rules for setting the CPSR on a 32-bit exception return are
subtly different from those for setting the CPSR via an instruction
like MSR or CPS. (In particular, in Hyp mode changing the mode bits
is not valid via MSR or CPS.) Split the exception-return case into
its own helper for setting CPSR, so we can eventually handle them
differently in the helper function.
Matthew Fortune [Tue, 23 Feb 2016 16:09:15 +0000 (16:09 +0000)]
migration/postcopy-ram: Guard use of sys/eventfd.h with CONFIG_EVENTFD
sys/eventfd.h was being guarded only by a check for linux but does
not exist on older distributions like CentOS 5. Move the include
into the code that uses it and add an appropriate guard.
Wei Yang [Thu, 4 Feb 2016 22:50:30 +0000 (22:50 +0000)]
migration: reorder code to make it symmetric
In qemu_savevm_state_complete_precopy(), it iterates on each device to add
a json object and transfer related status to destination, while the order
of the last two steps could be refined.
Yongbok Kim [Wed, 3 Feb 2016 12:31:07 +0000 (12:31 +0000)]
target-mips: implement R6 multi-threading
MIPS Release 6 provides multi-threading features which replace
pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new
CP0.Config5.VP (Virtual Processor) bit which indicates presence of
multi-threading support which includes CP0.GlobalNumber register and
DVP/EVP instructions.
James Hogan [Wed, 3 Feb 2016 17:16:53 +0000 (17:16 +0000)]
mips/kvm: Support MSA in MIPS KVM guests
Support the new KVM_CAP_MIPS_MSA capability, which allows MIPS SIMD
Architecture (MSA) to be exposed to the KVM guest.
The capability is enabled if the guest core has MSA according to its
Config3 register. Various config bits are now writeable so that KVM is
aware of the configuration (Config3.MSAP) and so that QEMU can
save/restore the guest modifiable bits (Config5.MSAEn). The MSACSR/MSAIR
registers and the MSA vector registers are now saved/restored. Since the
FP registers are a subset of the vector registers, they are omitted if
the guest has MSA.
James Hogan [Wed, 3 Feb 2016 17:16:52 +0000 (17:16 +0000)]
mips/kvm: Support FPU in MIPS KVM guests
Support the new KVM_CAP_MIPS_FPU capability, which allows the host's FPU
to be exposed to the KVM guest.
The capability is enabled if the guest core has an FPU according to its
Config1 register. Various config bits are now writeable so that KVM is
aware of the configuration (Config1.FP) and so that QEMU can
save/restore the guest modifiable bits (Config5.FRE, Config5.UFR,
Config5.UFE). The FCSR/FIR registers and the floating point registers
are now saved/restored (depending on the FR mode bit).
James Hogan [Wed, 3 Feb 2016 17:16:51 +0000 (17:16 +0000)]
mips/kvm: Support signed 64-bit KVM registers
Rename kvm_mips_{get,put}_one_reg64() to kvm_mips_{get,put}_one_ureg64()
since they take an int64_t pointer, and add separate signed 64-bit
accessors. These will be used for double precision floating point
registers.
James Hogan [Wed, 3 Feb 2016 17:16:50 +0000 (17:16 +0000)]
mips/kvm: Support unsigned KVM registers
Add KVM register access functions for the uint32_t type. This is
required for FP and MSA control registers, which are represented as
unsigned 32-bit integers.
James Hogan [Wed, 3 Feb 2016 17:16:49 +0000 (17:16 +0000)]
mips/kvm: Implement Config CP0 registers
Implement saving and restoring to KVM state of the Config CP0 registers
(namely Config, Config1, Config2, Config3, Config4, and Config5). These
control the features available to a guest, and a few of the fields will
soon be writeable by a guest so QEMU needs to know about them so as not
to clobber them on migration/savevm.
James Hogan [Wed, 3 Feb 2016 17:16:48 +0000 (17:16 +0000)]
mips/kvm: Implement PRid CP0 register
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
James Hogan [Wed, 3 Feb 2016 17:16:47 +0000 (17:16 +0000)]
mips/kvm: Remove a couple of noisy DPRINTFs
The DPRINTFs in cpu_mips_io_interrupts_pending() and kvm_arch_pre_run()
are particularly noisy during normal execution, and also not
particularly helpful. Remove them so that more important debug messages
can be more easily seen.
Peter Maydell [Thu, 25 Feb 2016 17:33:19 +0000 (17:33 +0000)]
Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2016-02-25-tag' into staging
qemu-ga patch queue for 2.6
* fix w32 build breakage when VSS enabled
* fix up wchar handling in guest-set-user-password
* fix re-install handling for w32 MSI installer
* add w32 support for guest-get-vcpus
* add support for enums in guest-file-seek SEEK params
instead of relying on platform-specific integer values
* remotes/mdroth/tags/qga-pull-2016-02-25-tag:
qga: fix w32 breakage due to missing osdep.h includes
qga: check utf8-to-utf16 conversion
qga: fix off-by-one length check
qga: use wide-chars constants for wchar_t comparisons
qga: use size_t for wcslen() return value
qga: use more idiomatic qemu-style eol operators
qga: implement the guest-get-vcpus for windows
qemu-ga: Fixed minor version switch issue
qga: Support enum names in guest-file-seek
Michael Roth [Thu, 25 Feb 2016 00:14:52 +0000 (18:14 -0600)]
qga: fix w32 breakage due to missing osdep.h includes
requester.h relied on qemu/compiler.h definitions to
handle GCC_FMT_ATTR() stub, but this include was removed as part
of scripted clean-ups via 30456d5:
all: Clean up includes
under the assumption that all C files would have included it via
qemu/osdep.h at that point. requester.cpp was likely missed
due to C++ files requiring manual/special handling as well as
VSS build options needing to be enabled to trigger build failures.
Fix this by including qemu/osdep.h. That in turn pulls in a
macro from qapi/error.h that conflicts with a struct field name
in requester.h, so fix that as well by renaming the field.
While we're at it, fix up provider.cpp/install.cpp to include
osdep.h as well.
Laszlo Ersek said: "The length check is off by one (in the safe direction); it
should be (nchars >= 2). The processing should be active for the wide string
L"\r\n" -- resulting in the empty wide string --, I believe."
Gal Hammer [Mon, 2 Nov 2015 14:49:48 +0000 (16:49 +0200)]
qga: implement the guest-get-vcpus for windows
Signed-off-by: Gal Hammer <[email protected]> Reviewed-by: Michael Roth <[email protected]>
* report rather than assert when VCPU count == 0
* fix up subject: s/set-vcpus/get-vcpus/ Signed-off-by: Michael Roth <[email protected]>
Leonid Bloch [Mon, 11 Jan 2016 09:12:41 +0000 (11:12 +0200)]
qemu-ga: Fixed minor version switch issue
With automatically generated GUID, on minor version changes, an error
occurred, stating that there is a problem with the installer.
Now, a notification is shown, warning the user that another version of
this product is already installed, and that configuration or removal of
the existing version is possible through Add/Remove Programs on the
Control Panel (expected behavior).
Eric Blake [Tue, 9 Feb 2016 21:27:16 +0000 (14:27 -0700)]
qga: Support enum names in guest-file-seek
Magic constants are a pain to use, especially when we run the
risk that our choice of '1' for QGA_SEEK_CUR might differ from
the host or guest's choice of SEEK_CUR. Better is to use an
enum value, via a qapi alternate type for back-compatibility.
With this,
{"command":"guest-file-seek", "arguments":{"handle":1,
"offset":0, "whence":"cur"}}
becomes a synonym for the older
{"command":"guest-file-seek", "arguments":{"handle":1,
"offset":0, "whence":1}}
Peter Maydell [Thu, 25 Feb 2016 15:30:57 +0000 (15:30 +0000)]
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* Asynchronous dump-guest-memory from Peter
* improved logging with -D -daemonize from Dimitris
* more address_space_* optimization from Gonglei
* TCG xsave/xrstor thinko fix
* chardev bugfix and documentation patch
# gpg: Signature made Thu 25 Feb 2016 15:12:27 GMT using RSA key ID 78C7AE83
# gpg: Good signature from "Paolo Bonzini <[email protected]>"
# gpg: aka "Paolo Bonzini <[email protected]>"
* remotes/bonzini/tags/for-upstream:
target-i386: fix confusion in xcr0 bit position vs. mask
chardev: Properly initialize ChardevCommon components
memory: Remove unreachable return statement
memory: optimize qemu_get_ram_ptr and qemu_ram_ptr_length
exec: store RAMBlock pointer into memory region
log: Redirect stderr to logfile if deamonized
dump-guest-memory: add qmp event DUMP_COMPLETED
Dump: add hmp command "info dump"
Dump: add qmp command "query-dump"
DumpState: adding total_size and written_size fields
dump-guest-memory: add "detach" support
dump-guest-memory: disable dump when in INMIGRATE state
dump-guest-memory: introduce dump_process() helper function.
dump-guest-memory: add dump_in_progress() helper function
dump-guest-memory: using static DumpState, add DumpStatus
dump-guest-memory: add "detach" flag for QMP/HMP interfaces.
dump-guest-memory: cleanup: removing dump_{error|cleanup}().
scripts/kvm/kvm_stat: Fix missing right parantheses and ".format(...)"
qemu-options.hx: Improve documentation of chardev multiplexing mode
Paolo Bonzini [Wed, 17 Feb 2016 09:54:53 +0000 (10:54 +0100)]
target-i386: fix confusion in xcr0 bit position vs. mask
The xsave and xrstor helpers are accessing the x86_ext_save_areas array
using a bit mask instead of a bit position. Provide two sets of XSTATE_*
definitions and use XSTATE_*_BIT when a bit position is requested.
Commit d0d7708b forgot to parse logging for spice chardevs and
virtual consoles. This requires making qemu_chr_parse_common()
non-static. While at it, use a temporary variable to make the
code shorter, as well as reduce the churn when a later patch
alters the layout of simple unions.
Gonglei [Sat, 20 Feb 2016 02:35:20 +0000 (10:35 +0800)]
memory: optimize qemu_get_ram_ptr and qemu_ram_ptr_length
these two functions consume too much cpu overhead to
find the RAMBlock by ram address.
After this patch, we can pass the RAMBlock pointer
to them so that they don't need to find the RAMBlock
anymore most of the time. We can get better performance
in address translation processing.
Gonglei [Mon, 22 Feb 2016 08:34:55 +0000 (16:34 +0800)]
exec: store RAMBlock pointer into memory region
Each RAM memory region has a unique corresponding RAMBlock.
In the current realization, the memory region only stored
the ram_addr which means the offset of RAM address space,
We need to qurey the global ram.list to find the ram block
by ram_addr if we want to get the ram block, which is very
expensive.
Now, we store the RAMBlock pointer into memory region
structure. So, if we know the mr, we can easily get the
RAMBlock.
Peter Maydell [Thu, 25 Feb 2016 12:13:49 +0000 (12:13 +0000)]
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
vhost, virtio, pci, pc
Fixes all over the place.
virtio dataplane migration support.
Old q35 machine types removed.
Signed-off-by: Michael S. Tsirkin <[email protected]>
# gpg: Signature made Thu 25 Feb 2016 11:16:46 GMT using RSA key ID D28D5469
# gpg: Good signature from "Michael S. Tsirkin <[email protected]>"
# gpg: aka "Michael S. Tsirkin <[email protected]>"
* remotes/mst/tags/for_upstream: (21 commits)
q35: No need to check gigabyte_align
q35: Remove unused q35-acpi-dsdt.aml file
ich9: Remove enable_tco arguments from init functions
machine: Remove no_tco field
q35: Remove old machine versions
tests/vhost-user-bridge: fix build on 32 bit systems
vring: remove
virtio-scsi: do not use vring in dataplane
virtio-blk: do not use vring in dataplane
virtio-blk: fix "disabled data plane" mode
virtio: export vring_notify as virtio_should_notify
virtio: add AioContext-specific function for host notifiers
vring: make vring_enable_notification return void
block-migration: acquire AioContext as necessary
pci core: function pci_bus_init() cleanup
pci core: function pci_host_bus_register() cleanup
balloon: Use only 'pc-dimm' type dimm for ballooning
virtio-balloon: rewrite get_current_ram_size()
move get_current_ram_size to virtio-balloon.c
vhost-user: don't merge regions with different fds
...
If an instruction uses a 64 bit register which consists of an even-odd pair
of 32 bit registers and if the register specifier in the instruction is
odd an opd trap is raised.
target-tricore: Fix wrong precedences on psw_write
Wrong braces on the restore of the cached TCGv SV and V bit could lead to
a wrong PSW. While at this it removes unnecessary braces for the restore
of the cached TCGv AV and SAV bits.
target-tricore: fix save_context_upper using env->PSW
If the cached bits for C, V, SV, AV, or SAV were set, they would
not be saved during the context save since env->PSW was stored instead
of properly reading them using psw_read().
Eduardo Habkost [Sat, 23 Jan 2016 16:02:09 +0000 (14:02 -0200)]
q35: Remove old machine versions
Migration with q35 was not possible before commit 04329029a8c539eb5f75dcb6d8b016f0c53a031a, because q35
unconditionally creates an ich9-ahci device, that was marked as
unmigratable. So all q35 machine classes before pc-q35-2.4 were
not migratable, so there's no point in keeping compatibility code
for them.
Remove all old pc-q35 machine classes and keep only pc-q35-2.4
and newer.
Paolo Bonzini [Sun, 14 Feb 2016 17:17:08 +0000 (18:17 +0100)]
virtio-blk: fix "disabled data plane" mode
In disabled mode, virtio-blk dataplane seems to be enabled, but flow
actually goes through the normal virtio path. This patch simplifies a bit
the handling of disabled mode. In disabled mode, virtio_blk_handle_output
might be called even if s->dataplane is not NULL.
This is a bit tricky, because the current check for s->dataplane will
always trigger, causing a continuous stream of calls to
virtio_blk_data_plane_start. Unfortunately, these calls will not
do anything. To fix this, set the "started" flag even in disabled
mode, and skip virtio_blk_data_plane_start if the started flag is true.
The resulting changes also prepare the code for the next patch, were
virtio-blk dataplane will reuse the same virtio_blk_handle_output function
as "regular" virtio-blk.
Because struct VirtIOBlockDataPlane is opaque in virtio-blk.c, we have
to move s->dataplane->started inside struct VirtIOBlock.
Paolo Bonzini [Sun, 14 Feb 2016 17:17:07 +0000 (18:17 +0100)]
virtio: export vring_notify as virtio_should_notify
Virtio dataplane needs to trigger the irq manually through the
guest notifier. Export virtio_should_notify so that it can be
used around event_notifier_set.
Paolo Bonzini [Sun, 14 Feb 2016 17:17:04 +0000 (18:17 +0100)]
block-migration: acquire AioContext as necessary
This is needed because dataplane will run during block migration as well.
The block device migration code is quite liberal in taking the iothread
mutex. For simplicity, keep it the same way, even though one could
actually choose between the BQL (for regular BlockDriverStates) and
the AioContext (for dataplane BlockDriverStates). When the block layer
is made fully thread safe, aio_context_acquire shall go away altogether.
balloon: Use only 'pc-dimm' type dimm for ballooning
For now there are only two dimm's: pc-dimm and nvdimm. This patch is
actually needed to disable ballooning on nvdimm. But, to avoid future
bugs, instead of disallowing nvdimm, we allow only pc-dimm. So, if
someone adds new dimm which should be balloon-able, then this ability
should be explicitly specified here.
Why ballooning for nvdimm should be disabled for now:
NVDIMM for now is planned to use as a backing store for DAX filesystem
in the guest and thus this memory is excluded from guest memory
management and LRUs.
In this case libvirt running QEMU along with configured balloon almost
immediately inflates balloon and effectively kill the guest as
qemu counts nvdimm as part of the ram.
Counting dimm devices as part of the ram for ballooning was started from
commit 463756d03:
virtio-balloon: Fix balloon not working correctly when hotplug memory
Peter Maydell [Thu, 25 Feb 2016 10:46:06 +0000 (10:46 +0000)]
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160225' into staging
ppc patch queue for 2016-02-25
Hopefully final queue before qemu-2.6 soft freeze. Currently
accumulated patches for target-ppc, pseries machine type and related
devices:
* SLOF firmware update
- Many new features, including virtio 1.0 non-legacy support
* H_PAGE_INIT hypercall implementation
* Small cleanups and bugfixes.
# gpg: Signature made Thu 25 Feb 2016 03:00:56 GMT using RSA key ID 20D9B392
# gpg: Good signature from "David Gibson <[email protected]>"
# gpg: aka "David Gibson (Red Hat) <[email protected]>"
# gpg: aka "David Gibson (ozlabs.org) <[email protected]>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.6-20160225:
ppc/kvm: Tell the user what might be wrong when using bad CPU types with kvm-hv
ppc/kvm: Use error_report() instead of cpu_abort() for user-triggerable errors
spapr: initialize local Error pointer
hw/ppc/spapr: Implement the h_page_init hypercall
pseries: Update SLOF firmware image to 20160223
Thomas Huth [Thu, 18 Feb 2016 21:01:56 +0000 (22:01 +0100)]
ppc/kvm: Tell the user what might be wrong when using bad CPU types with kvm-hv
Using a CPU type that does not match the host is not possible when using
the kvm-hv kernel module - the PVR is checked in the kernel function
kvm_arch_vcpu_ioctl_set_sregs_hv() and rejected with -EINVAL if it
does not match the host.
However, when the user tries to specify a non-matching CPU type, QEMU
currently only reports "kvm_init_vcpu failed: Invalid argument", and
this is of course not very helpful for the user to solve the problem.
So this patch adds a more descriptive error message that tells the
user to specify "-cpu host" instead.
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