Fabiano Rosas [Wed, 12 Jan 2022 10:28:27 +0000 (11:28 +0100)]
target/ppc: Add MSR_ILE support to ppc_interrupts_little_endian
Some CPUs set ILE via an MSR bit. We can make
ppc_interrupts_little_endian handle that case as well. Now we have a
centralized way of determining the endianness of interrupts.
Fabiano Rosas [Wed, 12 Jan 2022 10:28:27 +0000 (11:28 +0100)]
target/ppc: Add HV support to ppc_interrupts_little_endian
The ppc_interrupts_little_endian function could be used for interrupts
delivered in Hypervisor mode, so add support for powernv8 and powernv9
to it.
Also drop the comment because it is inaccurate, all CPUs that can run
little endian can have interrupts in little endian. The point is
whether they can take interrupts in an endianness different from
MSR_LE.
Thomas Huth [Wed, 12 Jan 2022 10:28:26 +0000 (11:28 +0100)]
MAINTAINERS: Improve the PowerPC machines section
Add some documentation files to the corresponding machine sections
and mention the machine names in the section titles where it is
not so obvious (e.g. that "taihu" is a 405 machine).
Cédric Le Goater [Wed, 12 Jan 2022 10:28:26 +0000 (11:28 +0100)]
target/ppc: Add extra float instructions to POWER5P processors
ISA v2.03 introduced Floating Round to Integer instructions : frin,
friz, frip, and frim. Add them to POWER5+.
The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
Estimate) instruction which was introduced in ISA v2.0x. The
architecture document says its optional and that might be the reason
why it has been kept under the PPC_FLOAT_EXT flag. This means 970 CPUs
can not use it under QEMU, which doesn't seem to be a problem.
Cédric Le Goater [Wed, 12 Jan 2022 10:28:26 +0000 (11:28 +0100)]
spapr: Fix support of POWER5+ processors
POWER5+ (ISA v2.03) processors are supported by the pseries machine
but they do not have Altivec instructions. Do not advertise support
for it in the DT.
To be noted that this test is in contradiction with the assert in
cap_vsx_apply().
* remotes/jsnow-gitlab/tags/python-pull-request:
simplebench: Fix Python syntax error (reported by LGTM)
python: update type hints for mypy 0.930
Python/aqmp: fix type definitions for mypy 0.920
python/aqmp: use absolute import statement
Peter Maydell [Tue, 11 Jan 2022 11:39:31 +0000 (11:39 +0000)]
Merge remote-tracking branch 'remotes/philmd/tags/sdmmc-20220108' into staging
SD/MMC patches queue
- Add SDHC support for SD card SPI-mode (Frank Chang)
# gpg: Signature made Sat 08 Jan 2022 21:56:02 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/sdmmc-20220108:
hw/sd: Add SDHC support for SD card SPI-mode
hw/sd/sdcard: Rename Write Protect Group variables
Peter Maydell [Tue, 11 Jan 2022 10:12:29 +0000 (10:12 +0000)]
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
virtio: revert config interrupt changes
Lots of fallout from config interrupt changes. Author wants to rework
the patches. Let's revert quickly so others don't suffer meanwhile.
Signed-off-by: Michael S. Tsirkin <[email protected]>
# gpg: Signature made Mon 10 Jan 2022 21:03:44 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "[email protected]"
# gpg: Good signature from "Michael S. Tsirkin <[email protected]>" [full]
# gpg: aka "Michael S. Tsirkin <[email protected]>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* remotes/mst/tags/for_upstream:
Revert "virtio: introduce macro IRTIO_CONFIG_IRQ_IDX"
Revert "virtio-pci: decouple notifier from interrupt process"
Revert "virtio-pci: decouple the single vector from the interrupt process"
Revert "vhost: introduce new VhostOps vhost_set_config_call"
Revert "vhost-vdpa: add support for config interrupt"
Revert "virtio: add support for configure interrupt"
Revert "vhost: add support for configure interrupt"
Revert "virtio-net: add support for configure interrupt"
Revert "virtio-mmio: add support for configure interrupt"
Revert "virtio-pci: add support for configure interrupt"
John Snow [Mon, 10 Jan 2022 19:13:49 +0000 (14:13 -0500)]
python: update type hints for mypy 0.930
Mypy 0.930, released Dec 22, changes the way argparse objects are
considered. Crafting a definition that works under Python 3.6 and an
older mypy alongside newer versions simultaneously is ... difficult,
so... eh. Stub it out with an 'Any' definition to get the CI moving
again.
John Snow [Mon, 10 Jan 2022 19:13:47 +0000 (14:13 -0500)]
python/aqmp: use absolute import statement
pylint's dependency astroid appears to have bugs in 2.9.1 and 2.9.2 (Dec
31 and Jan 3) that appear to erroneously expect the qemu namespace to
have an __init__.py file. astroid 2.9.3 (Jan 9) avoids that problem, but
appears to not understand a relative import within a namespace package.
Update the relative import - it was worth changing anyway, because these
packages will eventually be packaged and distributed separately.
Fixes: 316011b8a7 ("virtio-pci: decouple the single vector from the interrupt process") Cc: "Cindy Lu" <[email protected]> Signed-off-by: Michael S. Tsirkin <[email protected]>
Fixes: 634f7c89fb ("vhost-vdpa: add support for config interrupt") Cc: "Cindy Lu" <[email protected]> Signed-off-by: Michael S. Tsirkin <[email protected]>
Fixes: 081f864f56 ("virtio: add support for configure interrupt") Cc: "Cindy Lu" <[email protected]> Signed-off-by: Michael S. Tsirkin <[email protected]>
Fixes: f7220a7ce2 ("vhost: add support for configure interrupt") Cc: "Cindy Lu" <[email protected]> Signed-off-by: Michael S. Tsirkin <[email protected]>
Fixes: 497679d510 ("virtio-net: add support for configure interrupt") Cc: "Cindy Lu" <[email protected]> Signed-off-by: Michael S. Tsirkin <[email protected]>
Fixes: d48185f1a4 ("virtio-mmio: add support for configure interrupt") Cc: "Cindy Lu" <[email protected]> Signed-off-by: Michael S. Tsirkin <[email protected]>
Fixes: d5d24d859c ("virtio-pci: add support for configure interrupt") Cc: "Cindy Lu" <[email protected]> Signed-off-by: Michael S. Tsirkin <[email protected]>
target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DATA feature enabled
Commit a9431a03f7 ("target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature") added
a new feature for processors from the 68020 onwards which do not require data
accesses to be word aligned.
Unfortunately the original commit missed an additional case whereby the SP is
still word aligned when setting up an additional format 1 stack frame so add the
necessary M68K_FEATURE_UNALIGNED_DATA feature guard.
The macfb VRAM memory region was configured with coalescing rather than dirty
memory logging enabled, causing some areas of the screen not to redraw after
a full screen update.
Laurent Vivier [Fri, 7 Jan 2022 10:50:49 +0000 (11:50 +0100)]
q800: fix segfault with invalid MacROM
"qemu-system-m68k -M q800 -bios /dev/null" crashes with a segfault
in q800_init().
This happens because the code doesn't check that rom_ptr() returned
a non-NULL pointer .
To avoid NULL pointer, don't allow 0 sized file and use bios_size with
rom_ptr().
Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into staging
bsd-user: arm (32-bit) support
This series of patches brings in 32-bit arm support for bsd-user. It implements
all the bits needed to do image activation, signal handling, stack management
and threading. This allows us to get to the "Hello World" level. The arm and x86
code are now the same as in the bsd-user fork. For full context, the fork is at
https://github.com/qemu-bsd-user/qemu-bsd-user/tree/blitz (though the the recent
sig{bus,segv} needed updates are incomplete).
v5 changes:
o Moved to using the CPUArchState typedef and move
set_sigtramp_args, get_mcontext, set_mcontext, and
get_ucontext_sigreturn prototypes to
bsd-user/freebsd/target_os_ucontext.h
o Fix issues with arm's set_mcontext related to masking
and remove an unnecessary check.
We're down to only one hunk needing review:
bsd-user/arm/target_arch_signal.c: arm set_mcontext
Warnings that should be ignored:
o make checkpatch has a couple of complaints about the comments for the
signal trampoline, since it's a false positive IMHO.
WARNING: Block comments use a leading /* on a separate line
+ /* 8 */ sys_sigreturn,
WARNING: Block comments use a leading /* on a separate line
+ /* 9 */ sys_exit
# gpg: Signature made Fri 07 Jan 2022 11:36:37 PM PST
# gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100
# gpg: Good signature from "Warner Losh <[email protected]>" [unknown]
# gpg: aka "Warner Losh <[email protected]>" [unknown]
# gpg: aka "Warner Losh <[email protected]>" [unknown]
# gpg: aka "Warner Losh <[email protected]>" [unknown]
# gpg: aka "Warner Losh <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100
* tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu: (37 commits)
bsd-user: add arm target build
bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE
bsd-user/arm/signal.c: arm get_ucontext_sigreturn
bsd-user/arm/signal.c: arm set_mcontext
bsd-user/arm/signal.c: arm get_mcontext
bsd-user/arm/signal.c: arm set_sigtramp_args
bsd-user/arm/target_arch_signal.h: Define size of *context_t
bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signals
bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack
bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl
bsd-user/arm/target_arch_elf.h: arm get hwcap
bsd-user/arm/target_arch_elf.h: arm defines for ELF
bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread
bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm
bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space
bsd-user/arm/target_arch_reg.h: Implement core dump register copying
bsd-user/arm/target_arch_cpu.h: Implement system call dispatch
bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions
bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions
bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation
...
Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging
Second RISC-V PR for QEMU 7.0
- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- SiFive PLIC cleanups
- Mark Hypervisor extension as non experimental
- Enable Hypervisor extension by default
- Support 32 cores on the virt machine
- Corrections for the Vector extension
- Experimental support for 128-bit CPUs
- stval and mtval support for illegal instructions
# gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <[email protected]>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits)
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Fixup setting GVA
target/riscv: Set the opcode in DisasContext
target/riscv: actual functions to realize crs 128-bit insns
target/riscv: modification of the trans_csrxx for 128-bit support
target/riscv: helper functions to wrap calls to 128-bit csr insns
target/riscv: adding high part of some csrs
target/riscv: support for 128-bit M extension
target/riscv: support for 128-bit arithmetic instructions
target/riscv: support for 128-bit shift instructions
target/riscv: support for 128-bit U-type instructions
target/riscv: support for 128-bit bitwise instructions
target/riscv: accessors to registers upper part and 128-bit load/store
target/riscv: moving some insns close to similar insns
target/riscv: setup everything for rv64 to support rv128 execution
target/riscv: array for the 64 upper bits of 128-bit registers
target/riscv: separation of bitwise logic and arithmetic helpers
target/riscv: additional macros to check instruction support
qemu/int128: addition of div/rem 128-bit operations
exec/memop: Adding signed quad and octo defines
...
Warner Losh [Thu, 4 Nov 2021 23:08:04 +0000 (17:08 -0600)]
bsd-user/arm/target_arch_signal.h: Define size of *context_t
Define the native sizes of mcontext_t and ucontext_t so that the tests
in target_os_ucontext.h ensure the size of arm's version of these
structures is correct.
Warner Losh [Thu, 23 Sep 2021 15:12:12 +0000 (09:12 -0600)]
bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space
Various parameters describing the layout of the ARM address space. In
addition, define routines to get the stack pointer and to set the second
return value.
Warner Losh [Thu, 23 Sep 2021 15:08:21 +0000 (09:08 -0600)]
bsd-user/arm/target_arch_cpu.h: Implement system call dispatch
Implement the system call dispatch. This implements all three kinds of
system call: direct and the two indirect variants. It handles all the
special cases for thumb as well.
Implement EXCP_UDEF, EXCP_DEBUG, EXCP_INTERRUPT, EXCP_ATOMIC and
EXCP_YIELD. The first two generate a signal to the emulated
binary. EXCP_ATOMIC handles atomic operations. The remainder are fancy
nops.
Warner Losh [Thu, 23 Sep 2021 14:29:39 +0000 (08:29 -0600)]
bsd-user/arm/target_syscall.h: Add copyright and update name
The preferred name for the 32-bit arm is now armv7. Update the name to
reflect that. In addition, add Stacey's copyright to this file and
update the include guards to the new convention.
Warner Losh [Thu, 4 Nov 2021 22:34:48 +0000 (16:34 -0600)]
bsd-user: create a per-arch signal.c file
Create a place-holder signal.c file for each of the architectures that
are currently built. In the future, some code that's currently inlined
in target_arch_signal.h will live here.
Warner Losh [Fri, 29 Oct 2021 14:39:01 +0000 (08:39 -0600)]
bsd-user/freebsd: Create common target_os_ucontext.h file
FreeBSD has a MI ucontext structure that contains the MD mcontext
machine state and other things that are machine independent. Create an
include file for all the ucontext stuff. It needs to be included in the
arch specific files after target_mcontext is defined. This is largely
copied from sys/_ucontext.h with the comments about layout removed
because we don't support ancient FreeBSD binaries.
Warner Losh [Thu, 4 Nov 2021 22:31:27 +0000 (16:31 -0600)]
bsd-user/mips*: Remove mips support
FreeBSD is dropping support for mips starting with FreeBSD 14. mips
support has been removed from the bsd-user fork because updating it for
new signal requirements will take too much time. Remove it here since it
is a distraction.
Alistair Francis [Mon, 20 Dec 2021 06:49:16 +0000 (16:49 +1000)]
target/riscv: Implement the stval/mtval illegal instruction
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers.
The RISC-V spec states that "The stval register can optionally also be
used to return the faulting instruction bits on an illegal instruction
exception...". In this case we are always writing the value on an
illegal instruction.
This doesn't match all CPUs (some CPUs won't write the data), but in
QEMU let's just populate the value on illegal instructions. This won't
break any guest software, but will provide more information to guests.
Alistair Francis [Mon, 20 Dec 2021 06:49:15 +0000 (16:49 +1000)]
target/riscv: Fixup setting GVA
In preparation for adding support for the illegal instruction address
let's fixup the Hypervisor extension setting GVA logic and improve the
variable names.
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:08 +0000 (22:01 +0100)]
target/riscv: actual functions to realize crs 128-bit insns
The csrs are accessed through function pointers: we add 128-bit read
operations in the table for three csrs (writes fallback to the
64-bit version as the upper 64-bit information is handled elsewhere):
- misa, as mxl is needed for proper operation,
- mstatus and sstatus, to return sd
In addition, we also add read and write accesses to the machine and
supervisor scratch registers.
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:07 +0000 (22:01 +0100)]
target/riscv: modification of the trans_csrxx for 128-bit support
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:06 +0000 (22:01 +0100)]
target/riscv: helper functions to wrap calls to 128-bit csr insns
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We return 128-bit values using the same approach as for div/rem.
Theses helpers all call a unique function that is currently a fallback
on the 64-bit version.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:04 +0000 (22:01 +0100)]
target/riscv: support for 128-bit M extension
Mult are generated inline (using a cool trick pointed out by Richard), but
for div and rem, given the complexity of the implementation of these
instructions, we call helpers to produce their behavior. From an
implementation standpoint, the helpers return the low part of the results,
while the high part is temporarily stored in a dedicated field of cpu_env
that is used to update the architectural register in the generation wrapper.
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:03 +0000 (22:01 +0100)]
target/riscv: support for 128-bit arithmetic instructions
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:00 +0000 (22:01 +0100)]
target/riscv: support for 128-bit bitwise instructions
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:59 +0000 (22:00 +0100)]
target/riscv: accessors to registers upper part and 128-bit load/store
Get function to retrieve the 64 top bits of a register, stored in the gprh
field of the cpu state. Set function that writes the 128-bit value at once.
The access to the gprh field can not be protected at compile time to make
sure it is accessed only in the 128-bit version of the processor because we
have no way to indicate that the misa_mxl_max field is const.
The 128-bit ISA adds ldu, lq and sq. We provide support for these
instructions. Note that (a) we compute only 64-bit addresses to actually
access memory, cowardly utilizing the existing address translation mechanism
of QEMU, and (b) we assume for now little-endian memory accesses.
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:58 +0000 (22:00 +0100)]
target/riscv: moving some insns close to similar insns
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
where they more logically belong.
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:57 +0000 (22:00 +0100)]
target/riscv: setup everything for rv64 to support rv128 execution
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:55 +0000 (22:00 +0100)]
target/riscv: separation of bitwise logic and arithmetic helpers
Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:54 +0000 (22:00 +0100)]
target/riscv: additional macros to check instruction support
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Although RV128 is a superset of RV64, we keep for now the RV64 only tests
for extensions other than RVI and RVM.
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:53 +0000 (22:00 +0100)]
qemu/int128: addition of div/rem 128-bit operations
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and
64x64->128 mulu in host-utils.
These operations will be used within div/rem helpers in the 128-bit riscv
target.
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:51 +0000 (22:00 +0100)]
exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Philipp Tomsich [Thu, 6 Jan 2022 13:40:20 +0000 (14:40 +0100)]
target/riscv: Fix position of 'experimental' comment
When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set
them to be enabled by default, the comment about experimental
extensions was kept in place above them. This moves it down a few
lines to only cover experimental extensions.
Frank Chang [Wed, 5 Jan 2022 02:22:46 +0000 (10:22 +0800)]
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns
vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
floating-point. Therefore, should use require_rvf() to check whether
RVF/RVD is enabled.
vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to
single-width integer. Therefore, should use require_scale_rvf() to check
whether RVF/RVD is enabled.
Frank Chang [Wed, 5 Jan 2022 02:22:45 +0000 (10:22 +0800)]
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
floating-point, and vfwcvt.f.f.v convert double-width floating-point to
single-width floating-point. Therefore, should use require_scale_rvf() to
check whether RVF/RVD is enabled.
projects / qemu.git / log