* remotes/vivier2/tags/linux-user-for-6.0-pull-request:
linux-user/sparc: Handle tstate in sparc64_get/set_context()
linux-user/sparc: Don't restore %g7 in sparc64_set_context()
linux-user/sparc: Remove unneeded checks of 'err' from sparc64_get_context()
linux-user/sparc: Correct sparc64_get/set_context() FPU handling
linux-user: Add most IFTUN ioctls
linux-user: Implement copy_file_range
docs/user: Display linux-user binaries nicely
linux-user: Add support for MIPS Loongson 2F/3A
linux-user/elfload: Update HWCAP bits from linux 5.7
linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro
linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro
linux-user/elfload: Rename MIPS GET_FEATURE() as GET_FEATURE_INSN()
linux-user/elfload: Move GET_FEATURE macro out of get_elf_hwcap() body
linux-user/mmap.c: check range of mremap result in target address space
Peter Maydell [Fri, 18 Dec 2020 11:12:35 +0000 (11:12 +0000)]
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging
A collection of RISC-V improvements:
- Improve the sifive_u DTB generation
- Add QSPI NOR flash to Microchip PFSoC
- Fix a bug in the Hypervisor HLVX/HLV/HSV instructions
- Fix some mstatus mask defines
- Ibex PLIC improvements
- OpenTitan memory layout update
- Initial steps towards support for 32-bit CPUs on 64-bit builds
# gpg: Signature made Fri 18 Dec 2020 05:59:42 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <[email protected]>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20201217-1: (23 commits)
riscv/opentitan: Update the OpenTitan memory layout
hw/riscv: Use the CPU to determine if 32-bit
target/riscv: cpu: Set XLEN independently from target
target/riscv: csr: Remove compile time XLEN checks
target/riscv: cpu_helper: Remove compile time XLEN checks
target/riscv: cpu: Remove compile time XLEN checks
target/riscv: Specify the XLEN for CPUs
target/riscv: Add a riscv_cpu_is_32bit() helper function
target/riscv: fpu_helper: Match function defs in HELPER macros
hw/riscv: sifive_u: Remove compile time XLEN checks
hw/riscv: spike: Remove compile time XLEN checks
hw/riscv: virt: Remove compile time XLEN checks
hw/riscv: boot: Remove compile time XLEN checks
riscv: virt: Remove target macro conditionals
riscv: spike: Remove target macro conditionals
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
hw/riscv: Expand the is 32-bit check to support more CPUs
intc/ibex_plic: Clear interrupts that occur during claim process
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
target/riscv: Fix the bug of HLVX/HLV/HSV
...
Peter Maydell [Fri, 6 Nov 2020 15:27:38 +0000 (15:27 +0000)]
linux-user/sparc: Handle tstate in sparc64_get/set_context()
Correctly implement save/restore of the tstate field in
sparc64_get_context() and sparc64_set_context():
* Don't use the CWP value from the guest in set_context
* Construct and save a tstate value rather than leaving
it as zero in get_context
To do this we factor out the "calculate TSTATE value from CPU state"
code from sparc_cpu_do_interrupt() into its own sparc64_tstate()
function; that in turn requires us to move some of the function
prototypes out from inside a CPU_NO_IO_DEFS ifdef guard.
Peter Maydell [Fri, 6 Nov 2020 15:27:36 +0000 (15:27 +0000)]
linux-user/sparc: Remove unneeded checks of 'err' from sparc64_get_context()
Unlike the kernel macros, our __get_user() and __put_user() do not
return a failure code. Kernel code typically has a style of
err |= __get_user(...); err |= __get_user(...);
and then checking err at the end. In sparc64_get_context() our
version of the code dropped the accumulating into err but left the
"if (err) goto do_sigsegv" checks, which will never be taken. Delete
unnecessary if()s.
The handling of the FPU state in sparc64_get_context() and
sparc64_set_context() is not the same as what the kernel actually
does: we unconditionally read and write the FP registers and the
FSR, GSR and FPRS, but the kernel logic is more complicated:
* in get_context the kernel has code for saving FPU registers,
but it is hidden inside an "if (fenab) condition and the
fenab flag is always set to 0 (inside an "#if 1" which has
been in the kernel for over 15 years). So the effect is that
the FPU state part is always written as zeroes.
* in set_context the kernel looks at the fenab field in the
structure from the guest, and only restores the state if
it is set; it also looks at the structure's FPRS to see
whether either the upper or lower or both halves of the
register file have valid data.
Bring our implementations into line with the kernel:
* in get_context:
- clear the entire target_ucontext at the top of the
function (as the kernel does)
- then don't write the FPU state, so those fields remain zero
- this fixes Coverity issue CID 1432305 by deleting the code
it was complaining about
* in set_context:
- check the fenab and the fpsr to decide which parts of
the FPU data to restore, if any
- instead of setting the FPU registers by doing two
32-bit loads and filling in the .upper and .lower parts
of the CPU_Double union separately, just do a 64-bit
load of the whole register at once. This fixes Coverity
issue CID 1432303 because we now access the dregs[] part
of the mcfpu_fregs union rather than the sregs[] part
(which is not large enough to actually cover the whole of
the data, so we were accessing off the end of sregs[])
We change both functions in a single commit to avoid potentially
breaking bisection.
The three options handling `struct sock_fprog` (TUNATTACHFILTER,
TUNDETACHFILTER, and TUNGETFILTER) are not implemented. Linux kernel
keeps a user space pointer in them which we cannot correctly handle.
Thomas Huth [Fri, 11 Dec 2020 15:24:26 +0000 (16:24 +0100)]
configure: Compile with -Wimplicit-fallthrough=2
Coverity always complains about switch-case statements that fall through
the next one when there is no comment in between - which could indicate
a forgotten "break" statement. Instead of handling these issues after
they have been committed, it would be better to avoid them in the build
process already. Thus let's enable the -Wimplicit-fallthrough warning now.
The "=2" level seems to be a good compromise between being too strict and
too generic about the possible comments, so we'll start with "=2" for now.
Thomas Huth [Thu, 17 Dec 2020 12:57:24 +0000 (13:57 +0100)]
bsd-user: Silence warnings about missing fallthrough statement
When compiling with -Werror=implicit-fallthrough, the compiler complains
about a missing fallthrough annotation in this file. Looking at the code,
the fallthrough is indeed wanted here, so let's add a proper comment.
Thomas Huth [Fri, 11 Dec 2020 15:24:24 +0000 (16:24 +0100)]
tcg/optimize: Add fallthrough annotations
To be able to compile this file with -Werror=implicit-fallthrough,
we need to add some fallthrough annotations to the case statements
that might fall through. Unfortunately, the typical "/* fallthrough */"
comments do not work here as expected since some case labels are
wrapped in macros and the compiler fails to match the comments in
this case. But using __attribute__((fallthrough)) seems to work fine,
so let's use that instead (by introducing a new QEMU_FALLTHROUGH
macro in our compiler.h header file).
Chen Qun [Fri, 11 Dec 2020 15:24:23 +0000 (16:24 +0100)]
target/sparc/win_helper: silence the compiler warnings
When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning:
target/sparc/win_helper.c: In function ‘get_gregset’:
target/sparc/win_helper.c:304:9: warning: this statement may fall through [-Wimplicit-fallthrough=]
304 | trace_win_helper_gregset_error(pstate);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
target/sparc/win_helper.c:306:5: note: here
306 | case 0:
| ^~~~
Add the corresponding "fall through" comment to fix it.
Chen Qun [Fri, 11 Dec 2020 15:24:22 +0000 (16:24 +0100)]
target/sparc/translate: silence the compiler warnings
When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning:
target/sparc/translate.c: In function ‘gen_st_asi’:
target/sparc/translate.c:2320:12: warning: this statement may fall through [-Wimplicit-fallthrough=]
2320 | if (!(dc->def->features & CPU_FEATURE_HYPV)) {
| ^
target/sparc/translate.c:2329:5: note: here
2329 | case GET_ASI_DIRECT:
| ^~~~
The "fall through" statement place is not correctly identified by the compiler.
Chen Qun [Fri, 11 Dec 2020 15:24:21 +0000 (16:24 +0100)]
accel/tcg/user-exec: silence the compiler warnings
When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning:
../accel/tcg/user-exec.c: In function ‘handle_cpu_signal’:
../accel/tcg/user-exec.c:169:13: warning: this statement may fall through [-Wimplicit-fallthrough=]
169 | cpu_exit_tb_from_sighandler(cpu, old_set);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../accel/tcg/user-exec.c:172:9: note: here
172 | default:
Mark the cpu_exit_tb_from_sighandler() function with QEMU_NORETURN to fix it.
Chen Qun [Fri, 11 Dec 2020 15:24:20 +0000 (16:24 +0100)]
hw/intc/arm_gicv3_kvm: silence the compiler warnings
When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning:
hw/intc/arm_gicv3_kvm.c: In function ‘kvm_arm_gicv3_put’:
hw/intc/arm_gicv3_kvm.c:484:13: warning: this statement may fall through [-Wimplicit-fallthrough=]
kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
hw/intc/arm_gicv3_kvm.c:485:9: note: here
default:
^~~~~~~
hw/intc/arm_gicv3_kvm.c:495:13: warning: this statement may fall through [-Wimplicit-fallthrough=]
kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
hw/intc/arm_gicv3_kvm.c:496:9: note: here
case 6:
^~~~
hw/intc/arm_gicv3_kvm.c:498:13: warning: this statement may fall through [-Wimplicit-fallthrough=]
kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
hw/intc/arm_gicv3_kvm.c:499:9: note: here
default:
^~~~~~~
hw/intc/arm_gicv3_kvm.c: In function ‘kvm_arm_gicv3_get’:
hw/intc/arm_gicv3_kvm.c:634:37: warning: this statement may fall through [-Wimplicit-fallthrough=]
c->icc_apr[GICV3_G0][2] = reg64;
~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
hw/intc/arm_gicv3_kvm.c:635:9: note: here
case 6:
^~~~
hw/intc/arm_gicv3_kvm.c:637:37: warning: this statement may fall through [-Wimplicit-fallthrough=]
c->icc_apr[GICV3_G0][1] = reg64;
~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
hw/intc/arm_gicv3_kvm.c:638:9: note: here
default:
^~~~~~~
hw/intc/arm_gicv3_kvm.c:648:39: warning: this statement may fall through [-Wimplicit-fallthrough=]
c->icc_apr[GICV3_G1NS][2] = reg64;
~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
hw/intc/arm_gicv3_kvm.c:649:9: note: here
case 6:
^~~~
hw/intc/arm_gicv3_kvm.c:651:39: warning: this statement may fall through [-Wimplicit-fallthrough=]
c->icc_apr[GICV3_G1NS][1] = reg64;
~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
hw/intc/arm_gicv3_kvm.c:652:9: note: here
default:
^~~~~~~
Chen Qun [Fri, 11 Dec 2020 15:24:19 +0000 (16:24 +0100)]
target/i386: silence the compiler warnings in gen_shiftd_rm_T1
The current "#ifdef TARGET_X86_64" statement affects
the compiler's determination of fall through.
When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning:
target/i386/translate.c: In function ‘gen_shiftd_rm_T1’:
target/i386/translate.c:1773:12: warning: this statement may fall through [-Wimplicit-fallthrough=]
if (is_right) {
^
target/i386/translate.c:1782:5: note: here
case MO_32:
^~~~
Chen Qun [Fri, 11 Dec 2020 15:24:18 +0000 (16:24 +0100)]
hw/timer/renesas_tmr: silence the compiler warnings
When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning:
../hw/timer/renesas_tmr.c: In function ‘tmr_read’:
../hw/timer/renesas_tmr.c:221:19: warning: this statement may fall through [-Wimplicit-fallthrough=]
221 | } else if (ch == 0) {i
| ^
../hw/timer/renesas_tmr.c:224:5: note: here
224 | case A_TCORB:
| ^~~~
Add the corresponding "fall through" comment to fix it.
Thomas Huth [Fri, 11 Dec 2020 15:24:17 +0000 (16:24 +0100)]
hw/rtc/twl92230: Silence warnings about missing fallthrough statements
When compiling with -Werror=implicit-fallthrough, gcc complains about
missing fallthrough annotations in this file. Looking at the code,
the fallthrough is indeed wanted here, but instead of adding the
annotations, it can be done more efficiently by simply calculating
the offset with a subtraction instead of increasing a local variable
one by one.
Looking at the way the code is formatted here (there is an empty line
after break statements, but none where the break is missing), and the
instruction set overview at https://en.wikipedia.org/wiki/Unicore the
fallthrough is very likely intended here. So add a fallthrough comment
to make the it compilable with -Werror=implicit-fallthrough.
Thomas Huth [Fri, 11 Dec 2020 15:24:15 +0000 (16:24 +0100)]
disas/libvixl: Fix fall-through annotation for GCC >= 7
For compiling with -Wimplicit-fallthrough we need to fix the
fallthrough annotations in the libvixl code. This is based on
the following upstream vixl commit by Martyn Capewell:
Alistair Francis [Wed, 16 Dec 2020 18:23:08 +0000 (10:23 -0800)]
hw/riscv: Use the CPU to determine if 32-bit
Instead of using string compares to determine if a RISC-V machine is
using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
us having to maintain a list of CPU names to compare against.
This commit also fixes the name of the function to match the
riscv_cpu_is_32bit() function.
intc/ibex_plic: Clear interrupts that occur during claim process
Previously if an interrupt occured during the claim process (after the
interrupt is claimed but before it's completed) it would never be
cleared.
This patch ensures that we also clear the hidden_pending bits as well.
Alex Richardson [Mon, 30 Nov 2020 17:01:17 +0000 (17:01 +0000)]
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
The TW and TSR fields should be bits 21 and 22 and not 30/29.
This was found while comparing QEMU behaviour against the sail formal
model (https://github.com/rems-project/sail-riscv/).
Yifei Jiang [Mon, 30 Nov 2020 01:28:10 +0000 (09:28 +0800)]
target/riscv: Fix the bug of HLVX/HLV/HSV
We found that the hypervisor virtual-machine load and store instructions,
included HLVX/HLV/HSV, couldn't access guest userspace memory.
In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow:
"As usual when V=1, two-stage address translation is applied, and
the HS-level sstatus.SUM is ignored."
But get_physical_address() doesn't ignore sstatus.SUM, when HLVX/HLV/HSV
accesses guest userspace memory. So this patch fixes it.
* remotes/ehabkost-gl/tags/x86-next-pull-request:
cpu: Remove unnecessary noop methods
tcg: Make CPUClass.debug_excp_handler optional
tcg: make CPUClass.cpu_exec_* optional
tcg: cpu_exec_{enter,exit} helpers
i386: tcg: remove inline from cpu_load_eflags
i386: move TCG cpu class initialization to tcg/
x86/cpu: Add AVX512_FP16 cpu feature
i386: move hyperv_limits initialization to x86_cpu_realizefn()
i386: move hyperv_version_id initialization to x86_cpu_realizefn()
i386: move hyperv_interface_id initialization to x86_cpu_realizefn()
i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()
i386: move cpu dump out of helper.c into cpu-dump.c
i386: move TCG accel files into tcg/
i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
i386: move hax accel files into hax/
i386: move whpx accel files into whpx/
i386: move kvm accel files into kvm/
Userland ELF binaries using Loongson SIMD instructions have the
HWCAP_LOONGSON_MMI bit set [1].
Binaries compiled for Loongson 3A [2] have the HWCAP_LOONGSON_EXT
bit set for the LQ / SQ instructions.
ISA features are usually denoted in read-only bits from
CPU registers. Add the GET_FEATURE_REG_EQU() macro which
checks if a CPU register has bits set to a specific value.
Use the macro to check the 'Architecture Revision' level
of the Config0 register, which is '2' when the Release 6
ISA is implemented.
ISA features are usually denoted in read-only bits from
CPU registers. Add the GET_FEATURE_REG_SET() macro which
checks if a CPU register has bits set.
Use the macro to check for MSA (which sets the MSAP bit of
the Config3 register when the ASE implementation is present).
Tobias Koch [Wed, 28 Oct 2020 21:38:33 +0000 (22:38 +0100)]
linux-user/mmap.c: check range of mremap result in target address space
If mremap succeeds, an additional check is performed to ensure that the
new address range fits into the target address space. This check was
previously perfomed in host address space, with the upper bound fixed to
abi_ulong.
This patch replaces the static check with a call to `guest_range_valid`,
performing the range check against the actual size of the target address
space. It also moves the corresponding block to prevent it from being
called incorrectly when the mapping itself fails.
Claudio Fontana [Sat, 12 Dec 2020 15:55:14 +0000 (16:55 +0100)]
i386: move TCG cpu class initialization to tcg/
to do this, we need to take code out of cpu.c and helper.c,
and also move some prototypes from cpu.h, for code that is
needed in tcg/xxx_helper.c, and which in turn is part of the
callbacks registered by the class initialization.
Therefore, do some shuffling of the parts of cpu.h that
are only relevant for tcg/, and put them in tcg/helper-tcg.h
For FT0 and similar macros, put them in tcg/fpu-helper.c
since they are used only there.
Cathy Zhang [Wed, 16 Dec 2020 22:40:02 +0000 (06:40 +0800)]
x86/cpu: Add AVX512_FP16 cpu feature
AVX512 Half-precision floating point (FP16) has better performance
compared to FP32 if the presicion or magnitude requirements are met.
It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23].
Refer to
https://software.intel.com/content/www/us/en/develop/download/\
intel-architecture-instruction-set-extensions-programming-reference.html
Vitaly Kuznetsov [Thu, 19 Nov 2020 10:32:17 +0000 (11:32 +0100)]
i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()
As a preparation to expanding Hyper-V CPU features early, move
hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce
x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn()
itself.
* remotes/bonzini-gitlab/tags/for-upstream: (45 commits)
build: -no-pie is no functional linker flag
scripts/git.orderfile: Keep files with .inc extension sorted
compiler.h: remove QEMU_GNUC_PREREQ
linux-user: remove GNUC check
compiler: remove GNUC check
xen: remove GNUC check
poison: remove GNUC check
compiler.h: explicit case for Clang printf attribute
virtiofsd: replace _Static_assert with QEMU_BUILD_BUG_ON
tests: remove GCC < 4 fallbacks
qemu-plugin.h: remove GCC < 4
compiler.h: remove GCC < 3 __builtin_expect fallback
accel/tcg: Remove special case for GCC < 4.6
qemu/atomic: Drop special case for unsupported compiler
hw/core: Restrict 'fw-path-provider.c' to system mode emulation
docs: set CONFDIR when running sphinx
vl: rename local variable in configure_accelerators
qemu-option: pass QemuOptsList to opts_accepts_any
qemu-option: simplify search for end of key
kvm: Take into account the unaligned section size when preparing bitmap
...
Signed-off-by: Peter Maydell <[email protected]>
# Conflicts:
# softmmu/vl.c
Recent binutils changes dropping unsupported options [1] caused a build
issue in regard to the optionroms.
ld -m elf_i386 -T /<<PKGBUILDDIR>>/pc-bios/optionrom//flat.lds -no-pie \
-s -o multiboot.img multiboot.o
ld.bfd: Error: unable to disambiguate: -no-pie (did you mean --no-pie ?)
This isn't really a regression in ld.bfd, filing the bug upstream
revealed that this never worked as a ld flag [2] - in fact it seems we
were by accident setting --nmagic).
Since it never had the wanted effect this usage of LDFLAGS_NOPIE, should be
droppable without any effect. This also is the only use-case of LDFLAGS_NOPIE
in .mak, therefore we can also remove it from being added there.
compiler.h: explicit case for Clang printf attribute
Since commit efc6c07 ("configure: Add a test for the minimum compiler
version"), QEMU explicitely depends on GCC >= 4.8, we could thus drop
earlier version checks. Except clang advertizes itself as GCC 4.2.1.
Since clang doesn't support gnu_printf, make that case explicitely and
drop GCC version check.
Since commit efc6c070aca ("configure: Add a test for the
minimum compiler version") the minimum compiler version
required for GCC is 4.8.
We can safely remove the special case for GCC 4.6 introduced
in commit 0448f5f8b81 ("cpu-exec: Fix compiler warning
(-Werror=clobbered)").
No change for Clang as we don't know.
qemu/atomic: Drop special case for unsupported compiler
Since commit efc6c070aca ("configure: Add a test for the
minimum compiler version") the minimum compiler version
required for GCC is 4.8, which has the GCC BZ#36793 bug fixed.
We can safely remove the special case introduced in commit a281ebc11a6 ("virtio: add missing mb() on notification").
With clang 3.4, __ATOMIC_RELAXED is defined, so the chunk to
remove (which is x86-specific), isn't reached either.
Paolo Bonzini [Mon, 2 Nov 2020 15:46:52 +0000 (10:46 -0500)]
vl: rename local variable in configure_accelerators
Silly patch extracted from the next one, which is already big enough.
Because there are already local variables named "accel", we will name
the global vl.c variable for "-M accel" accelerators instead. Rename
it already in configure_accelerators to be ready.
Paolo Bonzini [Mon, 9 Nov 2020 08:50:46 +0000 (03:50 -0500)]
qemu-option: pass QemuOptsList to opts_accepts_any
A QemuOptsList can be of one of two kinds: either it is pre-validated, or
it accepts any key and validation happens somewhere else (typically in
a Visitor or against a list of QOM properties). opts_accepts_any
returns true if a QemuOpts instance was created from a QemuOptsList of
the latter kind, but there is no function to do the check on a QemuOptsList.
Since this property comes from the QemuOptsList and almost all callers of
opts_accepts_any use opts->list anyway, modify the function to accept
QemuOptsList.
Zenghui Yu [Tue, 8 Dec 2020 11:40:13 +0000 (19:40 +0800)]
kvm: Take into account the unaligned section size when preparing bitmap
The kernel KVM_CLEAR_DIRTY_LOG interface has align requirement on both the
start and the size of the given range of pages. We have been careful to
handle the unaligned cases when performing CLEAR on one slot. But it seems
that we forget to take the unaligned *size* case into account when
preparing bitmap for the interface, and we may end up clearing dirty status
for pages outside of [start, start + size).
If the size is unaligned, let's go through the slow path to manipulate a
temp bitmap for the interface so that we won't bother with those unaligned
bits at the end of bitmap.
I don't think this can happen in practice since the upper layer would
provide us with the alignment guarantee. I'm not sure if kvm-all could rely
on it. And this patch is mainly intended to address correctness of the
specific algorithm used inside kvm_log_clear_one_slot().
Maxim Levitsky [Thu, 10 Dec 2020 12:59:29 +0000 (14:59 +0200)]
scsi: fix device removal race vs IO restart callback on resume
There is (mostly theoretical) race between removal of a scsi device and
scsi_dma_restart_bh.
It used to be easier to hit this race prior to my / Paulo's patch series
that added rcu to scsi bus device handling code, but IMHO this race
should still be possible to hit, at least in theory.
Pavel Dovgalyuk [Tue, 8 Dec 2020 09:10:58 +0000 (12:10 +0300)]
icount: improve exec nocache usage
cpu-exec tries to execute TB without caching when current
icount budget is over. But sometimes refilled budget is big
enough to try executing cached blocks.
This patch checks that instruction budget is big enough
for next block execution instead of just running cpu_exec_nocache.
It halves the number of calls of cpu_exec_nocache function
during tested OS boot scenario.
Thomas Huth [Thu, 10 Dec 2020 15:58:06 +0000 (16:58 +0100)]
docs/system: Move the list of removed features to a separate file
Otherwise there is a chance that new deprecated features get added
to the list of removed features at the end of the file by accident.
It's way less confusing if the removed features reside in a separate
file.
Paolo Bonzini [Tue, 1 Dec 2020 14:29:56 +0000 (09:29 -0500)]
memory: clamp cached translation in case it points to an MMIO region
In using the address_space_translate_internal API, address_space_cache_init
forgot one piece of advice that can be found in the code for
address_space_translate_internal:
/* MMIO registers can be expected to perform full-width accesses based only
* on their address, without considering adjacent registers that could
* decode to completely different MemoryRegions. When such registers
* exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
* regions overlap wildly. For this reason we cannot clamp the accesses
* here.
*
* If the length is small (as is the case for address_space_ldl/stl),
* everything works fine. If the incoming length is large, however,
* the caller really has to do the clamping through memory_access_size.
*/
address_space_cache_init is exactly one such case where "the incoming length
is large", therefore we need to clamp the resulting length---not to
memory_access_size though, since we are not doing an access yet, but to
the size of the resulting section. This ensures that subsequent accesses
to the cached MemoryRegionSection will be in range.
With this patch, the enclosed testcase notices that the used ring does
not fit into the MSI-X table and prints a "qemu-system-x86_64: Cannot map used"
error.
projects / qemu.git / log