]> Git Repo - qemu.git/history - target/riscv
target/arm: Update SCTLR bits to ARMv9.2
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2022-04-21 Richard HendersonMerge tag 'pull-rx-20220421' of https://gitlab.com...
2022-04-21 Richard HendersonMerge tag 'python-pull-request' of https://gitlab.com...
2022-04-21 Richard HendersonMerge tag 'pull-qapi-2022-04-21' of git://repo.or.cz...
2022-04-21 Richard HendersonMerge tag 'misc-pull-request' of gitlab.com:marcandre...
2022-04-21 Marc-André Lureaucompiler.h: replace QEMU_NORETURN with G_NORETURN
2022-04-21 Richard HendersonMerge tag 'pull-ppc-20220420-2' of https://gitlab.com...
2022-04-20 Richard HendersonMerge tag 'pull-tcg-20220420' of https://gitlab.com...
2022-04-20 Richard HendersonMerge tag 'pull-log-20220420' of https://gitlab.com...
2022-04-20 Richard Hendersonexec/translator: Pass the locked filepointer to disas_l...
2022-04-20 Richard HendersonMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2022-04-06 Marc-André LureauRemove qemu-common.h include from most units
2022-04-06 Marc-André LureauMove CPU softfloat unions to cpu-float.h
2022-04-06 Marc-André LureauReplace config-time define HOST_WORDS_BIGENDIAN
2022-04-02 Peter MaydellMerge tag 'pull-request-2022-04-01' of https://gitlab...
2022-04-01 Peter MaydellMerge tag 'pull-target-arm-20220401' of https://git...
2022-04-01 Peter MaydellMerge tag 'pull-riscv-to-apply-20220401' of github...
2022-03-31 Yueh-Ting (eop)... target/riscv: rvv: Add missing early exit condition...
2022-03-31 Palmer Dabbelttarget/riscv: Avoid leaking "no translation" TLB entries
2022-03-09 Peter MaydellMerge remote-tracking branch 'remotes/legoater/tags...
2022-03-09 Peter MaydellMerge remote-tracking branch 'remotes/mcayland/tags...
2022-03-09 Peter MaydellMerge remote-tracking branch 'remotes/ericb/tags/pull...
2022-03-09 Peter MaydellMerge remote-tracking branch 'remotes/philmd/tags/mips...
2022-03-08 Peter MaydellMerge remote-tracking branch 'remotes/mst/tags/for_upst...
2022-03-08 Peter MaydellMerge remote-tracking branch 'remotes/jsnow-gitlab...
2022-03-08 Peter MaydellMerge remote-tracking branch 'remotes/thuth-gitlab...
2022-03-08 Peter MaydellMerge remote-tracking branch 'remotes/pmaydell/tags...
2022-03-08 Peter MaydellMerge remote-tracking branch 'remotes/kraxel/tags/seabi...
2022-03-08 Peter MaydellMerge remote-tracking branch 'remotes/cschoenebeck...
2022-03-07 Peter MaydellMerge remote-tracking branch 'remotes/philmd/tags/abstr...
2022-03-06 Philippe Mathieu... target: Use ArchCPU as interface to target CPU
2022-03-06 Philippe Mathieu... target: Introduce and use OBJECT_DECLARE_CPU_TYPE(...
2022-03-06 Philippe Mathieu... target: Use CPUArchState as interface to target-specifi...
2022-03-06 Philippe Mathieu... target: Include missing 'cpu.h'
2022-03-06 Philippe Mathieu... misc: Add missing "sysemu/cpu-timers.h" include
2022-03-04 Peter MaydellMerge remote-tracking branch 'remotes/kraxel/tags/kraxe...
2022-03-04 Peter MaydellMerge remote-tracking branch 'remotes/nvme/tags/nvme...
2022-03-04 Peter MaydellMerge remote-tracking branch 'remotes/rth-gitlab/tags...
2022-03-03 Peter MaydellMerge remote-tracking branch 'remotes/alistair/tags...
2022-03-03 Weiwei Litarget/riscv: expose zfinx, zdinx, zhinx{min} properties
2022-03-03 Weiwei Litarget/riscv: add support for zhinx/zhinxmin
2022-03-03 Weiwei Litarget/riscv: add support for zdinx
2022-03-03 Weiwei Litarget/riscv: add support for zfinx
2022-03-03 Weiwei Litarget/riscv: hardwire mstatus.FS to zero when enable...
2022-03-03 Weiwei Litarget/riscv: add cfg properties for zfinx, zdinx and...
2022-03-03 Philipp Tomsichtarget/riscv: fix inverted checks for ext_zb[abcs]
2022-02-28 Peter MaydellMerge remote-tracking branch 'remotes/legoater/tags...
2022-02-23 Peter MaydellMerge remote-tracking branch 'remotes/berrange-gitlab...
2022-02-22 Peter MaydellMerge remote-tracking branch 'remotes/lvivier-gitlab...
2022-02-22 Peter MaydellMerge remote-tracking branch 'remotes/thuth-gitlab...
2022-02-21 Peter MaydellMerge remote-tracking branch 'remotes/bonzini-gitlab...
2022-02-21 Philippe Mathieu... target: Add missing "qemu/timer.h" include
2022-02-16 Peter MaydellMerge remote-tracking branch 'remotes/alistair/tags...
2022-02-16 Weiwei Litarget/riscv: add support for svpbmt extension
2022-02-16 Weiwei Litarget/riscv: add support for svinval extension
2022-02-16 Weiwei Litarget/riscv: add support for svnapot extension
2022-02-16 Weiwei Litarget/riscv: add PTE_A/PTE_D/PTE_U bits check for...
2022-02-16 Guo Rentarget/riscv: Ignore reserved bits in PTE for RV64
2022-02-16 Anup Pateltarget/riscv: Allow users to force enable AIA CSRs...
2022-02-16 Anup Pateltarget/riscv: Implement AIA IMSIC interface CSRs
2022-02-16 Anup Pateltarget/riscv: Implement AIA xiselect and xireg CSRs
2022-02-16 Anup Pateltarget/riscv: Implement AIA mtopi, stopi, and vstopi...
2022-02-16 Anup Pateltarget/riscv: Implement AIA interrupt filtering CSRs
2022-02-16 Anup Pateltarget/riscv: Implement AIA hvictl and hviprioX CSRs
2022-02-16 Anup Pateltarget/riscv: Implement AIA CSRs for 64 local interrupt...
2022-02-16 Anup Pateltarget/riscv: Implement AIA local interrupt priorities
2022-02-16 Anup Pateltarget/riscv: Allow AIA device emulation to set ireg...
2022-02-16 Anup Pateltarget/riscv: Add defines for AIA CSRs
2022-02-16 Anup Pateltarget/riscv: Add AIA cpu feature
2022-02-16 Anup Pateltarget/riscv: Allow setting CPU feature from machine...
2022-02-16 Anup Pateltarget/riscv: Improve delivery of guest external interrupts
2022-02-16 Anup Pateltarget/riscv: Implement hgeie and hgeip CSRs
2022-02-16 Anup Pateltarget/riscv: Implement SGEIP bit in hip and hie CSRs
2022-02-16 Anup Pateltarget/riscv: Fix trap cause for RV32 HS-mode CSR acces...
2022-02-16 LIU Zhiweitarget/riscv: Fix vill field write in vtype
2022-02-16 Philipp Tomsichtarget/riscv: Add XVentanaCondOps custom extension
2022-02-16 Philipp Tomsichtarget/riscv: iterate over a table of decoders
2022-02-16 Philipp Tomsichtarget/riscv: access cfg structure through DisasContext
2022-02-16 Philipp Tomsichtarget/riscv: access configuration through cfg_ptr...
2022-02-16 Philipp Tomsichtarget/riscv: riscv_tr_init_disas_context: copy pointer...
2022-02-16 Philipp Tomsichtarget/riscv: refactor (anonymous struct) RISCVCPU...
2022-02-16 Frédéric Pétrottarget/riscv: correct "code should not be reached"...
2022-02-02 Peter MaydellMerge remote-tracking branch 'remotes/hdeller/tags...
2022-01-21 Peter MaydellMerge remote-tracking branch 'remotes/alistair/tags...
2022-01-21 LIU Zhiweitarget/riscv: Relax UXL field for debugging
2022-01-21 LIU Zhiweitarget/riscv: Enable uxl field write
2022-01-21 LIU Zhiweitarget/riscv: Set default XLEN for hypervisor
2022-01-21 LIU Zhiweitarget/riscv: Adjust scalar reg in vector with XLEN
2022-01-21 LIU Zhiweitarget/riscv: Adjust vector address with mask
2022-01-21 LIU Zhiweitarget/riscv: Fix check range for first fault only
2022-01-21 LIU Zhiweitarget/riscv: Remove VILL field in VTYPE
2022-01-21 LIU Zhiweitarget/riscv: Adjust vsetvl according to XLEN
2022-01-21 LIU Zhiweitarget/riscv: Split out the vill from vtype
2022-01-21 LIU Zhiweitarget/riscv: Split pm_enabled into mask and base
2022-01-21 LIU Zhiweitarget/riscv: Calculate address according to XLEN
2022-01-21 LIU Zhiweitarget/riscv: Alloc tcg global for cur_pm[mask|base]
2022-01-21 LIU Zhiweitarget/riscv: Create current pm fields in env
2022-01-21 LIU Zhiweitarget/riscv: Adjust csr write mask with XLEN
2022-01-21 LIU Zhiweitarget/riscv: Relax debug check for pm write
2022-01-21 LIU Zhiweitarget/riscv: Use gdb xml according to max mxlen
2022-01-21 LIU Zhiweitarget/riscv: Extend pc for runtime pc write
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