Parallel NOR Flash patches queue
- Code movement to ease maintainability
- Tracing improvements
# gpg: Signature made Thu 18 Mar 2021 15:44:12 GMT
# gpg: using RSA key
FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/pflash-
20210318:
hw/block/pflash_cfi: Replace DPRINTF with trace events
hw/block/pflash_cfi01: Correct the type of PFlashCFI01.ro
hw/block/pflash_cfi01: Clarify trace events
hw/block/pflash_cfi02: Add DeviceReset method
hw/block/pflash_cfi02: Factor out pflash_reset_state_machine()
hw/block/pflash_cfi02: Rename register_memory(true) as mode_read_array
hw/block/pflash_cfi02: Open-code pflash_register_memory(rom=false)
hw/block/pflash_cfi02: Set rom_mode to true in pflash_setup_mappings()
hw/block/pflash_cfi02: Extract pflash_cfi02_fill_cfi_table()
hw/block/pflash_cfi01: Extract pflash_cfi01_fill_cfi_table()
hw/block/pflash_cfi: Fix code style for checkpatch.pl
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>