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hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI
authorPeter Maydell <[email protected]>
Thu, 11 Jan 2018 13:25:40 +0000 (13:25 +0000)
committerPeter Maydell <[email protected]>
Thu, 11 Jan 2018 13:25:40 +0000 (13:25 +0000)
commitf1945632b43e36bd9f3e0c2feb0e5b152be7ed91
treeb2d4f343b5fb3b850cd459827e4330ca79f37b64tree | snapshot
parent2eea841c11096e8dcc457b80e21f3fbdc32d2590commit | diff
hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI

The GICv3 specification says that reserved register addresses
should RAZ/WI. This means we need to return MEMTX_OK, not MEMTX_ERROR,
because now that we support generating external aborts the
latter will cause an abort on new board models.

Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Message-id: 1513183941[email protected]
Reviewed-by: Alistair Francis <[email protected]>
hw/intc/arm_gicv3_dist.c diff | blob | blame | history
hw/intc/arm_gicv3_its_common.c diff | blob | blame | history
hw/intc/arm_gicv3_redist.c diff | blob | blame | history
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