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target/riscv: Correctly implement TSR trap
authorAlistair Francis <[email protected]>
Tue, 21 Jan 2020 05:36:57 +0000 (21:36 -0800)
committerPalmer Dabbelt <[email protected]>
Tue, 17 Mar 2020 00:03:13 +0000 (17:03 -0700)
commited5abf46b3c414ef58e647145f19b3966700b206
tree118e2d70b680eda5c99f5ecdc0c43414988b8f4ctree | snapshot
parenta98135f727595382e200d04c2996e868b7925a01commit | diff
target/riscv: Correctly implement TSR trap

As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.

This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.

Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Jonathan Behrens <[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
target/riscv/op_helper.c diff | blob | blame | history
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