]> Git Repo - qemu.git/commit
target-mips: raise RI exceptions when FIR.PS = 0
authorYongbok Kim <[email protected]>
Wed, 24 Jun 2015 23:24:18 +0000 (00:24 +0100)
committerLeon Alrae <[email protected]>
Fri, 26 Jun 2015 08:22:05 +0000 (09:22 +0100)
commite29c962804c4dd3fabd44e703aa87eec555ed910
treeec1c39ea7838439a678e688ae478b707ca2e9a9a
parent6893f07466b045c5faf314ab9e57ef3b4a6f9e49
target-mips: raise RI exceptions when FIR.PS = 0

64-bit paired-single (PS) floating point data type is optional in the
pre-Release 6.
It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
(The PS data type is removed in the Release 6.)
Loongson-2E and Loongson-2F don't have any implementation field in
FCSR0(FIR) but do support PS data format, therefore for these cores RI will
not be signalled regardless of PS bit.

Signed-off-by: Yongbok Kim <[email protected]>
Reviewed-by: Leon Alrae <[email protected]>
Reviewed-by: Aurelien Jarno <[email protected]>
Signed-off-by: Leon Alrae <[email protected]>
target-mips/translate.c
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