target/riscv: Add V extension state description

target/riscv: Add V extension state description

In the case of supporting V extension, add V extension description
to vmstate_riscv_cpu.

Signed-off-by: Yifei Jiang <[email protected]>
Signed-off-by: Yipeng Yin <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20201026115530[email protected]
Signed-off-by: Alistair Francis <[email protected]>