]> Git Repo - qemu.git/commit
target/riscv: Move the hfence instructions to the rvh decode
authorAlistair Francis <[email protected]>
Fri, 3 Apr 2020 21:05:01 +0000 (14:05 -0700)
committerAlistair Francis <[email protected]>
Fri, 19 Jun 2020 15:24:07 +0000 (08:24 -0700)
commitb8429ded723ec52568e05f6a24ed78c93224687c
treecbb8c8aed41e4ea73000e8e04123059855697586
parent88914473e748db20d8e18b9735f647a683319fa6
target/riscv: Move the hfence instructions to the rvh decode

Also correct the name of the VVMA instruction.

Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
target/riscv/insn32.decode
target/riscv/insn_trans/trans_privileged.inc.c
target/riscv/insn_trans/trans_rvh.inc.c [new file with mode: 0644]
target/riscv/translate.c
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