aspeed_sdmc: Set 'cache initial sequence' always true

aspeed_sdmc: Set 'cache initial sequence' always true

The SDRAM training routine sets the 'Enable cache initial' bit, and then
waits for the 'cache initial sequence' to be done.

Have it always return done, as there is no other side effects that the
model needs to implement. This allows the upstream u-boot training to
proceed on the ast2500-evb board.

Signed-off-by: Joel Stanley <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Tested-by: Cédric Le Goater <[email protected]>
Message-id: 20180807075757[email protected]
Signed-off-by: Peter Maydell <[email protected]>