Git Repo - qemu.git/commit - target/riscv/internals.h

]> Git Repo - qemu.git/commit - target/riscv/internals.h

author	LIU Zhiwei <[email protected]>
	Wed, 1 Jul 2020 15:25:44 +0000 (23:25 +0800)
committer	Alistair Francis <[email protected]>
	Thu, 2 Jul 2020 16:19:33 +0000 (09:19 -0700)
commit	9fc08be626a96ae1ac0cffb22f30ae652c1c645a
tree	386fddf1edd73d8f4b55e7abf057cb76180f3d39	tree \| snapshot
parent	90355f391d979ccd95d09ab42f647f103a3dbe69	commit \| diff

target/riscv: integer scalar move instruction

Signed-off-by: LIU Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20200701152549 [email protected]>
Signed-off-by: Alistair Francis <[email protected]>

target/riscv/insn32.decode		diff \| blob \| blame \| history
target/riscv/insn_trans/trans_rvv.inc.c		diff \| blob \| blame \| history
target/riscv/internals.h		diff \| blob \| blame \| history

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