]> Git Repo - qemu.git/commit
hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1
authorPeter Maydell <[email protected]>
Thu, 12 May 2022 15:14:53 +0000 (16:14 +0100)
committerPeter Maydell <[email protected]>
Thu, 19 May 2022 15:19:02 +0000 (16:19 +0100)
commit9c6f933e71ccfde036d7e19c1ddc2b1a82cc45c0
treec6c17062fef12afc84b4a79f617c1ab04cb18c4f
parent272f75e89088c968c861fef516a4ebc70846dcd5
hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1

As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
virtual priority bit setting, not the physical priority bit setting.
(For QEMU currently we always implement 8 bits of physical priority,
so the PRIbits field was previously 7, since it is defined to be
"priority bits - 1".)

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20220512151457.3899052[email protected]
Message-id: 20220506162129.2896966[email protected]
hw/intc/arm_gicv3_cpuif.c
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