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target/arm: Implement HSTR.TJDBX
authorPeter Maydell <[email protected]>
Mon, 16 Aug 2021 18:03:05 +0000 (19:03 +0100)
committerPeter Maydell <[email protected]>
Thu, 26 Aug 2021 16:02:01 +0000 (17:02 +0100)
commit8e228c9e4bcfea634e7ee404f4d13136d2072c71
treedc82dfa1366d417dd3f1fe3c6e35365104ced5b7tree | snapshot
parentcc7613bfaa1f653a6eb6ff50ac45d5c5fd717052commit | diff
target/arm: Implement HSTR.TJDBX

In v7A, the HSTR register has a TJDBX bit which traps NS EL0/EL1
access to the JOSCR and JMCR trivial Jazelle registers, and also BXJ.
Implement these traps. In v8A this HSTR bit doesn't exist, so don't
trap for v8A CPUs.

Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20210816180305[email protected]
target/arm/cpu.h diff | blob | blame | history
target/arm/helper.c diff | blob | blame | history
target/arm/helper.h diff | blob | blame | history
target/arm/op_helper.c diff | blob | blame | history
target/arm/syndrome.h diff | blob | blame | history
target/arm/translate.c diff | blob | blame | history
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