]> Git Repo - qemu.git/commit
target/arm: Fix routing of singlestep exceptions
authorPeter Maydell <[email protected]>
Thu, 15 Aug 2019 08:46:42 +0000 (09:46 +0100)
committerPeter Maydell <[email protected]>
Fri, 16 Aug 2019 13:02:49 +0000 (14:02 +0100)
commit8bd587c1066f4456ddfe611b571d9439a947d74c
tree3e5c1ce53b10d7b0fd221fc8e186d5e9ac31d1f0
parentc1d5f50f094ab204accfacc2ee6aafc9601dd5c4
target/arm: Fix routing of singlestep exceptions

When generating an architectural single-step exception we were
routing it to the "default exception level", which is to say
the same exception level we execute at except that EL0 exceptions
go to EL1. This is incorrect because the debug exception level
can be configured by the guest for situations such as single
stepping of EL0 and EL1 code by EL2.

We have to track the target debug exception level in the TB
flags, because it is dependent on CPU state like HCR_EL2.TGE
and MDCR_EL2.TDE. (That we were previously calling the
arm_debug_target_el() function to determine dc->ss_same_el
is itself a bug, though one that would only have manifested
as incorrect syndrome information.) Since we are out of TB
flag bits unless we want to expand into the cs_base field,
we share some bits with the M-profile only HANDLER and
STACKCHECK bits, since only A-profile has this singlestep.

Fixes: https://bugs.launchpad.net/qemu/+bug/1838913
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Tested-by: Alex Bennée <[email protected]>
Message-id: 20190805130952[email protected]
target/arm/cpu.h
target/arm/helper.c
target/arm/translate-a64.c
target/arm/translate.c
target/arm/translate.h
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