Git Repo - qemu.git/commit - target/riscv/csr.c

]> Git Repo - qemu.git/commit - target/riscv/csr.c

author	Alistair Francis <[email protected]>
	Wed, 16 Dec 2020 18:23:02 +0000 (10:23 -0800)
committer	Alistair Francis <[email protected]>
	Fri, 18 Dec 2020 05:56:44 +0000 (21:56 -0800)
commit	8987cdc48120c268568cdf87ba38591809d3efd1
tree	58e0517b00d2a16a56d21cb15c6220a9434660cc	tree \| snapshot
parent	f08c7ff3dc552d423439284a725f384b85b99062	commit \| diff

target/riscv: csr: Remove compile time XLEN checks

Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Palmer Dabbelt <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Tested-by: Bin Meng <[email protected]>
Message-id: 7371180970b7db310d3a1da21d03d33499c2beb0.1608142916 [email protected]

target/riscv/cpu_bits.h		diff \| blob \| blame \| history
target/riscv/csr.c		diff \| blob \| blame \| history

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