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target-mips: add exception base to MIPS CPU
authorLeon Alrae <[email protected]>
Thu, 9 Jun 2016 09:46:50 +0000 (10:46 +0100)
committerLeon Alrae <[email protected]>
Tue, 12 Jul 2016 08:10:14 +0000 (09:10 +0100)
commit89777fd10fc3dd573c3b4d1b2efdd10af823c001
tree0b761b2e015b2925b09528a20cab1035a53ce79dtree | snapshot
parent19494f811a43c6bc226aa272d86300d9229224fecommit | diff
target-mips: add exception base to MIPS CPU

Replace hardcoded 0xbfc00000 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.

Signed-off-by: Leon Alrae <[email protected]>
target-mips/cpu.h diff | blob | blame | history
target-mips/helper.c diff | blob | blame | history
target-mips/translate.c diff | blob | blame | history
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